DETAILED ACTION
Claims 1-27 were restricted. Claims 1-18 are elected.
Claims 1-2, 4, 10, 15-16, 18 are amended. Claim 30 is canceled.
Claims 1-29, 31-34 are pending. Claim(s) 19-27, 32-34 are withdrawn from consideration.
Priority: 12/7/2022(P)
Assignee: Hyannis Port
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 4/2/2026 has been entered.
Restriction
Claims 1-18 (1st group/elected) were restricted because Claim 1 recited, ‘An electronic data processing system comprising: a data processor…., a memory accessed by the data processor’. The spec defines ‘a memory’ to include an off-chip DRAM and an on-chip BRAM.
Claim 1 also recited, ‘each tile comprising an array of access nodes that represent open orders for a given ISP….one or more head and/or tail references that organize the array of access nodes into one or more prioritized collections of active and/or free access nodes’.
Claim 1 recited an organization of tiles. To minimize latency, the tiles (each tile stores order data for all open orders of a particular ISP) were already loaded into the BRAM. There was no recitation of request processing for an access node. There was no recitation of dynamic loading of a tile from DRAM to BRAM.
But amended Claim 1 recites limitations to process a request for an access node, including ‘accessing the one or more memories to locate the tile….’, which does not exclude dynamic loading of the tile. This is similar to Claim 19 (non-elected) and Figs. 6-7 of the spec (non-elected), which disclose processing a request for an access node by accessing ‘one or more memories’.
Amended claim 1 limitations ‘receiving a request… accessing one or more memories…,locating…,returning the….node’ incorporate at least Fig. 6, steps 510,520,550,560 and Fig. 7, steps 551,552,554,555 of the spec (both non-elected). Therefore these new limitations must be cancelled.
Amended independent Claim 18 recites ‘non-transitory computer-readable storage medium’, but the scope is unclear. The limitations, ‘receiving a request…., locating….the requested access node…, returning….’, incorporate at least Fig. 6, steps 510,520,550,560 and Fig. 7, steps 551,552,554,555 of the spec. Therefore the new(last 3) limitations in claim 18 must be cancelled.
Under MPEP 819 and 37 CFR 1.145, the incorporation of limitations from withdrawn, non-elected claims into the elected independent claim represents an impermissible attempt to shift to a distinct, non-elected invention without filing a divisional application.
Dependent claims 32-34 are new.
Claim 32 recites limitations that incorporate at least Fig. 6, steps 520,530 in the spec (non-elected), and claims 19, 21 (non-elected).
Claim 33 recites limitations that incorporate at least Fig. 6, step 550 and Fig. 7, steps 551,552,554,555 in the spec (both non-elected).
Claim 34 refers to pre-fetching when processing the request. Claim 34 incorporates at least Fig. 6, step 530, Para-0165 in the spec (non-elected).
New claims 32-34 reference and attempt to claim non-elected material from the spec that was previously subject to the initial restriction requirement under MPEP 803. Introducing the non-elected material increases the search burden because a new search for at least the following classifications have to be made: G06Q40/04, G06F16/90348, G06F12/0877, G06Q30/0206, G06Q40/06, G06Q10/087.
The Office prohibits improper shifting. See MPEP 819 and 37 CFR 1.145.
Claims 32-34 are withdrawn from consideration. Please see 37 CFR 1.142(b) and MPEP 821.03.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 1-17 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendments.
1.Amended Claim 1 is rejected for reciting a limitation that is unclear, ambiguous, and indefinite.
Amended Claim 1 recites, ‘a ….system comprising: a data processor….’, ‘one or more memories, accessed by the data processor….’. And further recites, ‘accessing the one or more memories to locate the tile….’.
The phrase ‘one or more memories’ is ambiguous because it is unclear if it means a single memory that is both BRAM and DRAM, or multiple separate memories where one is BRAM and another is DRAM.
Fig. 2, and Paras-0015,0072 of the spec disclose a processor 150 with memory (cache 160). The memory includes an off-chip DRAM and an on-chip BRAM. The spec discloses a singular, ‘a memory’ that contains multiple parts.
Independent claim 1 uses an open-ended, plural ‘one or more’, but does not state whether the processor connects to one hybrid memory or distinct individual memories.
Dependent claim 6 specifies two distinct types of memories (BRAM and DRAM), but the independent claim's broad phrasing leaves it uncertain if the single recited memory can fulfill both roles.
Hence the limitation ‘accessing the one or more memories to locate the tile….’, lacks clear boundaries rendering the scope indefinite. Hence claim 1 is rejected.
Note: Non-elected claim 19 recites, ‘one or more memories accessed by the one or more processors’.
2.Claim 3 is rejected for reciting a limitation that is unclear, ambiguous, and indefinite.
Claim 3 recites, ‘wherein the one or more prioritized collections are sorted based on one or more attributes of the access nodes in the array of access nodes, the one or more attributes including at least a sequence, a time received, or a quantity’.
As recited, the phrase ‘including at least’ creates an ambiguous, open-ended boundary for the ‘one or more attributes’. The phrase ‘including at least’ combined with the open list, ‘a sequence, a time received, or a quantity’, leaves the sorting criteria open to any attribute, thereby failing to determine what attributes are included or excluded.
The open-ended phrase ‘including at least’ within a listing limitation renders the claim indefinite because it makes the exact boundaries of the sorting attributes unclear. Hence claim 3 is rejected.
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claim(s) 1-18 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Note: In the Remarks, the Applicant does not mention the relevant specification paragraph(s) that recite the amendments.
1.Amended Claim 1 is rejected for reciting a limitation that is unsupported by the spec.
Amended Claim 1 recites, ‘a data processor….’, ‘one or more memories, accessed by the data processor….’, ‘….accessing the one or more memories to locate the tile associated with the particular ISP’.
Nowhere does the spec recite these limitations.
Para-0015 of the spec discloses that each memory comprises an on-chip BRAM and an off-chip DRAM. And Fig. 2 shows that each processor 150 includes a memory, cache 160.
The spec discloses a specific dual-hierarchy memory architecture comprising a BRAM and a DRAM. But claim 1 broadly recites ‘one or more memories’ without reciting the distinct BRAM/DRAM structure for the claimed processor.
To minimize latency, the spec limits the locating step explicitly within the BRAM. But the claim expands the locating step to occur ‘within the associated tile’ across generic ‘one or more memories’, failing to anchor the physical execution environment disclosed in the spec.
The claim recites a structure of two or more tiles, where each tile organizes an array of two or more access nodes into prioritized collections of active access nodes. The limitations, ‘accessing the one or more memories….’, and ‘locating the access node….’ are functional results (‘locating’, accessing’) that covers all ways to determine the access node, while providing no teaching on how to achieve these results.
The spec fails to clearly show that the inventor was in possession of a processor locating the tile and the associated access node for the ISP across ‘one or more memories’, at the time of filing. The spec fails to provide a specialized search algorithm, flow chart etc., to locate a tile and its access node for the ISP, by traversing the claimed structure, across ‘one or more memories’, by the processor.
The omission of the processor’s specific dual-hierarchy memory, the omission of the locating of the tile and access node for the ISP within the BRAM and the expansion from the dual-hierarchy memory of the claimed processor to generic ‘one or memories’, makes the claim recite a scope beyond the spec. Hence claim 1 recites new matter and is rejected.
2.Amended Claim 1 is rejected for reciting a limitation that is unsupported by the spec.
Amended Claim 1 recites, ‘one or more memories, accessed by the data processor to configure data stored therein as two or more tiles….’.
Nowhere does the spec recite this limitation.
The phrase, ‘two or more tiles’ sets a strict numerical threshold at 2 (2, 3, 4, etc.), and recites a tile configuration undisclosed in the spec.
The spec does not explicitly exclude a single tile system.
The spec describes a permissive configuration (‘may access…..to configure one or more tile data structures’), whereas the claim recites a limited structural/functional relationship (‘configure data stored therein as two or more tiles’), thereby introducing new matter.
The spec fails to demonstrate that the inventor was in possession of the specific limitation of configuring data stored into two or more tiles, at the time of filing.
Amended claim 1 further recites, ‘two or more tiles….with each tile further comprising: an array of two or more access nodes….’. The spec does not disclose this limitation. Para-0026 of the spec recites, ‘Each of the one or more tiles may contain an array of access nodes….’.
In summary, the spec fails to demonstrate that the inventor was in possession of the specific limitation of configuring data stored into two or more tiles where each tile comprises two or more access nodes, at the time of filing. Hence claim 1 is rejected. Claim 18 has the same issue. For examination, the spec is followed.
3.Amended Claim 1 is rejected for reciting limitations that are unsupported by the spec.
Amended Claim 1 recites, ‘….one or more memories, accessed by the data processor to configure data stored therein as two or more tiles’, ‘each tile further comprising: an array of two or more access nodes…..the two or more tiles each further….comprising one or more head and/or tail references that organize….prioritized collections of active access nodes'.
The spec does not recite this limitation.
The spec and Claim 1, submitted as part of the original disclosure recites, ‘….a memory, accessed by the data processor to configure data stored therein as one or more tiles, with each tile….: an array of access nodes…., one or more head and/or tail references….prioritized collections of active and/or free access nodes’.
The claim recites that the processor configures data stored in the ‘one or more memories’ as two or more tiles, requires an array of two or more nodes (omits single-node arrays) for each tile, and limits prioritized collections strictly to active nodes (omits free nodes).
On the other hand, the spec recites that the processor configures data stored data in the ‘memory’ as one or more tiles, allows an array of nodes (lacks an explicit numerical floor) and includes prioritized collections of active and/or free nodes.
In addition to the scope mismatch between the claim and the spec, the spec does not provide written description support for the limited claim scope. In other words, the claim fails to capture the full scope of the invention as described, thereby reciting new matter.
Para-0108 of the spec does not omit free nodes.
The functional result ‘organize the array of ….access nodes into one or more prioritized collections of active access nodes’, without teaching how the result is achieved, covers all possible ways to achieve the result.
The broad recitation of ‘a tile header comprising head and/or tail references’ organizing prioritized collections of active access nodes, does not reasonably convey that the inventor was in possession of sorting those collections or sorting them using an open list of ‘a sequence, a time received, or a quantity’ at the time of filing.
The spec also fails to teach how to sort the collections as linked lists and doubly linked lists using sequence, time received, or quantity. Implementing the sorting mechanism, especially for these specific data types requires undue experimentation because the spec provides insufficient algorithms, data structures, or guidance, thereby also failing the enablement prong of 112(a).
The spec casually mentions via one- to two-lines, in different paragraphs, isolated features without clearly explaining how all the claimed elements link with one another and use these features. These casual, one- to two-lines do not fulfill the written description requirement.
The spec fails to disclose the association between physical memory and the logical steps for the search and sort. The spec fails to disclose the physical/logical layout of the ‘organization’ in the ‘one or more memories’, the traversal algorithm, and the hardware-level interface interactions.
In essence, the spec fails to convey that the inventor was in possession of the claimed ‘organization’ and ‘accessing one or more memories….’, and ‘locating the requested access node for the particular ISP within the associated tile’ in this ‘organization’, as recited in amended claim 1, at the time of filing.
4.Amended Claim 18 is rejected for reciting limitations that are unsupported by the spec.
Amended Claim 18 recites, ‘first instructions for receiving an array of two or more access nodes’. The spec does not recite this limitation. Para-0024 of the spec recites, ‘receiving access node data structures’. The spec does not mandate a minimum count of elements (>= 2). The spec does not teach how to ‘receive an array of two or more access nodes’. The spec does not show that the inventor was in possession of ‘receiving an array of two or more access nodes’, at the time of filing.
Claim 18 further recites, ‘second instructions for inserting the access nodes into two or more tiles with each of the two or more tiles further comprising: a tile header comprising one or more at least a head and/or tail references that organize the access nodes in the array into one or more prioritized collections of access nodes’.
The spec does not recite these limitations. The limitations recite receiving the array of two or more access nodes but fails to recite ‘where each of the tiles include an array of the access nodes for a given instrument, side, and price’, as recited in Para-0024 of the spec. Due to this omission the ‘one or more prioritized collections of access nodes’, for each tile, represents an ‘organization’ unsupported by the spec.
The spec fails to convey that the inventor was in possession of the specific ‘organization’ recited in amended claim 18, at the time of filing. Therefore amended Claim 18 is rejected for reciting limitations unsupported by the spec. For examination the spec is followed.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 17-18, 28-29 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Taylor et al (20210174445), Kodde (20150095613) in view of Makhija (20230393784).
As per Claim 1, Taylor discloses an electronic data processing system (Taylor, [0076 - Fig. 8(a) system 800 employs a hardware-accelerated data processing capability through coprocessor 840/FPGA to process financial market depth data]) comprising:
a data processor configured (Taylor, [0078 – In Figs. 8a-8b coprocessor 840 comprises a reconfigurable logic device 802/FPGA]) for processing open orders (Taylor, [0018 – limit orders]) related to financial instruments (Taylor, [0005 - A financial instrument is a contract representing an equity ownership, debt, or credit, typically in relation to a corporate or governmental entity, wherein the contract is saleable. Examples of financial instruments include stocks, bonds, commodities, etc.]);
one or more memories (Taylor, [0086 - In Fig. 9(a), FPGA 802 such as a Xilinx Virtex 5 FPGA is in communication with a memory device 902/DRAM/off-chip]; [0188 - Maintaining the most recently accessed records in a fast, on-chip memory]), accessed by the data processor to configure data stored therein as two or more tiles (Taylor, [0018 - Exchanges keep a sorted listing of limit orders for each financial instrument, known as an order book]; [Claim 1 - The order data structures represent a plurality of order books/2 or more tiles for a plurality of financial instruments]),
with each tile (Taylor, [Claim 1 - each order book]) further comprising:
an array of two or more access nodes (Taylor, [Claim 1 - Each order book corresponds to a financial instrument and comprises a plurality of limit order records/access nodes for its corresponding financial instrument]),
each access node itself representing one of the open orders for a given financial instrument, side, and price (ISP) (Taylor, [0107 - A limit order record 2000 is shown in Fig. 20]);
the two or more tiles (Taylor, [0023 - a plurality of order books for a plurality of financial instruments]) further organized such that the given ISP associated with a first tile is different than the given ISP associated with a second tile (Taylor, [Claim 1 - each order book/tile corresponds to a financial instrument]);
the two or more tiles (Taylor, [0210 – In Figs. 25(a)-(d) a Sorted View Update/SVU module 2500 creates a summary view 2502 of the order books/tiles from the limit order events]) each further including a tile header (Taylor, [0036 - Each entry in an order book has one or more attributes]; [0202 - SVU module 2500 maintains a record/tile header that contains pointers to the top of the bid and ask side of the book, as well as other meta-data that describe the book]) comprising one or more head and/or tail references that organize the array of two or more access nodes into one or more prioritized collections of active access nodes (Taylor, [0206 - Fig. 26 shows an example of a set of positive integers sorted using a B+ tree. All of the stored integers are stored in the leaf nodes. As is well-known in the art, B+ tree nodes vary in size between a minimum and maximum size threshold that is dictated by the branching factor of the tree. The ‘next pointers’ are stored in each leaf node to create a linked list of leaf nodes that may be quickly traversed to retrieve the entire sorted order]);
wherein processing open orders (Taylor, [0022 - Financial market data received on a feed into the ticket plant can be transferred on a streaming basis to the coprocessor for high speed processing]) further comprises:
receiving a request for an access node associated with a particular ISP (Taylor, [0152 – In Fig. 16, ONPA module 1208 receives a limit order event 1600; Here a limit order event is for a limit order/access node associated with a ISP]; [0076 - Coprocessor 840/FPGA receives data that streams into the system 800 from a network 820. Such incoming data comprises a series of financial market data messages, the messages representing events such as limit orders relating to financial instruments]; [0225,0226 - Instructions from client applications are communicated to the hardware interface driver 3106 which then delivers an interleaved stream of financial market data and commands to the coprocessor 840]);
accessing the one or more memories to locate the tile associated with the particular ISP (Taylor, [0103 – In Fig. 16, ONPA module accesses memory 1602 that stores data structures which comprise the various order books/tiles tracked by the system]; [0202 - To locate the top of the book, the SVU module 2500 maintains a record that contains pointers to the top of the bid and ask side of the book, as well as other meta-data that describe the book. The record is located directly by using the symbol map index]);
locating the requested access node for the particular ISP within the associated tile (Taylor, [0152 - The ONPA module 1208, upon receipt of a limit order event 1600, processes data in the limit order event 1600 to access memory 1602 and retrieve a limit order record 2000/access node]);
returning the requested access node for the particular ISP (Taylor, [0226 - Outgoing data from coprocessor 840 returns to the hardware interface driver 3106, from which it can be supplied to MDC driver 3108 for delivery to the client connections and/or delivery to the background and maintenance processing block 3114]).
The spec does not disclose configuring data for two or more tiles where each tile comprises two or more access nodes.
Kodde discloses,
one or more memories (Kodde, [Fig. 7: off-chip DDR RAM/SDRAM]), accessed by the data processor (Kodde, [0124 - Fig. 7 shows a Market Data Processing system 100, in an FPGA on a PCIe Board 70 inside a standard server 71]) to configure data stored therein as tiles (Kodde, [Fig. 2]; [0006 - Market data processing systems using FPGAs comprise an order management device for storing details related to each financial order identified in the input commands in a data structure]),
with each tile (Kodde, [Fig. 2]; [Fig. 6: Keys memory 102]; [Fig. 2: chained orders for the given ISP]) further comprising:
an array of access nodes (Kodde, [0029 – In Fig. 2, a hash table associates each key/Order ID an address, computed using a hash function. This address is then used to retrieve the value/complete order in memory; In Fig. 2, the addresses computed by the hash function represents the array of access nodes]), each access node itself representing one of the open orders (Kodde, [0025 - The limits aggregation and book building device 4 takes each individual order of the same book and side and matches them by price, adding their quantity; This implies that an unmatched order is an open order]) for a given financial instrument, side, and price (ISP)(Kodde, [Fig. 6: Data Memory 103]; [0049 - The information related to each order is maintained in Data Memory 103. The information maintained in the data memory 103 may comprise the instrument, the side .i.e. bid/sell, the price, and the quantity of the order]; [0029 – ‘Collisions’ occur when the hash function generates the same address for more than one Order ID, thereby implying orders with the same given ISP. To handle the collisions, chain/group several orders in each hash table entry; Since each node represents one order, it implies that the chained orders/nodes form a tile for that given ISP]);
the tiles further organized such that the given ISP associated with a first tile is different than the given ISP associated with a second tile (Kodde, [Fig. 2]);
each tile further including one or more head and/or tail references (Kodde, [Fig. 2: index 0-address 007563/head reference, index 6-null/tail; Note: address is equivalent to reference]) that organize the array of access nodes into one or more prioritized collections (Kodde, [Fig. 2: LinkedList1 at index 0, List2 at index2, List3 at indexes 4-5; A linked list is a collection]) of active access nodes (Kodde, [Fig. 2: Indexes 0, 2, 4-5 are active, indexes 1,3,6 are free]; [0112 – In Fig. 6, each line in memory 102 or 103 represents a word of data, thereby implying that occupied lines are active nodes and empty lines are free nodes]).
wherein processing open orders (Kodde, [Fig. 5]) further comprises:
receiving a request for an access node associated with a particular ISP (Kodde, [0093 - In Fig. 5, step 500, a command related to Order ID is received comprising an order identifier and a set of order information; Here Order ID represents the ISP. Since the claim does not recite the format of the request, the citation is a valid interpretation]);
accessing the one or more memories to locate the tile associated with the particular ISP (Kodde, [0054 - Keys Memory 102 and Data Memory 103 share the total memory bandwidth, and an arbiter entity is provided to arbitrate between the concurrent accesses]);
locating the requested access node for the particular ISP within the associated tile (Kodde, [0097 – In Fig. 5, step 501, one or more addresses are computed by hashing the Order ID using a FPGA multiplier. After steps 502, 503, in step 504, the keys in couples {Key, Presence Bit}, in the read data, are compared to the Order ID in the input command]; [0055 - An offset is added to the address of the input of the arbiter, thereby locating the requested access node]);
returning the requested access node for the particular ISP (Kodde, [0099 – In Fig. 5, step 509, if a match is found with a presence bit equal to 1, .i.e. step 505, and if the input command is not an ADD command, .i.e. step 506, address/access node and position at which the key has been found are transmitted/returned to the Data address generation core 106, in step 509; Since the claim does not recite to what component the requested access node for the tile for the ISP is ‘returned’ to, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed. A limits aggregation and book building device aggregates the orders into order books, presents for each instrument a list of orders, aggregated into limits and sorted by price (Kodde, 0023).
Makhija clarifies the prioritized collections as follows,
one or more head and/or tail references (Makhija, [0062 – In Fig. 4, each queue/linked list 440 can have the head 442 and the tail 444]) that organize the array of two or more access nodes (Makhija, [Fig. 4: Head 442A….Head 442L; The head address of each queue can represent the index/address of the array of access nodes]) into one or more prioritized collections of active access nodes (Makhija, [0061 – In Fig. 4, the queues/linked lists are differentiated by their respective priorities, such as queue 440A has the highest priority level, and queue 440L has the lowest priority level]; [0087 – In Fig. 7, processing device 1002 is a FPGA]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the prioritized linked lists of Makhija into the hardware acceleration of financial instruments by Taylor, Kodde, for the benefit of having the data path sequencer/FPGA traverse the memory access command queues or linked lists in the order of their priorities starting with the highest priority queue. In each queue, the sequencer can process the memory access commands starting from the head of the queue (Makhija, 0023).
As per Claim 2, the rejection of claim 1 is incorporated, and Taylor discloses,
wherein the access nodes further contain references to cell data structures that contain additional data that represent the open orders (Taylor, [Fig. 20: shows the fields of a limit order record]; [0119 – In Fig. 20, an interest vector field 2022 serves to identify downstream subscribers that have an interest in the limit order; Here the interest vector field is a logical reference or pointer to those subscribers, as it explicitly associates the order data with the target participant accounts]).
As per Claim 3, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose,
wherein the one or more prioritized collections (Makhija, [0021 - Each queue/linked list is associated with a respective priority level]) are sorted based on one or more attributes of the access nodes in the array of access nodes (Makhija, [0023 - The data path sequencer traverses the memory access command queues/linked lists in the order of their priorities starting with the highest priority queue]), the one or more attributes including at least a sequence, a time received, or a quantity (Makhija, [0061 - The scheduling and ordering of memory access commands is implemented by the central processing unit 410/FPGA using one or more memory access command queues 440A-440L, each of which is represented by a memory buffer that stores a sequence of memory access commands]; [0087 – In Fig. 7, processing device 1002 can be a FPGA]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the prioritized linked lists of Makhija into the hardware acceleration of financial instruments by Taylor, Kodde for the benefit of having the data path sequencer/FPGA traverse the memory access command queues or linked lists in the order of their priorities starting with the highest priority queue. In each queue, the sequencer can process the memory access commands starting from the head of the queue (Makhija, 0023).
As per Claim 17, the rejection of claim 1 is incorporated and Taylor, Kodde, Makhija discloses,
wherein the processor is implemented using fixed logic (Kodde, [0004 - Logic blocks can be configured to perform complex combinational functions, or merely simple basic logical operations like boolean AND, OR, NAND, XOR etc.]), and the fixed logic comprises any of a field programmable gate array (FPGA) and application specific integrated circuit (ASIC) or other embedded hardware technologies (Kodde, [0004 - FPGA is an integrated circuit which can be configured after manufacturing. The configuration is generally specified using a hardware description language/HDL. FPGAs contain a huge number of programmable logic components/logic blocks, and a hierarchy of reconfigurable interconnections that allow the blocks to be ‘wired together’]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
As per Claim 18, Taylor discloses a computer program product in a non-transitory computer-readable storage medium (Taylor, [0086 - In Fig. 9(a), FPGA 802 such as a Xilinx Virtex 5 FPGA is in communication with a memory device 902/DRAM/off-chip]; [0188 - Maintaining the most recently accessed records in a fast, on-chip memory]) for use in a data processing system (Taylor, [0076 - Fig. 8(a) system 800 employs a hardware-accelerated data processing capability through coprocessor 840/FPGA to process financial market depth data]) for processing open orders related to financial instruments (Taylor, [0005 - A financial instrument is a contract representing an equity ownership, debt, or credit, typically in relation to a corporate or governmental entity, wherein the contract is saleable. Examples of financial instruments include stocks, bonds, commodities, etc.]),
the computer program product comprising:
first instructions (Taylor, [0022 - Financial market data received on a feed into the ticket plant is transferred on a streaming basis to the coprocessor for high speed processing]) for receiving an array of two or more access nodes (Taylor, [Claim 1 - Each order book corresponds to a financial instrument and comprises a plurality of limit order records/access nodes for its corresponding financial instrument]; [0079 – In Figs. 8a-8b, FAMs 850i of the FAM chain 850 are configured to perform specified data processing operations on any data that streams through the chain 850 from firmware socket module 804]; [0082 - The FAM chain 850 comprises a plurality of firmware application modules/FAMs 850a,850b,….that are arranged in a pipelined sequence; Streaming sequential data packets through pipelined hardware blocks implies receiving an array of two or more access nodes]),
each access node (Taylor, [0107 - A limit order record 2000 is shown in Fig. 20]) itself referencing a cell data structure representing one of the open orders associated with a given instrument, side and price (ISP) (Taylor, [Fig. 20: shows the fields of a limit order record]; [0119 - An interest vector field 2022 serves to identify downstream subscribers that have an interest in the limit order; Here the interest vector field is a logical reference or pointer to those subscribers, as it explicitly associates the order data with the target participant accounts]);
second instructions for inserting the access nodes into two or more tiles (Taylor, [0202 - inserting an entry into the book/tile moves entries above the insertion location up one memory location]), and organizing the two or more tiles (Taylor, [0023 - a plurality of order books for a plurality of financial instruments]) such that the given ISP for a first tile is different than the given ISP for a second tile (Taylor, [Claim 1 - each order book/tile corresponds to a financial instrument]),
with each of the two or more tiles further comprising:
a tile header (Taylor, [0036 - Each entry in an order book has one or more attributes]; [0202 - SVU module 2500 maintains a record/tile header that contains pointers to the top of the bid and ask side of the book, as well as other meta-data that describe the book]) comprising one or more head and/or tail references that organize the access nodes in the array into one or more prioritized collections of access nodes (Taylor, [0206 - Fig. 26 shows an example of a set of positive integers sorted using a B+ tree. All of the stored integers are stored in the leaf nodes. As is well-known in the art, B+ tree nodes vary in size between a minimum and maximum size threshold that is dictated by the branching factor of the tree. The ‘next pointers’ are stored in each leaf node to create a linked list of leaf nodes that may be quickly traversed to retrieve the entire sorted order]);
third instructions for processing the array of access nodes (Taylor, [0022 - Financial market data received on a feed into the ticket plant can be transferred on a streaming basis to the coprocessor for high speed processing]) by:
The remaining limitations are similar to claim 1 and hence the same mappings are incorporated.
As per Claim 28, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija discloses,
wherein the tiles further comprise: metadata fields that relate to additional order data for the given instrument, side and price (Kodde, [0049,0050 - The information related to each order is maintained in Data Memory 103. The information maintained in the data memory 103 comprises the instrument, the side, i.e. bid/sell, the price, and the quantity of the order]; [0025 - The size or quantity of an order designates the number of shares to be bought or sold]; [0024 - An aggregated limit can also have an ‘order count’ property reflecting the number of orders that have been aggregated in this limit]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
As per Claim 29, the rejection of claim 28 is incorporated, and Taylor, Kodde, Makhija disclose,
wherein the metadata fields represent an aggregate number of shares (Kodde, [0025 - The size or quantity of an order designates the number of shares to be bought or sold]) in the tile and a number of open orders in the tile (Kodde, [0025 - The limits aggregation and book building device 4 takes each individual order of the same book and side, bid or ask, and matches them by price, adding their quantity; Since claim does not define ‘open order’, the citation is a valid interpretation]; [0024 - An aggregated limit can also have an ‘order count’ property reflecting the number of orders that have been aggregated in this limit]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
Claim 31 is rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Taylor et al (20210174445), Kodde (20150095613) in view of Makhija (20230393784) and Hirose et al (20200250726).
As per Claim 31, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose storing tiles with attributes.
Hirose further discloses,
wherein the tile header further comprises fields indicating the given ISP associated with the tile (Hirose, [Fig. 9: node 135 is a tile with sell price or buy price]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the tile header of Hirose into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija, for the benefit of using the B-tree structure to store the tiles as the B-tree structure can store the tiles contiguously in increasing or decreasing sequential order by price (Hirose, 0114).
Claims 6-9 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Taylor et al (20210174445), Kodde (20150095613) in view of Makhija (20230393784) and Sukhwani et al (‘Database Analytics: A Reconfigurable-Computing Approach’, 2014, IEEE, Pgs. 19-29).
As per Claim 6, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose,
the one or more memories ([See 112(b)]) include on-chip Block Random Access Memory (Block RAM) located on a semiconductor chip with the processor (Kodde, [0033 - internal FPGA memory]);
the one or more memories ([See 112(b)]) also includes off-chip Dynamic Random Access Memory (DRAM) that is not located on the semiconductor chip with the processor (Kodde, [Fig. 7: off-chip DDR RAM/SDRAM]);
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
Sukhwani further discloses,
the one or more memories include on-chip Block Random Access Memory (Block RAM) located on a semiconductor chip with the processor (Sukhwani, [Pg. 21, Col. 2, Para-1 - FPGA block BRAM/on-chip is limited]; [Pg. 24, Col. 1, Para-3 – Fig. 4 shows the two phases of FPGA hash-join. The join columns and the row addresses are stored in the address table in the FPGA BRAM]; [Fig. 5]);
the one or more memories also include off-chip Dynamic Random Access Memory (DRAM) that is not located on the semiconductor chip with the processor (Sukhwani, [Fig. 2 shows an off-chip DRAM]; [Pg. 21, Col. 2, Para-1 - The full records are stored in on-card/offchip DRAM]; [Pg. 24, Col. 1, Para-3 – In Fig. 4, the full rows are stored in off-chip DRAM]);
and two or more tiles are stored contiguously such that they are accessible by a single address parameter (Sukhwani, [Pg. 24, Col. 1, Para-3 – In Fig. 4, rows hashing to the same position are chained in the address table]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the hardware acceleration of Sukhwani into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of using a hardware acceleration approach to offload and accelerate the most CPU-intensive operations in analytics queries on an FPGA. The FPGA operates on a database management system’s in-memory data, which is the most up-todate copy of the data, for real-time analytics alongside OLTP/online transaction processing which includes market data processing (Sukhwani, Pg. 20, Col. 1, Para-2).
As per Claim 7, the rejection of claim 6 is incorporated, and Taylor, Kodde Makhija, Sukhwani disclose,
wherein a source address (Kodde, [Abstract - receiving an input command for an asset comprising an asset identifier and asset information; It is well-known that the input command may include a source address]) and destination address for the processor to access the one or more memories include one or more of an off-chip DRAM address or an on-chip Block RAM address (Kodde, [Fig. 5: step 510]; [Abstract - Computing a data address/DRAM/destination to the data memory for the asset from the address/source address and position in the keys memory at which an entry has been found or allocated for the asset]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija, Sukhwani for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
As per Claim 8, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose,
wherein the one or more tiles further comprise a predetermined number of access nodes (Kodde, [Fig. 6: Keys Memory 102]; [Fig. 3: entry allocation core 104]; [0070 - If the entry allocation core 104 tries to add an entry into the hash table and no slot is available, then the memory is full; This implies a predetermined number of access nodes for each tile]),
such that a total number of access nodes for a given instrument, side and price extends beyond the predetermined number of access nodes (Kodde, [0029 - There are generally more possible IDs than there are available memory locations. With such data structures, ‘collisions’ often occur when the hash function generates the same address for more than one Order ID, thereby implying that the total number of access nodes extends/greater than the predetermined number of access nodes]; [0025 - Order books can comprise orders from the same instrument on different markets/consolidated books]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the asset management device of Kodde into the hardware acceleration of financial instruments by Taylor, Makhija for the benefit of configuring the asset management device to store details related to each received order so as to retrieve the orders when they are needed (Kodde, 0023).
Sukhwani further discloses,
and a selected tile (Sukhwani, [Fig. 2: Tile0]) contains a reference to another one (Sukhwani, [Fig. 2: Tile1]) of the tiles (Sukhwani, [Pg. 24, Col. 1, Para-3 - The join columns and the row addresses are stored in the address table in the FPGA BRAM]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the hardware acceleration of Sukhwani into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of using a hardware acceleration approach to offload and accelerate the most CPU-intensive operations in analytics queries on an FPGA (Sukhwani, Pg. 20, Col. 1, Para-2).
As per Claim 9, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system.
Sukhwani further discloses,
wherein at least one access node contained within a selected tile (Sukhwani, [Fig. 2: Tile0]) is accessible to the processor before an entire transfer of the selected tile is complete (Sukhwani, [Pg. 24, Col. 1, Para-3 – In Fig. 4, the full rows are stored in off-chip DRAM, wherea the join columns and the row addresses are stored in the address table in the FPGA BRAM, thereby implying that atleast one access node/address is accessible to the processor before an entire transfer of the selected tile is complete]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the hardware acceleration of Sukhwani into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of using a hardware acceleration approach to offload and accelerate the most CPU-intensive operations in analytics queries on an FPGA (Sukhwani, Pg. 20, Col. 1, Para-2).
Claims 4-5, 10-11, 14 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Taylor et al (20210174445), Kodde (20150095613) in view of Makhija (20230393784) and Nault (20010044762).
As per Claim 4, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose,
wherein the one or more prioritized collections are each implemented as a linked list (Makhija, [0062 – In Fig. 4, the memory access command queues 440 are linked lists]), with each linked list further comprising selected ones of the head and/or tail references (Makhija, [0062 - Each queue 440 has the head 442/reference and the tail 444/reference]),
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the prioritized linked lists of Makhija into the hardware acceleration of financial instruments by Taylor, Kodde, for the benefit of having the data path sequencer/FPGA traverse the memory access command queues or linked lists in the order of their priorities starting with the highest priority queue. In each queue, the sequencer can process the memory access commands starting from the head of the queue (Makhija, 0023).
Nault further discloses,
and each access node in the array including a reference to a next access node or a previous access node in the linked list (Nault, [0065 – In Fig. 5A, the linked list 501 is distinct and contains the pointers NEXT 502 and PREVIOUS 503 and a pointer to the chart structure 504]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the doubly linked lists of Nault into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of providing a set of accounting data, organizing the accounting data using doubly linked lists into a central memory of a computer and generating a financial statement (Nault, 0021).
As per Claim 5, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system using prioritized collections of lists.
Nault further discloses,
wherein the one or more prioritized collections are each implemented as a doubly linked list (Nault, [0021 - Providing a set of accounting data, organizing said accounting data using doubly linked lists into a central memory of a computer and generating a financial statement]), with each doubly linked list comprising selected ones of the head and tail references (Nault, [0065 - The organization of the accounting trial balance data 100 in memory corresponds to a doubly linked data structure 500 which permits insertion, destruction and reordering of the accounts inside the list. As shown in Fig. 5a, a particularity of this organizational data is that the linked list 501 is distinct and contains the pointers NEXT 502 and PREVIOUS 503 and a pointer to the chart structure 504 which permits flexibility for manipulation]; [0073 - The pointers for the first element 517/head and the last element 518/tail of the list of pointers 501 as well as the pointer to the first element 519 of the LINK vector are stored in memory]), and each access node in the array including both a reference to a next access node and a reference to a previous access node (Nault, [0141 - The transaction structure 2201 is a doubly linked with the pointers NEXT 2202 and PREVIOUS 2203 inside of the structure]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the doubly linked lists of Nault into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of providing a set of accounting data, organizing the accounting data using doubly linked lists into a central memory of a computer and generating a financial statement (Nault, 0021).
As per Claim 10, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system.
Nault further discloses,
wherein the one or more tiles further comprise a free list of access nodes maintained in order by index into the array of access nodes (Nault, [0066 - The insertion algorithm used enables the insertion in an empty/free list]; [0069 - When an account is deleted, the element in the list of pointers/array of access nodes containing the pointer/address to the chart structure 509/tile is taken out of the list of pointers by modifying the pointer NEXT 502 of the preceding element and the pointer PREVIOUS 503 of the NEXT element. The destruction algorithm used to remove an element from the doubly linked list is able to process information in which the list is empty/free list]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the doubly linked lists of Nault into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of providing a set of accounting data, organizing the accounting data using doubly linked lists into a central memory of a computer and generating a financial statement (Nault, 0021).
As per Claim 11, the rejection of claim 5 is incorporated, and Taylor, Kodde, Makhija, Nault further disclose,
wherein at least one of the tiles is configured to enable the processor to move an access node (Nault, [0071 - When an account is moved within the list, only the NEXT 502 pointer and the PREVIOUS 503 pointer of the elements concerned in the list of pointers/array of access nodes are modified, using, in a successive fashion, the algorithm of destruction and the algorithm of insertion]) between two of the prioritized collections by rewriting the reference to the previous access node and the reference to the next access node (Nault, [0074, 0075 – In Fig. 4, the data organization for financial statements corresponds to a doubly linked data structure 520 permitting insertion, destruction of lines of the financial statement inside of the list. As shown in Fig. 5b, a particularity of this organization is that the linked list 521 is distinct and contains pointers NEXT 522 and PREVIOUS 523 and a pointer to the financial statement structure 524, which makes the manipulation flexible]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the doubly linked lists of Nault into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of providing a set of accounting data, organizing the accounting data using doubly linked lists into a central memory of a computer and generating a financial statement (Nault, 0021).
As per Claim 14, the rejection of claim 2 is incorporated, and Taylor discloses,
wherein each access node contains a reference to a corresponding one of the cell data structures (Taylor, [Fig. 20: shows the fields of a limit order record]; [0119 – In Fig. 20, an interest vector field 2022 serves to identify downstream subscribers that have an interest in the limit order; Here the interest vector field is a logical reference or pointer to those subscribers, as it explicitly associates the order data with the target participant accounts]).
Nault clarifies,
wherein each access node contains a reference to a corresponding one of the cell data structures (Nault, [0060 – As per Fig. 3, loading in and organizing the accounting data and accounting transactions in the central memory of the computer, represent the cell data structures; Since the claim does not define ‘cell data structures’, the citation is a valid interpretation]; [0066 - In Fig. 5a, each time an account is created, a new element in the chart structure 508 is created. A new element/access node in the list of pointers 509/access nodes is also created and inserted in the list]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the doubly linked lists of Nault into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of providing a set of accounting data, organizing the accounting data using doubly linked lists into a central memory of a computer and generating a financial statement (Nault, 0021).
Claims 12-13, 15-16 are rejected under AIA 35 U.S.C. 103(a) as being unpatentable over Taylor et al (20210174445), Kodde (20150095613) in view of Makhija (20230393784) and Studnitzer et al (20210166315).
As per Claim 12, the rejection of claim 2 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system. Kodde discloses that the hash table represents a tile. And Read-Only hash tables store static order data.
Studnitzer further clarifies,
wherein the cell data structures include static order data stored in a data structure that is separate from the one or more tiles (Studnitzer, [0146 – In Fig. 1, user database 102 includes information identifying market participants, e.g. traders, brokers, etc., and other users of electronic trading system 100, such as account numbers or identifiers, user names and passwords; Here account numbers or IDs, user names, passwords are static data]; [0152 - The users may include one or more market makers 130 which maintain a market by providing constant/static bid and offer prices for a derivative or security to the electronic trading system 100]; [0148 – While communicating with the Fig. 1, electronic trading system 100, an user may send and receive trade/orders or other information; Since the claim does not recite how the cell data structures are populated, the citation is a valid interpretation]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the static data of Studnitzer into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of using a trading system having improved performance under increasing processing transaction loads while providing improved trading opportunities, fault tolerance, low latency processing, high volume capacity, risk mitigation and market protections (Studnitzer, Abstract).
As per Claim 13, the rejection of claim 12 is incorporated, and Taylor, discloses,
wherein each cell data structure includes fields indicating an instrument, side, price, and an access node index (Taylor, [Fig. 20: shows the fields of a limit order record]; [0119 – In Fig. 20, an interest vector field 2022 serves to identify downstream subscribers that have an interest in the limit order, thereby suggesting an access node index per subscriber]; [Fig. 19]; [Fig. 20: Symbol 1902]; [0090 - Downstream from the MP module 1204 is a symbol mapping/SM module 1206, and further downstream is ONPA module 1208 which generates the stream view of the limit order data contained in limit order events]; [0092 - SM module 1206 resolves a unique symbol identifier for the base financial instrument and the associated market center for a received event. Input events contain a symbol field that uniquely identifies the base financial instrument. The symbol mapping stage performs a one-to-one translation from the input symbol field to the symbol identifier]),
wherein the processor is enabled to use the instrument, side, price, and the associated access node index to locate an associated access node within at least one of the tiles (Taylor, [0202 - The record may be located directly by using the symbol map index]; [0152 - The ONPA module 1208, upon receipt of a limit order event 1600, thus processes data in the limit order event 1600 to access memory 1602 and retrieve a limit order record 2000]; [0172 - Hashing the symbol, exchange identifier, and order reference number to create an address offset into the static order region of the memory which contains the first entry in the linked list that contains the desired order; Since the claim does not recite the format of the input request, the citations suggest that the processor uses the ISP as a key to directly select and index a specific tile, and then applies the access node index as an offset or pointer within that tile's internal array to pinpoint the exact access node]).
As per Claim 15, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system.
Studnitzer further discloses,
wherein processing open orders (Studnitzer, [Figs. 2, 22-23]) further comprises one or more matching engine books (Studnitzer, [Figs. 11-12]; [0156 – In Fig. 2, electronic trading system 100 includes a match engine function 106 which is implemented by one or more sets 206 of redundant transaction processors 208, i.e. match engines]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the match engines of Studnitzer into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of improving fault tolerance (Studnitzer, 0066).
As per Claim 16, the rejection of claim 1 is incorporated, and Taylor, Kodde, Makhija disclose a FPGA-based market data processing system.
Studnitzer further discloses,
wherein processing open orders (Studnitzer, [Figs. 2, 22-23]) further comprises one or more market data feeds (Studnitzer, [0006 - Outstanding orders are maintained in one or more data structures or databases referred to as ‘order books’, such orders being referred to as ‘resting’, and made visible, i.e., their availability for trading is advertised, to the market participants through electronic notifications/broadcasts, referred to as market data feeds]; [0007 - The standard protocol that is typically utilized for the transmission of market data feeds is the Financial Information Exchange/FIX protocol Adapted for Streaming FAST, aka FIX/FAST, which is used by multiple exchanges to distribute their market data]).
Therefore it would have been obvious to a person of ordinary skill at the time of filing to incorporate the market data feeds of Studnitzer into the hardware acceleration of financial instruments by Taylor, Kodde, Makhija for the benefit of having pricing information conveyed by the market data feed to include the prices, or changes thereto, of resting orders, prices at which particular orders were recently traded, or other information representative of the state of the market or changes therein (Studnitzer, 0007).
Response to Arguments
The Applicant's arguments filed on April 02, 2026 have been fully considered, but moot in view of the new ground of rejection.
Conclusion
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Arvind Talukdar
Primary Examiner
Art Unit 2132
/ARVIND TALUKDAR/Primary Examiner, Art Unit 2132
Prosecution Insights