DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . This office action is in response to a filing of 1/12/2026.
Notice of Pre-AIA or AIA Status
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Priority
Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), which papers have been placed of record in the file.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 7/22/2024 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements have been considered by the examiner.
Election/Restrictions
In the response from applicant on the restriction requirement of 11/14/2025, applicant agrees to withdraw invention of species 2 (claims 11-20) and elects species 1 (claims 1-10). Hence Claims 11-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention and species, there being no allowable generic or linking claim. Election was made without traverse in the reply filed on 1/12/2026.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-10 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor, or for pre-AIA the applicant regards as the invention.
Regarding claim 1, cited term of “an offset correction loop circuit configured to correct an offset correction voltage while tracking an offset change of the hall sensor and an offset change of an amplifier circuit based on the temperature change” (line 5-7) is vague and renders the claims indefinite. Firstly, it is unclear that the “an offset correction voltage” refers to which one of components/elements, an offset correction voltage of hall sensor, an offset correction voltage of amplifier circuit, or an offset correction voltage of claimed analog front-end circuit. Secondly, it is unclear that the “an offset change” refers to which one of parameters, an offset change of voltage, an offset change of current, or an offset change of temperature?
Claims 2-10 are rejected as containing the deficiencies of claim 1 through their dependency from claim 1.
Therefore proper amendments are required in order to clarify the scopes of the claims and overcome the rejections.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1 - 10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Petrie et al (US 20160139230).
Regarding Claim 1, Petrie teaches an analog front-end circuit (abstract; figs. 3-4) comprising:
a hall bias correction loop circuit (fig. 2, 230) configured to correct a sensing voltage of a hall sensor by adjusting a hall bias current flowing in the hall sensor while tracking a change in the sensing voltage of the hall sensor (¶[0058], line 1-19, trim circuit 230 may be included or embedded as part of ADC 222, or may be included or embedded in circuitry that controls the Hall plates; the trim circuitry may adjust the current through the Hall plate in order to adjust the Hall plate's sensitivity) based on a temperature change (fig. 4, temperature sensor; ¶[0059], line 1-8, Circuit 200 may also include a temperature sensor circuit to sense the temperature of circuit 200. The amount of gain and offset adjustment performed by trim circuit 230 may be based on the temperature measured by the temperature sensor circuit);
an offset correction loop circuit configured to correct an offset correction voltage while tracking an offset change of the hall sensor and an offset change of an amplifier circuit based on the temperature change (fig. 13, loop of:702-GENERATE A MEASURED MAGNETIC FIELD SIGNAL, 712- GENERATE A REFERENCE MAGNETIC FIELD SIGNAL, 708- ADJUST THE GAIN AND/OR OFFSET OF THE EXTERNAL MAGNETIC FIELD SIGNAL, 718- ADJUST THE GAIN AND/OR OFFSET OF THE REFERENCE MAGNETIC FIELD SIGNAL, 720- COMBINE THE DIGITAL MEASURED MAGNETIC FIELD SIGNAL AND THE DIGITAL REFERENCE MAGNETIC FIELD SIGNAL TO GENERATE A CALIBRATED MAGNETIC FIELD SIGNAL, 722- USE THE CALIBRATED MAGNETIC FIELD SIGNAL TO GENERATE AN OUTPUT SIGNAL; ¶[0059], line 1-8, For example, if the temperature reading is high, trim circuit 230 may apply more or less gain and offset adjustment than if the temperature is low, or vice versa);
the amplifier circuit configured to amplify and output the sensing voltage of the hall sensor, corrected through at least one of the hall bias correction loop circuit and the offset correction loop circuit (¶[0058], line 1-19, trim circuit 230 may be an analog circuit containing analog filters and amplifiers, and may be coupled between amplifier 214 and ADC 222; The trim circuit 230 may include digital filters, digital adders and multipliers, and other circuits that can adjust the gain and offset of the output reference magnetic field signal); and
an analog-digital converter configured to convert an output voltage of the amplifier circuit into sensing data and output the sensing data (fig. 2, ADCs in 222; 224; ¶[0043], line 1-12, Circuit 200 includes one or more so-called signal paths, which is a path through circuit 200 over which a signal is propagated while the signal is being processed. For example, a signal may be generated by hall element(s) 202, then propagated to amplifier 214, then propagated to ADC 222 and through either converter circuit 234 or 236, and then finally propagated to an output of ADC 222 as signal 224).
Regarding Claim 2, Petrie teaches that the analog front-end circuit of claim 1, further comprising:
a temperature sensor configured to sense the temperature change and control operations of the hall bias correction loop circuit and the offset correction loop circuit according to a sensing result (fig. 4, temperature sensor; ¶[0059], line 1-8, Circuit 200 may also include a temperature sensor circuit to sense the temperature of circuit 200. The amount of gain and offset adjustment performed by trim circuit 230 may be based on the temperature measured by the temperature sensor circuit).
Regarding Claim 3, Petrie teaches that the analog front-end circuit of claim 1, wherein the hall bias correction loop circuit performs a correction operation of the sensing voltage of the hall sensor and then the offset correction loop circuit performs an operation of correcting the offset correction voltage (fig. 2, 230; ¶[0058], line 1-19, trim circuit 230 may be included or embedded as part of ADC 222, or may be included or embedded in circuitry that controls the Hall plates; the trim circuitry may adjust the current through the Hall plate in order to adjust the Hall plate's sensitivity; also see fig. 13, loop including 708, 718, 720, 722).
Regarding Claim 4, Petrie teaches that the analog front-end circuit of claim 1, wherein the hall bias correction loop circuit and the offset correction loop circuit (fig. 2, 230; ¶[0058], line 1-19, trim circuit 230 may be included or embedded as part of ADC 222, or may be included or embedded in circuitry that controls the Hall plates; the trim circuitry may adjust the current through the Hall plate in order to adjust the Hall plate's sensitivity), use a tracking method of a successive approximation register (SAR) logic (--this portion of claim is of a product-by-process claim, for product-by-process claim even though product-by-process claims are limited by and defined by the process, determination of patentability is based on the product itself. The patentability of a product does not depend on its method of production. If the product in the product-by-process claim is the same as or obvious from a product of the prior art, the claim is unpatentable even though the prior product was made by a different process. In re Thorpe, 777 F.2d 695, 698, 227 USPQ 964, 966 (Fed. Cir. 1985). See MPEP 2113).
Regarding Claim 5, Petrie teaches that the analog front-end circuit of claim 1, wherein the hall bias correction loop circuit and the offset correction loop circuit automatically operate according to an option signal (fig. 13, loop including 708, 718, 720, 722) or manually operate according to an external control signal (¶[0108], line 23-28, in response to an external trigger signal).
Regarding Claim 6, Petrie teaches that the analog front-end circuit of claim 1, wherein the hall bias correction loop circuit includes:
a multiplexer configured to select and output any one of a plurality of hall bias reference voltages (fig. 2, 238, 240; ¶[0051], line 1-18, ADC 222 may include multiplexors 238 and 240, or other switching circuits, that can selectively couple and de-couple converter circuits 234 and 236 from the other circuits included in ADC 222 so that converter circuit 234 processes measured magnetic field signal 204 during the measured time period and converter circuit 236 processes reference magnetic field signal 206 during the reference time period),
a hall bias current correction logic circuit configured to output current correction data by tracking a resistance change of the hall sensor based on the temperature change as an output of a SAR logic while comparing the sensing voltage of the hall sensor, changed based on the temperature change, with the hall bias reference voltage (fig. 4, L-BIST; ¶[0067], line 1-15, test circuitry and techniques may also be included in magnetic field sensor 104 to test digital portions of magnetic field sensor 104, such as logic BIST circuits to test a digital controller and a dual-bit error check to test an EEPROM; ¶[0076], line 1-6, Integrator circuit 430 may include a path select signal 438, a multiplexor 440, a clock signal 442, and logic AND gates 444 and 446.; fig. 13, loop including 708, 718, 720, 722; also Regarding claim 4 above), and
a hall bias current source configured to adjust the hall bias current according to the current correction data (fig. 2, 218; ¶[0045], line 1-9, A driver circuit 218 may produce a current that flows through coil 216 to produce the reference magnetic field mentioned above; fig. 13, loop including 708, 718, 720, 722).
Regarding Claim 7, Petrie teaches that the analog front-end circuit of claim 6, wherein the hall bias current source includes a current digital-analog converter configured to convert the current correction data into the hall bias current (fig. 2, 234-ADC; fig. 4, 408-ADC).
Regarding Claim 8, Petrie teaches that the analog front-end circuit of claim 6, wherein the hall bias correction loop circuit repeatedly performs an operation of correcting the sensing voltage of the hall sensor by adjusting the hall bias current based on the temperature change during a plurality of cycles of a clock signal and outputs the sensing voltage of the hall sensor, corrected by a lastly adjusted hall bias current, to the amplifier circuit (fig. 13, loop including 708, 718, 720, 722; fig. 4, temperature sensor; ¶[0059], line 1-8, Circuit 200 may also include a temperature sensor circuit to sense the temperature of circuit 200. The amount of gain and offset adjustment performed by trim circuit 230 may be based on the temperature measured by the temperature sensor circuit).
Regarding Claim 9, Petrie teaches that the analog front-end circuit of claim 5, wherein the offset correction loop circuit includes:
a multiplexer configured to select and output any one a plurality of offset reference voltages (fig. 2, 238, 240; ¶[0051], line 1-18, ADC 222 may include multiplexors 238 and 240, or other switching circuits, that can selectively couple and de-couple converter circuits 234 and 236 from the other circuits included in ADC 222 so that converter circuit 234 processes measured magnetic field signal 204 during the measured time period and converter circuit 236 processes reference magnetic field signal 206 during the reference time period),
an offset correction logic circuit configured to output offset correction data by tracking the offset change of the hall sensor and the offset change of the amplifier circuit based on the temperature change as an output of an SAR logic while comparing the output voltage of the amplifier circuit with the offset reference voltage (fig. 4, L-BIST; ¶[0067], line 1-15, test circuitry and techniques may also be included in magnetic field sensor 104 to test digital portions of magnetic field sensor 104, such as logic BIST circuits to test a digital controller and a dual-bit error check to test an EEPROM; ¶[0076], line 1-6, Integrator circuit 430 may include a path select signal 438, a multiplexor 440, a clock signal 442, and logic AND gates 444 and 446.; fig. 13, loop including 708, 718, 720, 722; also Regarding claim 4 above); and
an offset correction digital-analog converter configured to correct the output voltage of the amplifier circuit by generating the offset correction voltage and applying the offset correction voltage to an input terminal of the amplifier circuit according to the offset correction data (fig. 2, 234-ADC; fig. 4, 408-ADC; fig. 13, loop including 708, 718, 720, 722).
Regarding Claim 10, Petrie teaches that the analog front-end circuit of claim 9, wherein the offset correction loop circuit repeatedly performs an operation of correcting the output voltage of the amplifier circuit by correcting the offset correction voltage based on the temperature change during a plurality of cycles of a clock signal and outputs the output voltage of the amplifier circuit, corrected by a lastly adjusted offset correction voltage, to the analog-digital converter (fig. 13, loop including 708, 718, 720, 722; fig. 4, temperature sensor; ¶[0059], line 1-8, Circuit 200 may also include a temperature sensor circuit to sense the temperature of circuit 200. The amount of gain and offset adjustment performed by trim circuit 230 may be based on the temperature measured by the temperature sensor circuit; fig. 5, 418, 420, 220, 416; ¶[0068], line 1-14, Clock signals 418 and 420 are internal clock signals of ADC 222).
Examiner’s Note
Regarding the references, the Examiner cites particular figures, paragraphs, columns and line numbers in the reference(s), as applied to the claims above. Although the particular citations are representative teachings and are applied to specific limitations within the claims, other passages, internally cited references, and figures may also apply. In preparing a response, it is respectfully requested that the Applicant fully consider the references, in their entirety, as potentially disclosing or teaching all or part of the claimed invention, as well as fully consider the context of the passage as taught by the reference(s) or as disclosed by the Examiner.
Conclusion
Any inquiry concerning this communication or earlier communication from the examiner should be directed to Jie Lei whose telephone number is (571) 272 7231. The examiner can normally be reached on Mon.-Thurs. 8:00 am to 5:30 pm.
If attempts to reach the examiner by the telephone are unsuccessful, the examiner's supervisor, Thomas Pham can be reached on (571) 272 3689.The Fax number for the organization where this application is assigned is (571) 273 8300.
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/JIE LEI/Primary Examiner, Art Unit 2872