Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
This action is in response to the application filed on 12/07/2023.
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 08/23/2024 and 08/22/2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Claim Objections
Claims 5, 19, and 20 are objected to because of the following informalities: Regarding claim 5, in line 2, “the first terminal of the capacitor” appears that it should read as “a first terminal of the capacitor”. Regarding claim 19, in line 2, “the common” appears that it should read as “the common node”;in line 3, “the voltage across the capacitor” appears that it should read as “a voltage across the capacitor”. Regarding claim 20, in line 3-4, in line 3, “the voltage across the capacitor” appears that it should read as “a voltage across the capacitor”. Appropriate correction is required.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-6, 8-12, and 14-20 are rejected under 35 U.S.C. 103 as being unpatentable over Bianco et al. (US Patent Application Publication US 2010/0072968 A1, hereinafter “Bianco”) in view of Chen et al. (US Patent Application Publication US 2010/0301822 A1, hereinafter “Chen”).
Regarding claim 1, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) a circuit (see Fig. 1) comprising: a control circuit (160) coupled to a power converter (110) having an input voltage VIN (Vin) and an output voltage VOUT (Vout), the control circuit comprising (see Fig. 3): a current source (320); and a capacitor (340) connected between the current source and a ground (ground), wherein the current source is configured to charge the capacitor with a current equal to α(VIN−VOUT) when a pulse width modulate (PWM) signal of a PWM controller (comprising 140, 145, 150) of the power converter is high, and to discharge the capacitor with a current equal to α(−VOUT) when the PWM signal of the PWM controller is low (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging and proportional to (-Vout) when discharging), α being a pre-configured constant; and wherein the control circuit is configured to trigger the PWM controller to skip pulse(s) when a voltage across the capacitor (Tmin) increases to be larger than a skip threshold (CP) before a present switching cycle of the power converter ends (Ton+Toff).
Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 2, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the current source comprises: a first current source (see Fig. 3, 320) having a current αVIN (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging and proportional to (-Vout) when discharging), the first current source being connected to a first terminal of the capacitor (top-side terminal of 340) with a current flowing direction of the first current source from the first current source to the capacitor (from 320 to 430); and a second current source (315) having a current αVOUT (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging and proportional to (-Vout) when discharging), the second current source being connected between the first terminal of the capacitor and the ground, with a current flowing direction of the second current source from the first terminal of the capacitor to the ground (from top-side terminal of 340 to ground), and the second current source being connected in parallel with the capacitor (315 is parallel to 340).
Regarding claim 3, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises a first switch connected between the first current source and the first terminal of the capacitor (switch 320), the first switch being configured to switch on when the PWM signal is high (when switch 320 is ON, 320 is charged).
Regarding claim 4, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises a second switch (310) connected between the first terminal of the capacitor and the ground in parallel with the capacitor, the second switch being configured to set the voltage across the capacitor to zero (when 310 turns on 340 is discharged to zero).
Regarding claim 5, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises: a skip circuit (comprising 330, 335) having an input terminal (“-“ 330) connected to the first terminal of the capacitor, the skip circuit being configured to output a skip signal (EN) indicating to skip switching pulse(s) when the voltage across the capacitor increases to be larger than the skip threshold before the present switching cycle ends. Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the circuit of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 6, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) further comprising: a driver (155) connected between the power converter and the skip circuit, the driver being configured to control, based on the skip signal, to skip switching on a power switch of the power converter for pulse(s) (155 controls 310 and 135 of 110 based on EN).
Regarding claim 8, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the skip threshold is zero, or is greater than zero (CP is greater than zero).
Regarding claim 9, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) a method for controlling a pulse width modulate (PWM) controller (comprising 140, 145, 150) of a power converter (110) to skip pulse(s), comprising: in a switching cycle of the power converter (Ton+Toff), charging a capacitor (340) with a current equal to α(VIN−VOUT) when a PWM signal of the PWM controller is high (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging), α being a pre-configured constant, and the power converter having an input voltage VIN (Vin) and an output voltage VOUT (Vout); discharging the capacitor with a current equal to α(−VOUT) when the PWM signal of the PWM controller is low (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (-Vout) when discharging); and when detecting that a voltage across the capacitor (Tmin) increases to be larger than a skip threshold (CP) before the switching cycle ends, triggering the PWM controller to skip pulse(s) (EN going low triggers PWM to skip pulses).
Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 10, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) further comprising: generating a skip signal (EN) indicating to skip pulses when detecting that the voltage across the capacitor increases to be larger than the skip threshold before the switching cycle ends.
Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the method of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 11, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) further comprising: triggering, based on the skip signal, the PWM controller to skip switching on a power switch of the power converter for pulse(s) (EN going low triggers PWM to skip pulses).
Regarding claim 12, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein triggering, based on the skip signal, the PWM controller to skip switching on the power switch for pulse(s) comprises: triggering a driver (155) of the PWM controller to drive the power switch to skip pulse(s) (155 controls 310 and 135 of 110 based on EN).
Regarding claim 14, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) further comprising: resetting the skip signal at start of a next switching cycle (EN is reset at end of each Toff).
Regarding claim 15, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) further comprising: setting the voltage across the capacitor to zero at or before start of a next switching cycle (PL resets 340 before Ton).
Regarding claim 15, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) an apparatus comprising: a power converter (110) comprising a power switch (130, 135) and an inductor (120) that are connected between an input node (node of Vin) and an output node (node of Vout) of the power converter, the input node having an input voltage VIN (Vin) and the output node providing an output voltage VOUT (Vout); a pulse width modulate (PWM) controller (comprising 140, 145, 150) coupled to the power converter and configured to control the power converter to operate in a PWM mode; and a control circuit (160) coupled to the PWM controller, the control circuit comprising: a current source (320); and a capacitor (340) connected between the current source and a ground (ground), wherein the current source is configured to charge the capacitor with a current equal to αVIN or α(VIN−VOUT) when a PWM signal of the PWM controller is high (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging), and to discharge the capacitor with a current equal to α(−VOUT) or α(VIN−VOUT) when the PWM signal of the PWM controller is low (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (-Vout) when discharging), α being a pre-configured constant; and wherein the control circuit is configured to trigger the PWM controller to skip switching on the power switch for pulse(s) when a voltage at a common node of the current source and the capacitor (Tmin) increases to be larger than a skip threshold (CP) before a present switching cycle of the power converter ends (EN going low triggers PWM to skip pulses).
Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Regarding claim 17, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the current source comprises: a first current source (see Fig. 3, 320) having a current αVIN (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging and proportional to (-Vout) when discharging), the first current source being connected between the common node and the ground with a current flowing direction of the first current source being from the first current source to the common node (from 320 to 430); and a second current source (315) having a current αVOUT (see [0090] “capacitor 340 --whose charge is charged and discharged depending on the behavior of the inductor current of the respective DC-DC converter” where the inductor current is proportional to (Vin-Vout) when charging and proportional to (-Vout) when discharging), the second current source being connected between the common node and the ground with a current flowing direction of the second current source being from the common node to the ground (from top-side terminal of 340 to ground), and the second current source being connected in parallel with the capacitor (315 is parallel to 340).
Regarding claim 18, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises a first switch (switch 320) connected between the first current source and the common node, the first switch being configured to switch on when the PWM signal is high (when switch 320 is ON, 320 is charged).
Regarding claim 19, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises a second switch (310) connected between the common and the ground in parallel with the capacitor, the second switch being configured to set the voltage across the capacitor to zero (when 310 turns on 340 is discharged to zero).
Regarding claim 20, Bianco discloses (see Fig. 1, Fig. 3, and Fig. 4) wherein the control circuit further comprises: a skip circuit (comprising 330, 335) having an input terminal (“-“ 330) connected to the common node, the skip circuit being configured to output a skip signal (EN) indicating to skip switching pulse(s) when the voltage across the capacitor increases to be larger than the skip threshold before the present switching cycle ends. Bianco does not disclose wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold. However, Chen teaches (see Fig. 7 and Fig. 8) wherein the pulse(s) is skipped (see “PSM On time” of Fig. 8) when the voltage across the capacitor (522, see SAW) decreases to be less than a skip threshold (PSC_Ref; see Fig. 8, where PSM On time is high when SAW is lower than PSC_Ref). Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to modify the apparatus of Bianco wherein the pulse(s) is skipped when the voltage across the capacitor decreases to be less than a skip threshold, as taught by Chen, because it is a widely known design choice/option in implementing the pulse skip trigger, i.e. reversing the threshold crossing direction, and since it has been held that a mere reversal of the essential working parts of a device involves only routine skill in the art. In re Einstein, 8 USPQ 167.
Allowable Subject Matter
Claims 7 and 13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: Regarding Claim 7, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “further comprising a delay circuit connected between the skip circuit and the driver, the delay circuit comprising: an AND gate having a first input terminal connected to an output terminal of the skip circuit, and an output terminal connected to the driver; and a one shot timer having an input terminal connected to the output terminal of the skip circuit, and an output terminal connected to a second input terminal of the AND gate, with an input at the second input terminal of the AND gate inverted; and wherein the one shot timer is triggered, by the skip signal, to start timing according to a preset time, and the driver is configured to skip switching on the power switch for pulse(s) when the one shot timer expires before the present switching cycle ends.”. Regarding Claim 13, none of the cited prior art alone or in combination disclose or teach the claimed inventions in which “starting a one shot timer triggered by the skip signal; and wherein triggering the PWM controller to skip pulse(s) comprises: triggering the PWM controller to skip pulse(s) when the one shot timer expires before the switching cycle ends.”.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: US Patent Application Publication US 2014/0253080 A1 discloses a pulse skipping control method for a buck converter. US Patent Application Publication US 2006/0061343 A1 discloses a control method for a buck converter. US Patent Application Publication US 2015/0084606 A1 discloses a DC/DC converter with zero crossing detection and pulse skipping. US Patent Application Publication US 2012/0268095 A1 discloses a DC/DC converter with pulse skipping.
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/JYE-JUNE LEE/Examiner, Art Unit 2838
/JUE ZHANG/Primary Examiner, Art Unit 2838