DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Information Disclosure Statement The information disclosure statement (IDS) submitted on 1/31/24 is being considered by the examiner. Claim Rejections - 35 USC § 102 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis ( i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. Claim(s) 1 , 7, 8 and 16 is/are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Biswas et al. (US 2019/0236234) . With respect to claim 1, Figure 4 of Biswas discloses a n integrated circuit (IC) device, comprising: multiple rows of voltage rails (404(DD)(A)-404(DD)(D) and 404(SS)(A)-404(SS)(D)) , including supply voltage rails and reference voltage rails (VDD, VSS) ; and a first column of elongated metal stubs (408(DD)(A), 408( SS )(A), 408(DD)(E), 408( SS )( D ), 408(DD)(I), 408( SS )( G ), 408(DD)(M) , 408( SS )( J ) ) perpendicular to the rows of voltage rails (see Figure 4) , coupled to respective ones of the voltage rails via metal-filled vias of one or more dielectric layers to provide corresponding supply voltage stubs and reference voltage stubs (see Figure 6 and Paragraphs 86-87) . With respect to claim 7 , Biswas further teaches wherein the supply voltage rails and the reference voltage rails are arranged in an alternating fashion such that first column of elongated metal stubs form an alternating sequence of supply voltage stubs and reference voltage stubs (see Figure 4) . With respect to claim 8 , Biswas further teaches a first set of one or more metal layers that comprise the rows of voltage rails (M( i )) ; and a second set of one or more metal layers that comprise the elongated metal stubs (M(i+1)) . With respect to claim 16 , Figure 4 of Biswas discloses a method of designing a power distribution network of an integrated circuit (IC) design, comprising: placing multiple rows of tracks in a first metal layer of the IC design (404(DD)(A)-404(DD)(D) and 404(SS)(A)-404(SS)(D) in M( i ) layer) , wherein the tracks are arranged in an alternating sequence of supply voltage tracks and reference voltage tracks (see Figure 4) ; and placing a first column of elongated stubs in a second metal layer of the IC design (408(DD)(A), 408(SS)(A), 408(DD)(E), 408(SS)(D), 408(DD)(I), 408(SS)(G), 408(DD)(M) , 408(SS)(J) in M(i+1) layer ) , perpendicular to the rows of tracks of the first layer (see Figure 4) , and coupling the elongated stubs to respective ones of the tracks of the first layer, through vias of a dielectric layer placed between the first and second metal layers, to provide an alternating sequence of supply voltage stubs and reference voltage stubs (see Figure 6 and Paragraphs 86-87) . Allowable Subject Matter Claims 2-6 and 17-20 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 9-15 appear to comprise allowable subject matter. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Jany Richardson whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-5074 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday - Friday, 7:00am to 3:00pm . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Alexander Taningco can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 571-272-8048 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JANY RICHARDSON/ Primary Examiner, Art Unit 2844