DETAILED ACTION
Notice of Pre-AIA or AIA Status
Applicant’s amendment, filed 09/15/2025, for application number 18/533,074 has been received and entered into record. Claims 24, 25, 38, 39, 45 and 46 are amended. Claims 37 and 40 are cancelled. Claims 47 and 48 are added. Thus, claims 24-36, 38-39, 41-48 are presented for examination.
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 24-32, 34-36, 41-45, 47, and 48 are rejected under 35 U.S.C. 103 as being unpatentable over Chaudhari (US 2004/0003361 A1) in view of Wang et al. (US 2013/0021072 A1).
Regarding claim 24, Chaudhari teaches an apparatus (Figure 2, IC 200), comprising:
a block including a first domain and a second domain, wherein the block includes a clock distribution tree configured to distribute a clock signal within the block (“The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block of the circuit component and the circuit component receives the other clock signal at a second component block to create a second time domain for the second component block of the circuit component.” Par 0017) [the circuit component corresponds to the block, and it contains first and second component blocks which establish first and second time domains, respectively], wherein the block includes an interface between the first domain and the second domain, wherein the interface includes at least one of a pseudo-synchronous first-in-first-out queue or a pulse crosser, wherein the interface is configured to support communications between the first domain and the second domain (“As shown in FIG. 3, a signal crossing from a first time domain of the first component block 207 of the circuit component-2 206-2 to the second component block 209 of circuit component-2 having a second time domain, travels along a path” par 0028 and “the synchronization logic includes a double clock synchronizer 320 including a first flip-flop 322 timed at CLK2 and a second flip-flop 324 also timed at CLK2.” Par 0029) [the path between the component blocks (domains) functions as the interface, and the double clock synchronizer provides the required synchronization logic for communication, corresponds to the function of a pulse-crosser].
However, Chaudhari does not explicitly teach wherein the block is configured to control, based on information indicative of a workload on the block, which clock pulses of the clock signal are permitted to pass from a first portion of the clock distribution tree of the block associated with the first domain to a second portion of the clock distribution tree of the block associated with the second domain.
In the analogous art, Wang teaches wherein the block is configured to control, based on information indicative of a workload on the block, which clock pulses of the clock signal are permitted to pass from a first portion of the clock distribution tree of the block associated with the first domain to a second portion of the clock distribution tree of the block associated with the second domain (“clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal. For example, clock control unit 12 could effectively reduce the frequency of a clock signal output by a coarse clock-gating unit 14 by asserting the enable signal for only one of every four cycles of the root clock signal. This in turn results in the coarse clock-gating unit 14 outputting a clock signal having effectively ¼ the frequency of the root clock signal.” Par 0023 and “Each of the functional units 15 in the embodiment shown is coupled to signals indicative of performance (Performance' signal as shown) to clock control unit 12. Such indications may include indication of processing workload,” par 0022 and claims 1 and 6) [frequency is reduced based on workload by asserting an enable signal for only a fraction of the clock cycle, selectively permitting pulses to pass through the coarse clock-gating unit which supplies the operational clock signal to the functional unit (block)],
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chaudhari and Wang before him before the effective filing date of the claimed invention, to have modified Chaudhari to incorporate the teachings of Wang to permit certain clock signals to pass to another domain to dynamically reduce power consumption based on workload for components operating in the default separate clock domain mode.
Claim 45 corresponds to claim 24 and is rejected accordingly.
Regarding claim 25, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein a fraction of the clock pulses of the of the clock signal that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is controlled to remain within a range between a non-zero minimum and a maximum that is based on the clock signal of the block ("the enable signal may be asserted for one of every N cycles of the input clock signal, and de-asserted for the remaining N-1 clock cycles of the input signal. The value of N may be an integer value greater than one." par 0037 and "Each coarse clock-gating unit 14 is coupled to output a respective clock signal to a corresponding instance of functional unit 15. The clock signal output by each coarse clock-gating unit 14 may be provided to, via another inverter 13, to a number of different leaf nodes 17 in each of functional units 15." par 0026 and "When the enable signal is periodically toggled between its asserted and de-asserted states, the coarse clock-gating unit may effectively provide an output clock signal to the functional unit that has a lower frequency …than the full frequency," par 0036 and "For the full clock frequency, the enable signal may be held asserted." par 0039 and Figure 5 and claim 1) [controlling the passing fraction (1/N) dynamically based on workload supports operation at a full frequency (fraction = 1, maximum) and a reduced frequency (fraction = 1/N, N>1, non-zero minimum].
Regarding claim 26, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein clock pulses of the clock signal of the block are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block when the information indicative of the workload on the block is indicative that activity is presented at an input interface to the block ("In some cases, a given functional unit 15 may be active, but may nevertheless have a low performance demand. For example, consider a situation in which a given functional unit 15 has made a number of requests for information from another one of functional units 15 (or to an agent external to IC 10). In such a case, there may be significant latency in satisfying such requests. Accordingly, the functional unit 15 that initiated the requests may have no other work to perform while waiting for the requested information to be returned. In such a situation, clock control unit 12 may reduce the frequency of the clock signal provided to that particular functional unit 15. More particularly, clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023 and "Although not explicitly shown, functional unit 15 may include performance-monitoring circuitry coupled to each of the leaf nodes and configured to determine if its corresponding synchronous circuits 19 are active or inactive." par 0027) [enabling the output means permitting the pulses to pass; this occurs when the functional unit is active].
Regarding claim 27, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block when the information indicative of the workload on the block is indicative that no activity is presented at an input interface to the block ("If all circuits of a given functional unit 15 are idle, clock control unit 15 may de-assert a corresponding enable signal provided to the respective coarse clock-gating unit 14. This may inhibit the clock signal from being provided to the entirety of the idle functional unit 15," par 0022 and "Although not explicitly shown, functional unit 15 may include performance-monitoring circuitry coupled to each of the leaf nodes and configured to determine if its corresponding synchronous circuits 19 are active or inactive." par 0027) [the functional units provide signals indicative of performance].
Regarding claim 28, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein clock pulses of the clock signal of the block are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block when the information indicative of the workload on the block is indicative that activity is available at an output interface from the block ("In some cases, a given functional unit 15 may be active, but may nevertheless have a low performance demand. For example, consider a situation in which a given functional unit 15 has made a number of requests for information from another one of functional units 15 (or to an agent external to IC 10). In such a case, there may be significant latency in satisfying such requests. Accordingly, the functional unit 15 that initiated the requests may have no other work to perform while waiting for the requested information to be returned. In such a situation, clock control unit 12 may reduce the frequency of the clock signal provided to that particular functional unit 15. More particularly, clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023) [when a functional block is active (a state determined by workload information, which can include scenarios involving interaction via interfaces, such as making requests) the clock control unit enables the clock-gating unit (permitting to pass the clock pulses from the first to second portion of the tree].
Regarding claim 29, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein clock pulses of the clock signal of the block are prevented from passing from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block when the information indicative of the workload on the block is indicative that no activity is available at an output interface from the block ("If all circuits of a given functional unit 15 are idle, clock control unit 15 may de-assert a corresponding enable signal provided to the respective coarse clock-gating unit 14. This may inhibit the clock signal from being provided to the entirety of the idle functional unit 15," par 0022) [the idle state (reflecting no workload or activity, including at interfaces, under BRI) causes de-asserting the enable signal for the coarse clock-gating unit, which inhibits the signal from being provided to the functional unit's internal clock tree (second portion)].
Regarding claim 30, Chaudhari and Wang teach the apparatus of claim 24. Wang further teaches wherein clock pulses of the clock signal of the block are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block when the information indicative of the workload on the block is indicative that a measure of internal states of the block is indicative that work is presented to the block ("In some cases, a given functional unit 15 may be active, but may nevertheless have a low performance demand. For example, consider a situation in which a given functional unit 15 has made a number of requests for information from another one of functional units 15 (or to an agent external to IC 10). In such a case, there may be significant latency in satisfying such requests. Accordingly, the functional unit 15 that initiated the requests may have no other work to perform while waiting for the requested information to be returned. In such a situation, clock control unit 12 may reduce the frequency of the clock signal provided to that particular functional unit 15. More particularly, clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023 and "Each of the functional units 15 in the embodiment shown is coupled to signals indicative of performance (Performance' signal as shown) to clock control unit 12. Such indications may include indication of processing workload, memory requests, cache requests and/or cache hits, and virtually any other type of information that may indicate a performance demand for a particular functional unit 15." par 0022 and Figure 2) [the "other type of information" may encompass measures of internal states, as performance monitoring circuitry in the functional units can determine if synchronous circuits 19 are active or inactive; being active with some performance demand or processing workload corresponds to "work is presented at the block].
Regarding claim 31, Chaudhari and Wang teach the apparatus of claim 30. Wang further teaches wherein the measure of internal states is based on at least one of a measure of an occupancy of a work queue of the block or a measure of a number of active threads of the block ("Such indications may include indication of processing workload, memory requests, cache requests and/or cache hits, and virtually any other type of information that may indicate a performance demand for a particular functional unit 15." par 0022 and "functional unit 15 may include performance-monitoring circuitry coupled to each of the leaf nodes and configured to determine if its corresponding synchronous circuits 19 are active or inactive. This information may be provided with the performance information as discussed above." par 0027) [the processing workload may include measurements related to queue occupancy of active threads].
Regarding claim 32, Chaudhari and Wang teach the apparatus of claim 30. Wang further teaches wherein an amount of the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is based on the measure of the internal states of the block ("In some cases, a given functional unit 15 may be active, but may nevertheless have a low performance demand. For example, consider a situation in which a given functional unit 15 has made a number of requests for information from another one of functional units 15 (or to an agent external to IC 10). In such a case, there may be significant latency in satisfying such requests. Accordingly, the functional unit 15 that initiated the requests may have no other work to perform while waiting for the requested information to be returned. In such a situation, clock control unit 12 may reduce the frequency of the clock signal provided to that particular functional unit 15. More particularly, clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023) [the clock control unit reduces frequency when functional unit is active but has a low performance demand; this is based on the performance signal (Fig. 1) and information about whether the synchronous circuits are active or inactive; thus decision to control the amount of permitted pulses (by enabling for 1/N cycles) is based on this performance information, which includes internal state measures].
Regarding claim 34, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block are synchronous to the clock signal of the block at a leaf level of the clock distribution tree of the block ("The synchronous circuits 19 may include flip-flops, latches, and/or other types of circuits that operate in accordance with a clock signal." par 0026 and "the use of the inverters/buffers may be used to control the skew of the clock signals distributed among the various leaf nodes 17 so that the clock edges are substantially aligned from one leaf node 17 to the next," par 0028 and Figures 1-2).
Regarding claim 35, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the block includes: a controller configured to generate, based on the information indicative of the workload on the block, a clock control signal configured to control which clock pulses of the clock signal are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block ("clock control unit 12 may take various actions to control the clock signals to optimize the balance between performance and power consumption." par 0022 and " Such indications may include indication of processing workload," par 0022 and "clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023 and Figure 1) [clock control unit corresponds to the controller, which generates control signals CCLKEn0-CCLKEn2 to control the CCG units 14; it uses the indications of the workload to enable the coarse clock-gating unit for one of every N cycles, which indicates which clock pulses are permitted to pass]; and a clock modulator configured to control, based on the clock control signal, passage of clock pulses of the clock signal of the block from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block ("When an enable signal is asserted to a respective coarse clock-gating unit 14, the clock signal is passed for distribution to the corresponding functional unit 15. If the enable signal is de-asserted, the respective coarse clock-gating unit 14 may inhibit the clock signal from being provided to the corresponding functional unit 15." par 0020 and Figure 1) [the CCG units 14 corresponds to the clock modulator].
Regarding claim 36, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the block includes: a controller configured to generate, based on the information indicative of the workload on the block, a clock control signal configured to control which clock pulses of the clock signal are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block ("clock control unit 12 may take various actions to control the clock signals to optimize the balance between performance and power consumption." par 0022 and " Such indications may include indication of processing workload," par 0022 and "clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal." par 0023) [clock control unit corresponds to the controller; it uses the indications of the workload to enable the coarse clock-gating unit for one of every N cycles, which indicates which clock pulses are permitted to pass]; and a clock modulator including a clock input configured to receive the clock signal of the block, a control input configured to receive a latched version of the clock control signal, and a clock output configured to output the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block ("Clock-gating unit 25 in the embodiment shown includes a latch 26 and an AND gate 27. Latch 26 in the embodiment shown is a level-sensitive latch that is coupled to receive the enable signal (‘EN’) on its ‘D’ input and the input clock signal (‘ClkIn’) on its clock input. The output of latch 26 is a synchronized enable signal (‘EnIn’) that is provided as the second input to AND gate 27. When the synchronized enable signal provided to AND gate 27 is high, the output of clock-gating unit 25 (from AND gate 27) follows the state of the input clock signal." par 0030 and Figure 3) [the CCG units 14 corresponds to the clock modulator; the root clock signal input corresponds to the clock input receiving the clock signal; the synchronized enable signal output by the latch corresponds to the latched version of the clock control signal; the operational clock signal to the functional unit (i.e. second portion) corresponds to the clock output].
Regarding claim 41, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the apparatus is a device including an electronic circuit on which the block is disposed ("system 150 may be a mobile device (e.g. personal digital assistant (PDA), smart phone, etc.)" par 0041 and Figure 6) [the IC (corresponding to the electronic circuit) is included in system 150].
Regarding claim 42, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the apparatus is an electronic circuit on which the block is disposed (Figure 1, the root clock, clock-gating units and functional units are disposed on the integrated circuit (IC) 10).
Regarding claim 43, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the apparatus is an integrated circuit on which the block is disposed (Figure 1, the root clock, clock-gating units and functional units are disposed on the integrated circuit (IC) 10).
Regarding claim 44, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein the apparatus is an application specific integrated circuit on which the block is disposed (Figure 1, the root clock, clock-gating units and functional units are disposed on the integrated circuit (IC) 10) [in some embodiments, the elements can be disposed on an ASIC].
Regarding claim 47, Chaudhuri and Wang teach the apparatus of claim 24. Chaudhuri further teaches wherein, for communications from the first domain into the second domain, the communications may be supported based on at least one of the pseudo-synchronous first-in-first-out queue or the pulse crosser (“the synchronization logic includes a double clock synchronizer 320 including a first flip-flop 322 timed at CLK2 and a second flip-flop 324 also timed at CLK2.” Par 0029) [this double clock synchronizer is the module used in the default path to translate a signal crossing domains, functionally equivalent to a pulse crosser].
Regarding claim 48, Chaudhuri and Wang teach the apparatus of claim 24. Wang further teaches wherein, for communications from the second domain into the first domain, the communications may be supported based on the pseudo- synchronous first-in-first-out queue (“The handshake signals may be used to convey handshaking information necessary to synchronize operation between two functional units 15, including situations in which the functional units 15 are operating at different clock frequencies with respect to one another” par 0024) [this describes the pseudo-synchronous communication supported by handshake signals between functional units (including communication from a second domain to a first domain) operating at different scaled frequencies (which is crucial for coordinating data flow across a specialized element like a FIFO)].
Claim 33 is rejected under 35 U.S.C. 103 as being unpatentable over Chaudhuri and Wang in view of Nijasure (US 2021/0157639 A1).
Regarding claim 33, Chaudhuri and Wang teach the apparatus of claim 32. However, Chaudhuri and Wang do not explicitly teach wherein the amount of the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses to be permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block.
In the analogous art, Nijasure teaches wherein the amount of the clock pulses of the clock signal of the block that are permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block is determined based on a mapping table that maps a set of workload thresholds to a set of fractions of clock pulses to be permitted to pass from the first portion of the clock distribution tree of the block to the second portion of the clock distribution tree of the block ("The control module 320 compares the workload information to the workload thresholds stored at the workload threshold registers 324…retrieves the program frequency for the program from the program frequency registers 322. The control module 320 then sends control signaling to the clock control module 110 to adjust the frequency of the CK clock signal to the retrieved program frequency." par 0029 and paragraph 31-35 and Figures 2 and 4) [under BRI, the comparison of workload information to workload thresholds and selecting a corresponding clock frequency (corresponds to a fraction of clock pulses) from stored program frequencies to adjust clock signal is analogous to the mapping table lookup].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chaudhuri, Wang and Nijasure before him before the effective filing date of the claimed invention, to have modified Chaudhuri and Wang to incorporate the teachings of Nijasure to permit clock pulses based on a mapping table as it allows for dynamically adjusting the clock frequency based on the workload to save power without suspending the operation.
Claims 38 and 39 are rejected under 35 U.S.C. 103 as being unpatentable over Chaudhuri and Wang in view of Ware et al. (US 2011/0235459 A1).
Regarding claim 38, Chaudhuri and Wang teach the apparatus of claim 24. However, Chaudhuri and Wang do not explicitly teach wherein the interface includes the pseudo-synchronous first-in-first-out queue and the pulse crosser.
In the analogous art, Ware teaches wherein the interface includes the pseudo-synchronous first-in-first-out queue and the pulse crosser (“a packet-alignment FIFO 371 is loaded with a sequence of transmit data packets (Tdata[i][7:0] and thus each an 8-bit packet in this example) in response to the controller core clock (PCK1) and unloaded (i.e., packet popped from head of FIFO or queue) into parallel register 367 in response to a buffer-delayed instance (FCK1[i]) of a de-framing clock signal (TCK1[i]),” par 0081) [this describes a FIFO as a component of a drift-compensating serializer/deserializer interface that uses active phase adjustment (pulse crossing) to transfer packets between domains] ("the controller core 105 includes a transaction queue 109 (or request queue) for queuing memory access requests received via a host interface (e.g., from a processor or other memory access requestor)," par 0056) [the queue is associated with the interface handling incoming requests].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chaudhuri, Wang and Ware before him before the effective filing date of the claimed invention, to have modified Chaudhuri and Wang to incorporate the teachings of Ware to include a pseudo- synchronous first-in-first-out queue in the interface to use its state to enable the power-mode controller to stop the clock during idle periods, thereby saving power.
Regarding claim 39, Chaudhuri and Wang teach the apparatus of claim 24. However, Chaudhuri and Wang do not explicitly teach wherein the interface includes a pulse-transition-pulse module.
In the analogous art, Ware teaches wherein the interface includes a pulse-transition-pulse module (“FIG. 16D illustrates an embodiment of a clock-phase-shifting circuit that provides a glitchless 0.5UI phase advance in response to a phase-advance signal (“Adv0.5UI). As shown, the circuit includes a ring-coupled pair of differential edge-triggered flip- flops 841, 843 that are clocked by rising and falling (positive and negative) edges of the bit-rate receive clock (RCK8[i]), respectively.” Par 0148) [this clock-phase-shifting circuit (corresponding to a pulse-transition-pulse module) uses ring-coupled differential edge-triggered flip- flops and a mux to execute controlled phase jumps (transitions) in the clock signal, thereby regulating the timing of generated pulses].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Chaudhuri, Wang and Ware before him before the effective filing date of the claimed invention, to have modified Chaudhuri and Wang to incorporate the teachings of Ware to include a pulse-transition-pulse module to enable the power-mode controller to stop the clock during idle periods, thereby saving power.
Claim 46 is rejected under 35 U.S.C. 103 as being unpatentable over Wang in view of Chaudhari.
Regarding claim 46, Wang teaches an apparatus (IC 10, Figure 1), comprising:
a block (Figure 1, clk gen 11 and root clock and CCG units 14 and functional units 15), wherein the block includes a set of elements configured to operate based on a clock signal applied to the block (Figure 1, the functional units 15 operate based on the root clock signals), wherein the block includes a clock distribution tree configured to distribute clock pulses of the clock signal to the set of elements of the block ("The root clock signal may be distributed, via additional instances of inverter 13, to various instances of a coarse clock-gating unit 14…The clock signal output by each coarse clock-gating unit 14 may be provided to, via another inverter 13, to a number of different leaf nodes 17 in each of functional units 15." par 0026 and Figure 2, clock tree 21 and claim 1), wherein the block is configured to control, based on information indicative of a workload on the block, which of the clock pulses of the clock signal are permitted to pass from the first portion of the clock distribution tree of the block into the second portion of the clock distribution tree of the block, wherein the block includes an interface between the first domain and the second domain (“clock control unit 12 may enable the clock signal output from a corresponding coarse clock-gating unit 14 for one of every N cycles of the root clock signal. For example, clock control unit 12 could effectively reduce the frequency of a clock signal output by a coarse clock-gating unit 14 by asserting the enable signal for only one of every four cycles of the root clock signal. This in turn results in the coarse clock-gating unit 14 outputting a clock signal having effectively ¼ the frequency of the root clock signal.” Par 0023 and “Each of the functional units 15 in the embodiment shown is coupled to signals indicative of performance (Performance' signal as shown) to clock control unit 12. Such indications may include indication of processing workload,” par 0022 and "the clock control unit may enable power savings by reducing the frequency of an instance of the operational clock signal as output by a coarse clock-gating unit when the corresponding functional unit is active but otherwise not processing a large workload." par 0010 and claims 1 and 6) [frequency is reduced based on workload by asserting an enable signal for only a fraction of the clock cycle, selectively permitting pulses to pass through the coarse clock-gating unit which supplies the operational clock signal to the functional unit (block)] [claim 1 describes the mechanism of allowing specific pulses to pass and block others; the apparatus gates/selectively enables pulses within the functional unit's clock path; the global clock distribution may correspond to a first portion of the block and the clock distribution within the functional unit may correspond to a second portion].
Wang does not explicitly teach wherein a first portion of the clock distribution tree of the block is configured to serve a first domain of the block including a first portion of the elements of the block, wherein a second portion of the clock distribution tree of the block is configured to serve a second domain of the block including a second portion of the elements of the block, wherein the interface includes at least one of a pseudo-synchronous first-in-first-out queue or a pulse crosser, wherein the interface is configured to support communications between the first domain and the second domain.
In the analogous art, Chaudhuri teaches wherein a first portion of the clock distribution tree of the block is configured to serve a first domain of the block including a first portion of the elements of the block, wherein a second portion of the clock distribution tree of the block is configured to serve a second domain of the block including a second portion of the elements of the block (“The master clock signal and the other clock signal are transmitted through a clock distribution tree to a circuit component. In a default mode, the circuit component receives the master clock signal at a first component block to create a first time domain for the first component block of the circuit component and the circuit component receives the other clock signal at a second component block to create a second time domain for the second component block of the circuit component.” Par 0017) [this shows a single circuit component (block) partitioned into two distinct blocks (portions) that receive two separate clock signals via the distribution tree, creating two separate clock domains],
wherein the block includes an interface between the first domain and the second domain, wherein the interface includes at least one of a pseudo-synchronous first-in-first-out queue or a pulse crosser, wherein the interface is configured to support communications between the first domain and the second domain (“As shown in FIG. 3, a signal crossing from a first time domain of the first component block 207 of the circuit component-2 206-2 to the second component block 209 of circuit component-2 having a second time domain, travels along a path” par 0028 and “the synchronization logic includes a double clock synchronizer 320 including a first flip-flop 322 timed at CLK2 and a second flip-flop 324 also timed at CLK2.” Par 0029) [the path between the component blocks (domains) functions as the interface, and the double clock synchronizer provides the required synchronization logic for communication, corresponds to the function of a pulse-crosser].
It would have been obvious to a person having ordinary skill in the art, having the teachings of Wang and Chaudhari before him before the effective filing date of the claimed invention, to have modified Wang to incorporate the teachings of Chaudhari to include synchronization logic to handle signals crossing clock domains to reliably transfer signals between blocks operating in different clock domains.
Response to Arguments
Applicant’s arguments, see pages 1-3, filed 9/15/2025, with respect to the rejection(s) of claim(s) 24 under 35 U.S.C. 102(a)(1) over Wang et al. have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Chaudhuri in view of Wang.
Chaudhuri and Wang teach an integrated circuit where separate clock domains (functional units/component blocks) are dynamically fed by a clock tree with workload-based pulse gating, which supports communications between these domains using synchronization logic (corresponding to a pulse crosser) or handshaking signals (pseudo-synchronous FIFO). Examiner respectfully points to the updated mapping of claim 23.
No additional arguments were presented as to the remaining claims. As such, the rejection is maintained.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/AYMAN FATIMA/Examiner, Art Unit 2176
/JAWEED A ABBASZADEH/Supervisory Patent Examiner, Art Unit 2176