Detailed Action
Summary
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
1.This office action is in response to the application filed on December 07,2023.
2. Claims 1-18 are pending and has been examined.
Priority
3. Acknowledgment is made of applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d), which the certified copy has been placed in the record of the file.
Information Disclosure Statement
4. The information disclosure statement (IDS) submitted on 12/07/2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Drawings
5. Drawings submitted on 12/07/2023 are acceptable.
Claim Objections
6. Claims 2,10 and 12-18 are objected to because of the following informalities:
Claim 2 recites “receives output currents” in line 2 should be “the receive output currents”.
Claim 10 recites “output currents” in line 2 should be “the output current”.
Claims 12-18 recite “performing phase shift” on the switch in line respectively should be “performing the phase shift” on the switch.
Claims 3-9 depend from claim 2, thus are also objected because of their dependency.
Claim Rejections - 35 USC § 103
7. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3 and 10-11 are rejected under 35 U.S.C. 103 as being unpatentable over Kezobo “250140054103” in a view of Yahyaoui NPL document “Switch Short-Circuit Fault Detection Algorithm based on Drain-to-Source Voltage Monitoring for a Fault Tolerant DC/DC Converter” Published on October 2016. Hereafter Yahayaoui.
In re to claim 1, Kezobo discloses an apparatus for diagnosing failure of an inverter (Figs. 1-12 is showing a technology of detecting an open fault of an inverter see praag.0001) , the apparatus comprising: switches (switching elements UP, UN, VP, VN, WP, and WN and diodes DUP, DUN, DVP, DVN, DWP, and DWN) coupled to three phases of A, B, and C, respectively (Figs. 1 and 9 shows an inventor 22 has phase A, B and C);
a measurer configured to measure each of output currents of the three phases (current detectors CT1, CT2, and CT3 respectively for detecting currents Iu, Iv, and Iw of the U-, V-, and W-phases, see prag.0041) ;
a comparison processor (current control means 23) configured to receive the output currents measured by the measurer (Iu, Iv, and Iw) and compare the received output currents with a set value (current command Iq* and ; and Id*, see Fig. 2 and further prag.0048, 0056, 0058)
a failure determination processor (fault detecting means 25 ) configured to detect a switch having an output current equal to or smaller than the set value (0071, 0105, 0117, 0340) based on the comparison performed by the comparison processor (Fig .6, shows fault detecting means 25 detect a fault in which the V-phase and the W-phase are placed in the open state S6, see parg.0109 -0018) to determine the switch as faulty (the fault detecting means 25 detects in which of the plurality of phases and an open-state fault has occurred, see parag.0065, 0067 ) upon detecting faulty switch are identify which phase switch (when the open-state fault is identified in the U-phase of the motor 2, the control on the motor 2 is continued by controlling the currents only for the other V-phase and W-phase see prag. 0473-0474. Furthermore see prag.0156, 0016, 0232) and duty ratio (Figs. 7-5 shows a duty cycle of the switches . Furthermore, see parag. 0053) .
Kezobo discloses a duty ratio but fails explicitly to discloses phase switch is faulty to change duty ratio of the switch determined to be faulty and to perform phase shift on switches not determined to be faulty.
Whereas, Yahayaoui discloses detection technique proposed to
identify the short circuited cell in a cascade H-bridge inverter (see page 2212, col. 2 lines 17-20) having which phase switch is faulty to change duty ratio of the switch determined to be faulty (method detects faults with a limitation law over the duty cycle (D) that must be considered to avoid false fault detection due to non-ideal behavior of power switches, delays and dead times, see pages 2212 col. 1, lines 12-15 and page 2212, col. 2, lines 13-23. Fig.7 shows a Switch Short-Circuit fault detection with a duty cycle around 80%) and to perform phase shift on switches not determined to be faulty ( Fig.9 it can be seen that healthy MOSFETs are subjected to an electrical stress due to the fault occurrence. A transition from six legs (phase shifted by T/6) to five legs (phase shifted by T/5) after fault isolation and converter reconfiguration is performed to solve this problem, see page 2216,col. 1, lines 1-9).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the diagnosing failure of inverter of Kezobo to include phase switch is faulty to change duty ratio of the switch determined to be faulty and to perform phase shift on switches not determined to be faulty as taught by Yahayaoui to improve the fault tolerance behavior and the fault tolerance capability of the IBC is enhanced by the fault tolerant action of PWM control without adding any additional components to the basic circuit, see page.2215, col. 1, lines 31-37.
In re to claim 2, Kezobo as modified discloses (Figs. 1-12) wherein the comparison processor receives output currents of at least two phases coupled to a load and compares the received output currents with the set value (Iu, Iv, and Iw and compare current command Iq* and Is ; and Id*, see Figs. 1-2, see parag.0005).
In re to claim 3, Kezobo discloses (Figs. 1-12) wherein the failure determination processor (25) is configured to: determine whether any of the switches (UP, UN, VP, VN, WP, and WN and diodes DUP, DUN, DVP, DVN, DWP, and DWN), located at upper and lower ends of each of the three phases (U, V and W phases), has an output current (Iu, Iv, and Iw ) equal to or smaller than the set value and determine the switch having the output current equal to or smaller than the set value as faulty (see prag. 0071, 0105, 0117, 0340) and duty ratio (Figs. 7-8 shows a duty cycle of the switches . Furthermore, see paragraph [0053]).
Furthermore, Yahayaou discloses control a duty ratio of a phase determined to be faulty and perform phase shift on phases operating in normal state (method detects faults with a limitation law over the duty cycle (D) that must be considered to avoid false fault detection due to non-ideal behavior of power switches, delays and dead times, see pages 2212 col. 1, lines 12-15 and page 2212, col. 2, lines 13-23. Fig.7 shows a Switch Short-Circuit fault detection with a duty cycle around 80%) and to perform phase shift on switches not determined to be faulty ( Fig.9 it can be seen that healthy MOSFETs are subjected to an electrical stress due to the fault occurrence. A transition from six legs (phase shifted by T/6) to five legs (phase shifted by T/5) after fault isolation and converter reconfiguration is performed to solve this problem, see page 2216,col. 1, lines 1-9).
In re to claim 10, Kezobo discloses (Figs. 1-12) , wherein the comparison processor is further configured to compare output currents measured two or more times by the measurer with the set value (current detectors CT1, CT2, and CT3 respectively for detecting currents Iu, Iv, and Iw of the U-, V-, and W-phases and compare with the set value, see 0071, 0105, 0117, 0340. Examiner noted that currents measured two or more times is based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome)
In re to claim 11, Kezobo discloses a method of diagnosing failure of an inverter (Figs. 1-12 is showing a technology of detecting an open fault of an inverter see praag.0001), the method comprising:
Measuring , by a measurer, output currents two times (current detectors CT1, CT2, and CT3 respectively for detecting currents Iu, Iv, and Iw of the U-, V-, and W-phases, see prag.0041. Examiner noted that currents measured two or more times is based upon a design needs / intended purpose for specific reason or goal for acquiring a desired outcome);
Comparing (current control means 23), by a comparison processor, the output currents (Iu, Iv, and Iw) with a set value (current command Iq* and ; and Id*, see Fig. 2 and further prag.0048, 0056, 0058);
Determining (fault detecting means 25 ), by a failure determination processor, a failure of any of switches located at upper and lower ends of each of three phases based on the measured currents (0071, 0105, 0117, 0340); and
when any of the switches located at the upper and lower ends of each of the three phases is determined to be faulty (the fault detecting means 25 detects in which of the plurality of phases three phases an open-state fault has occurred , see parag.0065, 0067 ), controlling, by the failure determination processor (when the open-state fault is identified in the U-phase of the motor 2, the control on the motor 2 is continued by controlling the currents only for the other V-phase and W-phase see prag. 0473-0474. Furthermore see prag.0156, 0016, 0232) and duty ratio (Figs. 7-5 shows a duty cycle of the switches. Furthermore, see parg.0053) .
Kezobo discloses a duty ratio but fails explicitly to discloses a duty ratio of a phase determined to be faulty and performing phase shift on a switch of a phase in normal operation.
Whereas, Yahayaoui discloses detection technique proposed to
identify the short circuited cell in a cascade H-bridge inverter (see page 2212, col. 2 lines 17-20) having which phase switch is faulty to change duty ratio of the switch determined to be faulty (method detects faults with a limitation law over the duty cycle (D) that must be considered to avoid false fault detection due to non-ideal behavior of power switches, delays and dead times, see pages 2212 col. 1, lines 12-15 and page 2212, col. 2, lines 13-23. Fig.7 shows a Switch Short-Circuit fault detection with a duty cycle around 80%) and performing phase shift on a switch of a phase in normal operation ( Fig.9 it can be seen that healthy MOSFETs are subjected to an electrical stress due to the fault occurrence. A transition from six legs (phase shifted by T/6) to five legs (phase shifted by T/5) after fault isolation and converter reconfiguration is performed to solve this problem, see page 2216,col. 1, lines 1-9).
Therefore, it would have been obvious to one of ordinary skilled person in the art before the effective filing date of the claimed invention to have modified the diagnosing failure of inverter of Kezobo to include phase switch is faulty to change duty ratio of the switch determined to be faulty and to performing phase shift on a switch of a phase in normal operation as taught by Yahayaoui to improve the fault tolerance behavior and the fault tolerance capability of the IBC is enhanced by the fault tolerant action of PWM control without adding any additional components to the basic circuit, see page.2215, col. 1, lines 31-37.
Allowable Subject Matter
8. Claims 4-9 and 12-18 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Claim 4 , the prior art of record fails to disclose or suggest the apparatus including the limitation of “when a phase A upper switch S1 is determined to be faulty, the failure determination processor sets a phase A duty ratio to 0, performs Phase A/180 phase shift on phase B, and performs |(Phase C/180 - Phase A/180)| phase shift on phase C. ”
Claim 5, the prior art of record fails to disclose or suggest the apparatus including the limitation of “wherein, when a phase A lower switch S2 is determined to be faulty, the failure determination processor sets a phase A duty ratio to 1, performs 1-Phase A/180 phase shift on phase B, and performs 1- |(Phase C/180 - Phase A/180)| phase shift on phase C.”
Claim 6, the prior art of record fails to disclose or suggest the apparatus including the limitation of “wherein, when a phase B upper switch S3 is determined to be faulty, the failure determination processor sets a phase B duty ratio to 0, performs Phase A/180 phase shift on phase A, and performs (Phase C/180) phase shift on phase C.”
Claim 7, the prior art of record fails to disclose or suggest the apparatus including the limitation of “wherein, when a phase B lower switch S4 is determined to be faulty, the failure determination processor sets a phase B duty ratio to 1, performs 1-Phase A/180 phase shift on phase A, and performs (1- Phase C/180) phase shift on phase C.”
Claim 8, the prior art of record fails to disclose or suggest the apparatus including the limitation of “wherein, when a phase C upper switch S5 is determined to be faulty, the failure determination processor sets a phase C duty ratio to 0, performs |Phase A/180-Phase C/180 | phase shift on phase A, and performs (Phase C/180) phase shift on phase B.”
Claim 9, the prior art of record fails to disclose or suggest the apparatus including the limitation of “wherein, when a phase C lower switch S6 is determined to be faulty, the failure determination processor sets a phase C duty ratio to 1, performs 1 - | (Phase A/180-Phase C/1 80) | phase shift on phase A, and performs 1- (Phase C/180) phase shift on phase B. ”
Claim 12, the prior art of record fails to disclose or suggest the method including the limitation of “wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase A upper switch S1 is determined to be faulty, setting a phase A duty ratio to 0, performing Phase A/180 phase shift on phase B, and performing I(Phase C/180 - Phase A/180) | phase shift on phase C, by the failure determination processor.”
Claim 13, the prior art of record fails to disclose or suggest the method including the limitation of “wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase A lower switch S2 is determined to be faulty, setting a phase A duty ratio to 1, performing 1-PhaseA/180 phase shift on phase B, and performing 1- |(Phase C/180 - Phase A/180)I phase shift on phase C, by the failure determination processor.”
Claim 14, the prior art of record fails to disclose or suggest the method including the limitation of “wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase B upper switch S3 is determined to be faulty, setting a phase B duty ratio to 0, performing Phase A/180 28 phase shift on phase A, and performing (Phase C/180) phase shift on phase C, by the failure determination processor.”
Claim 15, the prior art of record fails to disclose or suggest the method including the limitation of “wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase B lower switch S4 is determined to be faulty, setting a phase B duty ratio to 1, performing 1- Phase A/180 phase shift on phase A, and performing (1 -Phase C/1 80) phase shift on phase C, by the failure determination processor.”
Claim 16, the prior art of record fails to disclose or suggest the method including the limitation of “wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase C upper switch S5 is determined to be faulty, setting a phase C duty ratio to 0, performing I Phase A/1 80- Phase C/1 80 | phase shift on phase A, and performing (Phase C/180) phase shift on phase B, by the failure determination processor.”
Claim 17, the prior art of record fails to disclose or suggest the method including the limitation of “ wherein performing phase shift on the switch of the phase in normal operation comprises, when a phase C lower switch S6 is determined to be faulty, setting a phase C duty ratio to 1, performing 1- I(Phase A/180-PhaseC/180)I phase shift on phase A, and performing 1- (Phase C/180) phase shift on phase B, by the failure determination processor. ”
Claim 18, the prior art of record fails to disclose or suggest the method including the limitation of “ wherein performing phase shift on the switch of the phase in normal operation comprises, changing, by the failure determination processor, duty ratio of the switch determined to be faulty and performing phase shift on switches not determined to be faulty so that an effective value current equal to a current in a normal state is applied to the phase determined as switch failure. ”
Conclusion
9. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Itamoto “20140300305” invention relates to a motor control device that controls driving of a motor.
Rastogi “20220115958” the present disclosure relates generally to power converters. More specifically, the disclosure relates to a method and system for detecting open-circuit faults in three-phase Dual Active Bridge (DAB) converters.
Erodos “20130187678” the present invention relates to a method of detecting a failure of an alternator.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SISAY G TIKU whose telephone number is (571)272-6898. The examiner can normally be reached 8:30AM-6:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice . If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Tran, Thienvu Vu can be reached on (571) 270-1276. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SISAY G TIKU/
Primary Examiner, Art Unit 2838