DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Election/Restrictions
Applicant’s election without traverse of Group I (Claims 1-13) in the reply filed on 7/15/26 is acknowledged.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Information Disclosure Statement
The information disclosure statement (IDS) submitted on 12/8/23 was filed. The submission is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement has been considered by the examiner.
Drawings
The drawings were received on 6/24/21. These drawings are acceptable.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-13 are rejected under 35 U.S.C. 103 as being unpatentable over US 2021/0167471 A1 (US'471) in view of US 2020/0051739 A1 (US'739) and US 8,304,115 B1 (US'115).
As to Claim 1:
US’471 discloses a battery comprising a power-generating element, namely multilayer solid-state battery 100, including an electrode layer, namely positive-electrode layer 110; a counter-electrode layer placed to face the electrode layer, namely negative-electrode layer 120; and a solid-electrolyte layer 130 located between positive-electrode layer 110 and negative-electrode layer 120 (US’471 [0035], [0038]-[0039], Fig. 1).
US’471 further discloses an insulating layer, namely insulating cover layer 30, which covers the top surface 100A and side surface 100B of solid-state battery 100 and entirely and extensively encloses the battery (US’471 [0057], [0060]-[0063], Fig. 2).
Under the broadest reasonable interpretation, the claimed first and second insulating films do not require separately formed layers and may constitute respective portions of a single continuous insulating layer. The portion of insulating cover layer 30 covering top surface 100A constitutes the first insulating film. Top surface 100A is expressly identified as one of the principal or main surfaces of solid-state battery 100. Because insulating cover layer 30 covers the entire top-surface region, the top-surface portion extends inward from the peripheral ends of the power-generating element when viewed in a planar view of principal surface 100A (US’471 [0060]-[0061], Fig. 2).
The portion of insulating cover layer 30 covering side surface 100B constitutes the second insulating film. This side-surface portion covers the side surface of the power-generating element and is continuous with the peripheral ends of the top-surface portion. In particular, US’471 forms one insulating cover layer by disposing a resin precursor to entirely cover the solid-state battery and curing or molding the precursor into the insulating cover layer. Thus, the top-surface and side-surface portions are portions of the same molded insulating cover layer and meet continuously at the peripheral ends of the top-surface portion (US’471 [0060]-[0063], [0152]-[0154], Figs. 2 and 15(C)-15(D)).
However, US’471 does not expressly disclose that the second insulating film covering side surface 100B is thinner than the first insulating film covering principal surface 100A. Although US’471 discloses a preferred thickness range for insulating cover layer 30, US’471 does not differentiate the thickness of the side-surface portion from the thickness of the principal-surface portion (US’471 [0063]).
US’739 discloses a multilayer ceramic device having first and second insulating side-margin portions 112 and 113 formed on respective side surfaces of a multilayer body and upper and lower insulating cover portions 114 and 115 formed on respective principal surfaces of the multilayer body (US’739 [0036]-[0039], [0053]-[0058], [0061], Fig. 4). US’739 expressly discloses that the side-margin portions have an average thickness of 2-10 μm, whereas each upper and lower cover portion has a thickness of 20 μm. Accordingly, US’739 expressly teaches an insulating structure in which the side-surface insulating portion is thinner than the principal-surface insulating portion (US’739 [0038], [0053]-[0058], [0061]-[0064], Fig. 4).
US’739 further explains that limiting the thickness of the side-margin portions secures a larger overlapping active-electrode region and permits implementation of a smaller device, while the thicker upper and lower cover portions protect the internal electrodes from physical and chemical stress (US’739 [0051]-[0052], [0057]-[0058], [0062]-[0064]).
US’471, US’739, and US’115 constitute analogous art. US’471 and US’115 concern compact multilayer solid-state batteries, while US’739 concerns a compact multilayer ceramic capacitor having stacked internal electrodes and peripheral insulating portions. US’115 expressly teaches that a solid-state multilayer ceramic battery may employ construction concepts utilized in the multilayer ceramic capacitor industry and may be processed using equipment employed in that industry (US’115, Abstract; Col. 5, lines 1-28). Thus, US’115 expressly establishes the technical pertinence of US’739’s multilayer-ceramic insulating structure to the multilayer solid-state battery of US’471.
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to configure US’471’s continuous insulating cover layer 30 so that its side-surface portion is thinner than its principal-surface portion, as taught by US’739, in order to reduce the lateral space occupied by the insulating layer and preserve a larger active-electrode region while retaining greater protective thickness over the principal surface. Such a modification is expressly supported by US’739’s teachings that thinner side-margin portions promote device miniaturization and preserve the active-electrode overlap area, whereas thicker principal-surface cover portions protect the internal electrodes from physical and chemical stress (US’739 [0051]-[0052], [0057]-[0058], [0062]-[0064]). US’115 provides an express basis for applying multilayer-capacitor construction teachings to a multilayer ceramic solid-state battery (US’115, Abstract; Col. 5, lines 1-28). The proposed modification would retain US’471’s single continuous insulating cover across the principal and side surfaces while providing the relative thickness relationship taught by US’739.
As to Claim 2:
US’471 discloses the battery according to Claim 1, as set forth in the rejection of Claim 1 above. US’471 further discloses that positive-electrode layer 110 and negative-electrode layer 120 each contain an electrode active material and may respectively include a positive-electrode current-collector layer and a negative-electrode current-collector layer (US’471 [0040], [0051]-[0052]).
US’471 further discloses forming a solid-electrolyte sheet, applying positive- or negative-electrode paste containing the respective electrode active material onto the solid-electrolyte sheet, and printing a current-collector layer over the electrode paste before stacking and firing the layers. The resulting electrode structure therefore includes an electrode collector and an electrode active-material layer located between the electrode collector and solid-electrolyte layer (US’471 [0133]-[0137]).
As to Claim 3:
US’471 discloses the battery according to Claim 2, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 2 above.
US’471 further discloses a power-generating element in the form of multilayer solid-state battery 100. The battery laminate includes positive-electrode layer 110, negative-electrode layer 120, and solid-electrolyte layer 130 interposed between the positive- and negative-electrode layers. Positive-electrode layer 110 contains a positive-electrode active material, and negative-electrode layer 120 contains a negative-electrode active material (US’471 [0035], [0038]–[0040], Fig. 1).
US’471 further discloses insulating cover layer 30 disposed around solid-state battery 100 so as to entirely surround the battery without allowing any battery surface to remain externally exposed. In particular, insulating cover layer 30 covers the entire top surface 100A and side surface 100B of solid-state battery 100 (US’471 [0057], [0060]–[0063], Fig. 2). Accordingly, the portion of insulating cover layer 30 constituting the second insulating film covers, on side surface 100B of the power-generating element, the exposed side edges of the active-material-containing electrode layers 110 and 120 and solid-electrolyte layer 130. US’471 therefore discloses that the second insulating film covers the electrode active-material layer and the solid-electrolyte layer on the side surface of the power-generating element (US’471 [0038]–[0040], [0057], [0060], Figs. 1–2).
As to Claim 4:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses that positive-electrode layer 110 and negative-electrode layer 120 each contain an electrode active material and may respectively include a positive-electrode current-collector layer and a negative-electrode current-collector layer (US’471 [0038]–[0040], [0051]–[0052]).
US’471 also discloses forming a solid-electrolyte sheet, applying positive- or negative-electrode paste containing the respective electrode active material onto the solid-electrolyte sheet, and printing a current-collector layer over the electrode paste. Accordingly, the resulting electrode layer includes an electrode collector and an electrode active-material layer located between the electrode collector and the solid-electrolyte layer (US’471 [0133]–[0138]).
However, US’471 does not expressly disclose that the first insulating film extends inward from the ends of the power-generating element and is located between the electrode active-material layer and the solid-electrolyte layer. US’471’s insulating cover layer 30 is disposed externally over the principal and side surfaces of solid-state battery 100, rather than internally at the interface between an electrode active-material layer and a solid-electrolyte layer (US’471 [0057], [0060]–[0063], Fig. 2).
US’115 discloses a multilayer solid-state battery having porous electrode regions formed on a dense solid-electrolyte tape. US’115 screen-prints porous electrode paste on the dense electrolyte tape in a pattern that creates electrode areas separated by borders on several sides, and subsequently fills the borders with dense insulating paste printed in the negative pattern of the porous electrode layer. The dense border is printed to the same level as the porous electrode prints and defines the peripheral boundaries of the porous active-material-containing electrode regions (US’115, Col. 9, lines 37–65).
US’115 further discloses an embodiment containing an internal metal current collector. After printing two porous-electrode portions, US’115 prints a continuous platinum current-collector layer, applies a dense boundary-paste layer, and then prints additional porous-electrode portions and dense boundary layers. Thus, US’115 teaches combining an internal current collector, an active-material-containing porous electrode region, a dense solid-electrolyte layer, and dense insulating boundary material at the peripheral interface of the electrode region (US’115, Col. 10, lines 23–55).
US’739 discloses first and second insulating side-margin portions 112 and 113 disposed over exposed peripheral ends of internal conductive layers. The side-margin portions have an average thickness of 2–10 μm and prevent short-circuiting of the internal electrodes exposed at the side surfaces (US’739 [0036]–[0038], [0061]–[0064], Fig. 4). US’739 therefore teaches extending peripheral insulation over the side surface while maintaining the side insulation thinner than the inwardly extending dense insulating boundary. US’739 further explains that the thinner side margins preserve a larger active region and facilitate device miniaturization (US’739 [0051]–[0052], [0062]–[0064]).
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify US’471’s multilayer solid-state battery by providing a dense peripheral insulating boundary of the type taught by US’115, extending the boundary inward over the solid-electrolyte layer and beneath the peripheral portion of the electrode active-material layer, and joining the outer end of that boundary to US’471’s side-surface insulating cover. Such a modification would have provided electrode areas separated by dense insulating borders, as taught by US’115, while insulating the exposed peripheral electrode regions to prevent short-circuiting, as taught by US’739 (US’115, Col. 9, lines 37–65; US’739 [0061]–[0064]). It further would have been obvious to form the side-surface portion thinner than the internal first insulating film, consistent with US’739’s teaching that thin side margins preserve a larger active region and permit device miniaturization (US’739 [0051]–[0052], [0062]–[0064]). The resulting battery would include an electrode collector, an electrode active-material layer located between the collector and solid-electrolyte layer, and a first insulating film located between the electrode active-material layer and the solid-electrolyte layer, as required by Claim 4.
As to Claim 5:
US’471 discloses the battery according to Claim 2, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 2 above.
US’471 further discloses that solid-state battery 100 includes positive-electrode layer 110, negative-electrode layer 120 placed to face positive-electrode layer 110, and solid-electrolyte layer 130 interposed between positive-electrode layer 110 and negative-electrode layer 120. Accordingly, positive-electrode layer 110 constitutes the claimed electrode layer, and negative-electrode layer 120 constitutes the claimed counter-electrode layer (US’471 [0038]–[0040], Fig. 1). Thus, US’471 expressly discloses that the electrode layer is a positive-electrode layer and the counter-electrode layer is a negative-electrode layer, as required by Claim 5.
As to Claim 6:
US’471 discloses the battery according to Claim 2, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 2 above.
US’471 further discloses a multilayer solid-state battery including positive-electrode layer 110, negative-electrode layer 120, and solid-electrolyte layer 130 interposed between the positive- and negative-electrode layers. Each electrode layer contains an electrode active material and may include a respective electrode current-collector layer (US’471 [0035], [0038]–[0040], [0051]–[0052]). US’471 also discloses insulating cover layer 30 covering the principal and side surfaces of the solid-state battery (US’471 [0057], [0060]–[0063], Fig. 2).
However, US’471 does not expressly disclose the inherited Claim 2 limitation requiring the first insulating film to be located between the electrode collector and the electrode active-material layer. US’471 also does not expressly disclose that the first insulating film is located in a region where a length of the electrode active-material layer from an outer periphery, in a plan view of the principal surface of the power-generating element, is shorter than or equal to 1 mm.
US’115 discloses a multilayer solid-state battery having porous electrode regions that are subsequently impregnated with active-material precursors and converted into active-material-containing electrode layers. The porous electrode regions are separated by peripheral borders filled with dense boundary paste (US’115, Col. 9, lines 37–65). US’115 further discloses printing a continuous platinum current-collector layer using the same pattern as the porous electrode, applying a dense boundary-paste layer after printing the current collector, and subsequently printing additional porous-electrode portions and dense boundary layers. The resulting structure includes a thin, continuous current collector within the active-material-containing porous electrode and a dense peripheral boundary adjacent the collector and porous electrode region (US’115, Col. 10, lines 23–55). As explained in the rejection of Claim 2, these teachings support providing the peripheral first insulating film between the electrode collector and the electrode active-material layer.
US’739 discloses a compact multilayer ceramic structure in which the dielectric layer and the internal electrode have the same plan-view width, and expressly teaches that the width of the dielectric layer and internal electrode may be 100–900 μm (US’739 [0049]–[0050]). US’739 further discloses insulating side-margin portions having a thickness of 2–10 μm over the exposed distal ends of the internal electrodes (US’739 [0036]–[0038], [0061]–[0064]). Because US’115 prints its current collector with the same pattern as its active-material-containing porous electrode, dimensioning that common electrode pattern according to US’739’s 100–900 μm range would provide an electrode active-material layer having a plan-view width no greater than 900 μm, or 0.9 mm. The dense peripheral boundary constituting the first insulating film would therefore necessarily be located within 0.9 mm of an outer periphery of the electrode active-material layer.
US’739 explains that limiting the peripheral margin increases the overlapping active-electrode region and permits implementation of a compact multilayer device, while retaining sufficient peripheral insulation to prevent short-circuiting and maintain mechanical strength (US’739 [0051]–[0052], [0062]–[0069]).
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify US’471’s multilayer solid-state battery, as set forth in the rejection of Claim 2, by providing the peripheral first insulating film and same-pattern internal current collector and active-material-containing electrode region taught by US’115, and by dimensioning the plan-view width of that electrode region within US’739’s expressly disclosed range of 100–900 μm. The modification would have preserved a larger active-electrode region and facilitated implementation of a compact multilayer battery while maintaining peripheral insulation and preventing short-circuiting, as taught by US’739 (US’739 [0051]–[0052], [0061]–[0069]). Because the maximum disclosed width of 900 μm equals 0.9 mm, the peripheral first insulating film would be located in a region where the length of the electrode active-material layer from an outer periphery is shorter than or equal to 1 mm, thereby producing the structure required by Claim 6.
As to Claim 7:
US’471 discloses the battery according to Claim 2, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 2 above.
US’471 further discloses insulating cover layer 30 entirely surrounding solid-state battery 100 without allowing the battery surfaces to remain externally exposed. In particular, insulating cover layer 30 covers the entire top-surface region 100A and the entire side-surface region 100B of solid-state battery 100 (US’471 [0057], [0060]–[0063], Fig. 2).
However, US’471 does not expressly disclose the Claim 2 arrangement in which the first insulating film is located between the electrode collector and the electrode active-material layer. Consequently, US’471 alone does not expressly disclose that its side-surface insulating film extends from the ends of such an internally located first insulating film in first and second mutually opposite directions along the side surface of the power-generating element.
US’115 discloses a multilayer solid-state battery having porous electrode layers containing active materials, a solid-electrolyte layer between the electrode layers, and thin, continuous internal metal current collectors located within the porous active-material-containing electrode layers (US’115, Col. 3, lines 60–67; Col. 4, lines 1–17, 55–67; Col. 10, lines 23–55; Fig. 1). US’115 further discloses forming dense boundary material around the porous electrode regions and applying a dense boundary-paste layer after printing an internal platinum current-collector layer and before printing additional porous-electrode material (US’115, Col. 7, lines 36–50; Col. 9, lines 37–65; Col. 10, lines 23–55). As explained in the rejection of Claim 2, these teachings support locating the peripheral first insulating film between the electrode collector and the electrode active-material layer.
US’739 discloses first and second insulating side-margin portions 112 and 113 disposed on both side surfaces of a multilayer body, including over the exposed distal ends of the internal electrodes (US’739 [0036]–[0039], [0060]–[0063], Fig. 4). The side-margin portions extend along the side surfaces of active portion A between upper cover portion 114 and lower cover portion 115 (US’739 [0053]–[0058], [0061], Fig. 4). Thus, when US’739’s full-height side-margin structure is applied to the internally located peripheral first insulating film of the Claim 2 combination, the side-surface insulating film necessarily includes:
a first portion extending from the ends of the first insulating film in a first direction along the side surface of the power-generating element; and
a second portion extending from the same ends of the first insulating film in a second direction opposite to the first direction along the side surface of the power-generating element.
In particular, because the ends of the first insulating film are located internally within the electrode-layer stack, while the side-surface insulating film extends along the side surface above and below those internal ends, one portion extends toward one principal surface and another portion extends toward the opposite principal surface (US’739 [0036]–[0039], [0053]–[0061], Fig. 4; US’115, Col. 9, lines 37–65; Col. 10, lines 23–55).
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify US’471’s multilayer solid-state battery, as set forth in the rejection of Claim 2, by providing the internally located peripheral first insulating film supported by US’115 and extending US’471’s side-surface insulating film along the entire side surface above and below the ends of that first insulating film, consistent with US’739’s full-height side-margin portions. Such a configuration would have insulated the exposed peripheral regions of the internal conductive layers to prevent short-circuiting, as taught by US’739, while entirely enclosing and protecting the battery side surface against external exposure and water-vapor transmission, as taught by US’471 (US’739 [0061]–[0064]; US’471 [0056]–[0063]). The resulting side-surface insulating film would necessarily have a first portion extending from the ends of the first insulating film in a first direction and a second portion extending from those ends in the opposite direction, thereby producing the structure required by Claim 7.
As to Claim 8:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses a power-generating element including positive-electrode layer 110, negative-electrode layer 120 placed to face positive-electrode layer 110, and solid-electrolyte layer 130 located between the positive- and negative-electrode layers. The positive- and negative-electrode layers contain respective electrode active materials and may include respective electrode current-collector layers (US’471 [0038]–[0040], [0051]–[0052], Fig. 1).
US’471 further discloses forming an electrode layer by applying an electrode paste containing an electrode active material onto a solid-electrolyte sheet and printing a current-collector layer over the electrode paste. Thus, the resulting electrode active-material layer is located between the electrode collector and the solid-electrolyte layer (US’471 [0133]–[0136]).
US’471 also discloses that an outermost layer of the battery stack may be an electrode layer and that insulating cover layer 30 covers the entire top surface 100A and side surface 100B of solid-state battery 100 (US’471 [0057], [0060]–[0063], [0135]–[0136], Fig. 2). In the disclosed arrangement in which the outermost electrode layer includes a current-collector layer printed over the electrode active-material layer, the portion of insulating cover layer 30 covering top surface 100A constitutes the first insulating film and faces the electrode active-material layer across the intervening electrode collector. US’471 therefore teaches that the first insulating film faces the electrode active-material layer across the electrode collector, as required by Claim 8.
As to Claim 9:
US’471 discloses the battery according to Claim 8, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 8 above.
US’471 further discloses a solid-state battery laminate including positive-electrode layer 110, negative-electrode layer 120, and solid-electrolyte layer 130 interposed between the positive- and negative-electrode layers. The electrode layers contain respective electrode active materials and may include respective electrode current-collector layers (US’471 [0038]–[0040], [0051]–[0052], Fig. 1).
US’471 discloses forming the laminate by applying electrode-active-material paste to solid-electrolyte sheets, printing a current-collector layer over the electrode paste, stacking the resulting sheets, and cutting the laminate to a prescribed size (US’471 [0133]–[0138]). US’471 further discloses insulating cover layer 30 entirely surrounding solid-state battery 100 without allowing any battery surface to remain externally exposed. In particular, insulating cover layer 30 covers the entire side-surface region 100B of solid-state battery 100 (US’471 [0057], [0060]–[0063], Fig. 2). Accordingly, the portion of insulating cover layer 30 constituting the second insulating film covers, on the side surface of the power-generating element, the side portions of the electrode current-collector layer, the electrode active-material layer, and the solid-electrolyte layer, as required by Claim 9.
As to Claim 10:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses the first insulating film comprises at least one of an inorganic insulating material and a resin material (paragraphs [0062], [0063], [0065], [0101], [0102], explicitly disclosing that insulating cover layer 30 covering the top principal surface comprises a resin material, an inorganic material, or an inorganic insulating material such as silica, alumina, titanium oxide, or zirconium oxide).
As to Claim 11:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses the second insulating film covers a region of the side surface of the power-generating element (paragraphs [0013], [0060], [0064], [0117], [0118], FIG. 2, FIG. 14).
However, US'471 does not explicitly disclose that the second insulating film is thinner than the first insulating film (noting in paragraph [0109] that dry-plated or sputtered insulating films may have a substantially same thickness dimension at both local locations on top and side surfaces), nor does US'471 explicitly disclose that a region of the side surface of the power-generating element that is not covered with the second insulating film and a surface of the second insulating film that faces away from the power-generating element are flush with each other.
US'739 discloses a multi-layer ceramic component having side margin insulating portions (second insulating film) covering side surfaces of an active electrode stack and cover portions (first insulating film) covering principal surfaces, wherein the side margin portions have an average thickness of 2 µm to 10 µm (paragraphs [0038], [0063]), whereas each of the cover portions on the principal surfaces has a thickness of 20 µm (paragraph [0057]), thereby explicitly teaching a second insulating film covering the side surface that is thinner than the first insulating film extending over the principal surface; and further discloses that the side margin insulating film is formed in a side margin region such that the outer surface of the second insulating film and an uncovered region of the side surface are flush with each other to eliminate surface steps and maintain uniform exterior dimensions (paragraphs [0012], [0036], [0112], [0117], [0120], FIG. 4, FIGS. 5E–5F). Furthermore, US'115 discloses a solid-state multi-layer ceramic battery (Col. 1, lines 10–25; Col. 2, lines 5–20) and explicitly teaches applying multi-layer ceramic capacitor (MLCC) construction concepts, margin/edge insulation layouts, and ceramic processing technologies directly to multi-layer solid-state ceramic batteries (Col. 1, lines 15–25; Col. 2, lines 5–20; Col. 3, lines 20–35; Col. 4, line 55 to Col. 5, line 15).
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify the insulating cover layer structure of US'471 by configuring the second insulating film covering the side surface to be thinner than the first insulating film extending over the principal surface, and arranging the second insulating film such that a region of the side surface not covered with the second insulating film and a surface of the second insulating film that faces away from the power-generating element are flush with each other, as taught by US'739 in view of the MLCC adaptation teachings of US'115, in order to eliminate height steps along the lateral edges, improve surface mountability and packaging density, and minimize lateral dead space to maximize volumetric energy density while preventing short-circuit defects.
As to Claim 12:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses insulating cover layer 30 covering the entire principal surface 100A and side surface 100B of solid-state battery 100. Under the interpretation applied in the rejection of Claim 1, the portion covering principal surface 100A constitutes the first insulating film, and the portion covering side surface 100B constitutes the second insulating film. These portions form parts of the same continuous insulating cover layer (US’471 [0057], [0060]–[0063], Fig. 2).
US’471 also discloses forming insulating cover layer 30 by disposing a resin precursor so as to entirely cover solid-state battery 100 and curing or molding the resin precursor. Alternatively, insulating cover layer 30 may be formed by an application method, such as spraying, so that its sectional profile reflects the outlines of supporting substrate 10 and solid-state battery 100 (US’471 [0152], [0159], Figs. 15(C) and 16).
However, US’471 does not expressly disclose that the thickness of the second insulating film becomes smaller as the distance from the first insulating film increases. US’471 provides a general thickness range for insulating cover layer 30 but does not expressly disclose a directional thickness profile along the side surface (US’471 [0063]).
US’739 discloses a multilayer ceramic device having upper and lower insulating cover portions 114 and 115 on its principal surfaces and first and second insulating side-margin portions 112 and 113 on its side surfaces (US’739 [0036]–[0039], [0053]–[0061], Fig. 4). US’739 expressly discloses that each principal-surface cover portion may have a thickness of 20 μm, whereas each side-margin portion has an average thickness of 2–10 μm. Thus, US’739 teaches an insulating structure in which the side-surface insulation is substantially thinner than the adjoining principal-surface insulation (US’739 [0038], [0053]–[0058], [0061]–[0064], Fig. 4).
US’739 further explains that reducing the thickness of the side-margin portions increases the overlapping active-electrode region and permits implementation of a smaller multilayer device, while the principal-surface cover portions protect the internal electrodes from physical and chemical stress (US’739 [0051]–[0052], [0057]–[0058], [0062]–[0064]). US’739 therefore provides a reference-based reason to retain greater insulating thickness adjacent the principal-surface cover while reducing the insulating thickness along the side surface.
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify US’471’s continuous insulating cover layer 30 according to the relative-thickness teachings of US’739 by forming the side-surface portion with a thickness that transitions from a greater thickness adjacent the principal-surface first insulating film to a smaller thickness at locations progressively farther from the first insulating film. The modification would have retained greater insulating protection near the principal-surface cover while reducing the lateral space occupied by the side-surface insulation and preserving a larger active-electrode region, consistent with the expressly stated benefits of US’739 (US’739 [0051]–[0052], [0057]–[0058], [0062]–[0064]). US’471’s disclosed resin-application and spraying methods provide a method of forming the resulting continuous profiled cover layer (US’471 [0152], [0159]). US’115 expressly supports applying multilayer-capacitor construction teachings to a multilayer ceramic solid-state battery (US’115, Abstract; Col. 5, lines 1–28). The resulting second insulating film would become thinner as its distance from the first insulating film increases, thereby producing the structure required by Claim 12.
As to Claim 13:
US’471 discloses the battery according to Claim 1, except for the limitations supplied by US’739 and US’115, as set forth in the rejection of Claim 1 above.
US’471 further discloses the solid electrolyte layer contains a solid electrolyte having lithium-ion conductivity (paragraphs [0038], [0041], [0048], [0049], explicitly disclosing solid electrolyte layer 130 located between positive electrode layer 110 and negative electrode layer 120, where the solid electrolyte is a material capable of conducting lithium ions).
However, US'471 does not explicitly disclose that the second insulating film is thinner than the first insulating film (noting in paragraph [0109] that dry-plated or sputtered insulating films may have a substantially same thickness dimension at both local locations on top and side surfaces).
US'739 discloses a multi-layer ceramic component having side margin insulating portions (second insulating film) covering side surfaces of an active electrode stack and cover portions (first insulating film) covering principal surfaces, wherein the side margin portions have an average thickness of 2 µm to 10 µm (paragraphs [0038], [0063]), whereas each of the cover portions on the principal surfaces has a thickness of 20 µm (paragraph [0057]), thereby explicitly teaching a second insulating film covering the side surface that is thinner than the first insulating film extending over the principal surface. Furthermore, US'115 discloses a solid-state multi-layer ceramic battery (Col. 1, lines 10–25; Col. 2, lines 5–20) and explicitly teaches applying multi-layer ceramic capacitor (MLCC) construction concepts, margin/edge insulation layouts, and ceramic processing technologies directly to multi-layer solid-state ceramic batteries (Col. 1, lines 15–25; Col. 2, lines 5–20; Col. 3, lines 20–35; Col. 4, line 55 to Col. 5, line 15), as well as utilizing solid electrolytes having lithium ion conductivity in multi-layer ceramic battery structures (Col. 2, lines 10–20; Col. 3, lines 10–25).
It would have been obvious to a person skilled in the art before the effective filing date of the instant application to modify the insulating cover layer structure of US'471 by configuring the second insulating film covering the side surface to be thinner than the first insulating film extending over the principal surface, as taught by US'739 in view of the MLCC adaptation teachings of US'115, in order to minimize lateral dead space and reduce the overall package footprint, thereby maximizing volumetric energy density while maintaining sufficient dielectric strength and mechanical cushioning on the principal surface during vertical cell pressing and assembly.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
CN 105103359 B discloses a non-aqueous electrolyte secondary battery, wherein a diaphragm is arranged between the positive electrode active material layer and the negative electrode active material layer, and the density of the negative electrode active material layer is 1.4 to 1.6g/cm3.
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/JIMMY VO/
Primary Examiner
Art Unit 1723
/JIMMY VO/Primary Examiner, Art Unit 1723
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