DETAILED ACTION
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 12/8/23 and 3/12/26 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 4, 8, and 9 are rejected under 35 U.S.C. 103 as being unpatentable over Ikeda (US 2021/0167266) in view of Kubota (US 2023/0340694).
As to claim 1, Ikeda teaches a display device (figs. 1 and 4) comprising:
a substrate (10, [0024]);
a heat dissipation layer (160) on the substrate (10, [0030]);
a plurality of light-emitting elements (100) provided on the heat dissipation layer (660) on the main surface (10a) of the substrate (10, [0032]);
an insulating film (20/24/35) covering the heat dissipation layer (160, [0040]); and
cathode wiring (60) provided on the insulating film (20/24/35) in a peripheral region (GA) outside a display region (AA) of the substrate and electrically coupled to a cathode (90e) of the light-emitting elements (100, [0028]),
wherein the heat dissipation layer (160) is continuously provided from a region overlapping the light-emitting elements (100) to the peripheral region (GA, [0030], fig. 4), and
the insulating film (20/24/35) has a contact hole (H1) overlapping the cathode wiring (60) and the heat dissipation layer (160) in plan view from a direction perpendicular to the main surface (10a) of the substrate (100, Fig. 4, [0053]).
Ikeda does not teach that the heat dissipation layer is on the main surface of the substrate and that it includes aluminum nitride (AlN). However, determining the ideal location of the heat dissipation layer with respect to the substrate (i.e. on the main surface or on the bottom surface) would have been obvious so as to most effectively remove heat from whichever elements are being damaged the most. If that leads to the heat dissipation layer being on the top surface of the substrate rather than the bottom surface of the substrate (i.e. closer to the elements needing heat dissipation), then that is the result of ordinary skill in the art and not innovation.
While Ikeda does not teach the heat dissipation layer includes AlN, Kubota teaches using AlN as a heat dissipation material because it “has a high thermal conductivity and is superior in heat transfer in the downstream process” ([0038]). Therefore, it would have been obvious to one of ordinary skill in the art at the time the invention was filed to use AlN for the material of the heat dissipation layer for the reasons stated above, since it has been held that a choosing from a finite number of known options is within the technical grasp of a person having ordinary skill in the art and is not patentable over the prior art. See MPEP 2143(E).
As to claim 4, Ikeda further teaches a plurality of transistors (Tr1, Tr3, Tr5) provided on the heat dissipation layer (160) on the main surface of the substrate (100, fig. 4), wherein the heat dissipation layer (160) is continuously provided in a region overlapping the light-emitting elements (100) and the transistors (Tr1, Tr3, Tr5) in the display region (AA), and the insulating film (20/24/35) covers the transistors (Tr1, Tr3, Tr5, [0044]).
As to claim 8, Ikeda further teaches thermal conductivity of the heat dissipation layer is higher than thermal conductivity of the substrate ([0038], AlN has a higher thermal conductivity than glass).
As to claim 9, Ikeda further teaches the substrate is a glass substrate ([0038]).
Allowable Subject Matter
Claims 2, 3, and 5-7 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is a statement of reasons for the indication of allowable subject matter: The prior art taken either singularly or in combination fails to anticipate or fairly suggest the limitations of the claims listed above in such a manner that a rejection under 35 U.S.C. 102 or 103 would be proper.
The prior art fails to teach a combination of all of the features in the claims. As to claim 2, Ikeda does not teach the light-emitting elements are provided in direct contact with the heat dissipation layer and each comprise a high resistance layer, an n-type cladding layer, an active layer, and a p-type cladding layer stacked in order on the heat dissipation layer. While it is obvious to move the heat dissipation layer to be closest to the element needing heat dissipation, given the structure of the instant device, there would not be an obvious way to have the heat dissipation layer directly contacting the light-emitting element (claim 2 limitation) and simultaneously have the insulating layer covering the heat dissipation layer and the cathode wiring on the insulating layer (claim 1 limitations).
As to claim 5, Ikeda teaches a gate insulating film (29) provided between a semiconductor layer (27) and a gate electrode (31) of the transistors (fig. 4, [0041]); and an element insulating film (80) provided covering a periphery of an upper surface and a side surface of the light-emitting elements (100, [0080]).
Ikeda fails to teach the gate insulating film and the element insulating film are integrally and continuously formed using common material. They are on different levels and would not be formed integrally and continuously.
As to claim 6, Ikeda fails to teach the light-emitting elements each comprise a first light-emitting element and a second light-emitting element adjacent to the first light-emitting element, the first light-emitting element and the second light- emitting element are formed on a common high resistance layer provided in direct contact with the heat dissipation layer, and the height between an anode electrode of the first light-emitting element and the high resistance layer is different from the height between an anode electrode of the second light-emitting element and the high resistance layer in the direction perpendicular to the main surface of the substrate.
Claims 3 and 7 are allowable at least because they depend from allowable claims.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Conclusion
Any response to this Office Action should be faxed to (571) 273-8300 or mailed to:
Commissioner for Patents
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Alexandria, VA 22313-1450
Hand-Delivered responses should be brought to:
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Any inquiry concerning this communication or earlier communications from the examiner should be directed to KAREN M KUSUMAKAR whose telephone number is (571)270-3520. The examiner can normally be reached on Monday – Friday from 7:30a – 4:30p EST.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Fernando Toledo can be reached on 571-272-1867. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/KAREN KUSUMAKAR/
Primary Examiner, Art Unit 2897
3/31/26
Prosecution Insights