DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-3, 5-6, 9-16 and 18 are rejected under 35 U.S.C. 103 as being unpatentable over JP-2008159909 (Katsuhisa) in view of US 5,721,751 (Itaya) and US 4,329,660 (Yano).
For claim 1, Katsuhisa teaches an optoelectrical assembly (fig. 1), comprising:
an optoelectrical semiconductor device configured to output an output optical power (fig. 1, 5; output power monitored by 16; [0020]);
a voltage conversion circuit (fig. 1, 22) coupled to the optoelectrical semiconductor device (5) and configured to:
provide a bias voltage to the optoelectrical semiconductor device (fig. 1, Vld); and adjust, by changing the bias voltage, the output optical power ([0024]);
an optoelectrical detection circuit (fig. 1, 16; [0020]) coupled to the optoelectrical semiconductor device (5) and configured to:
detect the output optical power ([0020]); and
output a detection signal (fig. 1, Impd; [0020]); and
a controller (fig. 1, 20) coupled to the voltage conversion circuit (22) and the optoelectrical detection circuit (16) and configured to:
receive the detection signal (fig. 1, Impd);
determine a control signal based on the detection signal and to adjust the bias voltage (fig. 1, control signal Impd; [0023]-[0024]); and
output the control signal to the voltage conversion circuit (fig. 1, Vb to 22).
Katsuhisa does not teach a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation.
However, Itaya teaches a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (fig. 14, threshold power to max power plotted) (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation (fig. 14, approximately 2Ω above laser threshold). An approximately 2Ω Rdiff has the advantage of providing a diode characteristic as taught by Yano (c. 7, l. 33-38).
It would have been obvious to combine the differential resistance characteristics taught by Itaya with the device of Katsuhisa in order to provide an advantageous diode characteristic.
For claim 2, Itaya further teaches a differential resistance of the optoelectrical semiconductor device within a sub-range of the target optical power (Rdiffsub) (fig. 14; any subrange between the threshold current and a higher current has an Rdiffsub of approximately 2Ω) and an average differential (Rdiffavg) (fig. 14; Riffavg is approximately 2Ω) satisfy a formula, and wherein the formula is:
max(0.02*Rdiffavg, 0.1 Ω) ≤ Rdiffsub ≤ min(50*Rdiffavg, 50 Ω), wherein max(0.02*Rdiffavg, 0.1 Ω) indicates a larger value of 0.02*Rdiffavg and 0.1 Ω, and, wherein min(50*Rdiffavg, 50 Ω) indicates a smaller value of 50*Rdiffavg and 50 Ω, and wherein Rdiffavg indicates a ratio of a bias voltage variation corresponding to a lower optical power limit and an upper optical power limit of the optoelectrical semiconductor device within the range to a corresponding current variation (fig. 14, substantially constant differential resistance of approximately 2 Ω after threshold current satisfies the inequality).
For claim 3, Katsuhisa teaches the optoelectrical semiconductor device is a light source (fig. 1, laser 5). The combination does not explicitly teach wherein a resistance value of the light source is less than or equal to 60 Ω within the range. However, the examiner takes official notice that resistance was well-known in the art before the filing date of the claimed invention as a results effective variable influencing conversion efficiency. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention optimize the resistance value of the light source below 60 Ω in order to optimize conversion efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
For claim 5, Katsuhisa teaches the controller is further configured to: enable or disable the voltage conversion circuit (fig. 1, controller 20 provides Vb to the voltage conversion circuit and thus enables the voltage conversion circuit 22).
Further, while the limitation is written in the alternative and thus does not require both disabling and enabling, the examiner takes official notice that disabling a circuit was well-known in the art before the filing date of the claimed invention in order to terminate operation if a device is operating outside of desired parameters. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the well-known disabling with the controller of the previous combination in order to terminate operation if the semiconductor device is operating outside of desired parameters.
For claim 6, Katsuhisa teaches the controller is further configured to: obtain load link information, wherein the load link information comprises a value of the bias voltage ([0027]; starts operation by setting drive voltage to a low voltage such as 1.0V); and further determine the control signal based on the load link information ([0022]; subsequently feedback is performed to reach set Ib).
For claim 9, the combination does not teach Katsuhisa teaches the voltage conversion circuit is further configured to input a power supply voltage ranging from 1.8 volts (V) to 18 V. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine the optimal and workable input power supply voltage for the voltage conversion circuit in order to suitably drive the optoelectrical semiconductor device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 10, Katsuhisa teaches a filter (fig. 1, 38) so that the bias voltage is configured to minimize a voltage ripple ([0067]). Katsuhisa does not specify that the ripple is less than or equal to 50 millivolts (mV). However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine the optimal and workable ripple value in order to minimize its effects on the feedback loop, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
For claim 11, Katsuhisa teaches the voltage conversion circuit comprises a first voltage conversion circuit (fig. 1, 22), and wherein the optoelectrical semiconductor device comprises:
a first optoelectrical semiconductor device configured to output a first output optical power (fig. 1, 5; output power monitored by 16; [0020]);
wherein the optoelectrical detection circuit comprises:
a first optoelectrical detection circuit (fig. 1, 16; [0020]), configured to:
detect the first output optical power ([0020]); and
output a first detection signal (fig. 1, Impd; [0020]) to the controller (fig. 1, 20);
and, wherein the controller is further configured to:
determine a first control signal based on the first detection signal, wherein the first control signal adjusts a first bias voltage provided to the first optoelectrical semiconductor device (fig. 1, control signal Impd; [0023]-[0024]);
send the first control signal to the first voltage conversion circuit (fig. 1, Vb to 22).
The combination does not teach the claimed second voltage conversion circuit,
the second optoelectrical semiconductor device configured to output a second output optical power, and
a second optoelectrical detection circuit configured to: detect the second output optical power; and
output a second detection signal to the controller
and
the controller configured to determine a second control signal based on the second detection signal, wherein the second control signal adjusts a second bias voltage provided to the second optoelectrical semiconductor device; and
send the second control signal to the second voltage conversion circuit.
However, the second voltage conversion circuit, the second optoelectrical semiconductor device, and the second optoelectrical detection circuit coupled to the controller are a duplication of parts. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to duplicate the first voltage conversion circuit, the first optoelectrical semiconductor device, and the first optoelectrical detection circuit coupled to the controller in order to provide a second transmitter, since it has been held that mere duplication of the essential working parts of a device involves only routine skill in the art. St. Regis Paper Co. v. Bemis Co., 193 USPQ 8.
For claim 12, the combination does not teach a digital-to-analog converter; coupled to the controller, wherein the controller is configured to send the first control signal and the second control signal to the digital-to-analog converter in a serial manner, and wherein the digital-to-analog converter is configured to:
perform digital-to-analog conversion on the first control signal to obtain a first signal;
output the first signal to the first voltage conversion circuit; and perform digital-to-analog conversion on the second control signal to obtain a second signal; and the second signal to the second voltage conversion circuit.
However, the examiner takes official notice that digital controllers were well-known in the art before the effective filing date of the claimed invention, and that both digital to analog and analog to digital convertors serially coupled to digital and analog components were well-known in the art before the effective filing date of the claimed invention in order to transfer information between analog and digital forms required by analog components and digital controllers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a well-known digital controller as a simple substitution for the controller of the previous combination as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative controller. See MPEP 2143 I.B.
With the simple substitution of a digital controller, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a well-known digital to analog converter coupled to the controller to serially convert the digital information of the digital controller to analog required by voltage conversion circuit.
For claim 13, the combination does not teach a bit width of the digital-to-analog converter is greater than or equal to 6 bits. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to use a bit width of the digital-to-analog converter of greater than or equal to 6 bits in order to provide sufficient accuracy in the conversion, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
For claim 14, the art is applied as in the rejection of claim 11 above. The control signal of claim 14 is interpreted to include the first and second control signal discussed in the rejection of claim 11 above. The voltage conversion circuit of claim 14 is interpreted to include the first and second voltage conversion circuit discussed in the rejection of claim 11 above.
For claim 15, the combination does not teach an analog-to-digital converter coupled to the controller and configured to:
perform analog-to-digital conversion on the first detection signal to obtain a digitalized first detection signal:
perform analog-to-digital conversion on the second detection signal to obtain a digitalized second detection signal; and
output the digitalized first detection signal and the digitalized second detection signal to the controller in a serial manner.
However, the examiner takes official notice that digital controllers were well-known in the art before the effective filing date of the claimed invention, and that both digital to analog and analog to digital convertors serially coupled to digital and analog components were well-known in the art before the effective filing date of the claimed invention in order to transfer information between analog and digital forms required by analog components and digital controllers.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a well-known digital controller as a simple substitution for the controller of the previous combination as the substituted components and their functions were known in the art and the substitution would have yielded predictable results. In the present case, the substituted component provides an alternative controller. See MPEP 2143 I.B.
With the simple substitution of a digital controller, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use a well-known analog to digital converter coupled to the controller to serially convert the analog information of first and second detection signal to a digital form required by the digital controller.
For claim 16, Katsuhisa teaches a feedback network, and the feedback network is coupled to the controller and configured to increase or decrease a voltage range of the control signal (fig. 1, 16 is coupled to controller 20 to increase or decrease voltage range of Vb).
For claim 18, Katsuhisa teaches a light source pool comprising at least one optoelectrical assembly (fig. 1), comprising:
an optoelectrical semiconductor device configured to output an output optical power (fig. 1, 5; output power monitored by 16; [0020]),
a voltage conversion circuit (fig. 1, 22) coupled to the optoelectrical semiconductor device (5) and configured to:
provide a bias voltage to the optoelectrical semiconductor device (fig. 1, Vld); and adjust, by changing the bias voltage, the output optical power ([0024]);
an optoelectrical detection circuit (fig. 1, 16; [0020]) coupled to the optoelectrical semiconductor device (5) and configured to:
detect the output optical power ([0020]); and
output a detection signal (fig. 1, Impd; [0020]); and
a controller (fig. 1, 20) coupled to the voltage conversion circuit (22) and the optoelectrical detection circuit (16) and configured to:
receive the detection signal (fig. 1, Impd);
determine a control signal based on the detection signal and to adjust the bias voltage (fig. 1, control signal Impd; [0023]-[0024]); and
output the control signal to the voltage conversion circuit (fig. 1, Vb to 22).
Katsuhisa does not specify a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation.
However, Itaya teaches a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation (fig. 14, approximately 2Ω above laser threshold). An approximately 2Ω Rdiff has the advantage of providing a diode characteristic as taught by Yano (c. 7, l. 33-38).
It would have been obvious to combine the differential resistance characteristics taught by Itaya with the device of Katsuhisa in order to provide an advantageous diode characteristic.
Claims 4 are rejected under 35 U.S.C. 103 as being unpatentable over JP-2008159909 (Katsuhisa) in view of US 5,721,751 (Itaya) and US 4,329,660 (Yano), and further in view of US 2010/0321768 (Sone).
For claim 4, the previous combination does not teach the optoelectrical semiconductor device is an optical amplifier, and wherein a resistance value of the optical amplifier is less than or equal to 60 Ω within the range.
However, Sone teaches using an optoelectrical semiconductor device with a controlled output (fig. 1) where the optoelectrical semiconductor device is an optical amplifier (fig. 1, 1) in order to amplify input light (fig. 1). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use an optical amplifier as the optoelectrical semiconductor device in the previous combination in order to amplify input light.
The combination does not explicitly teach wherein a resistance value of the light source is less than or equal to 60 Ω within the range. However, the examiner takes official notice that resistance was well-known in the art before the filing date of the claimed invention as a results effective variable influencing conversion efficiency. It would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention optimize the resistance value of the light source below 60 Ω in order to optimize conversion efficiency, since it has been held that discovering an optimum value of a result effective variable involves only routine skill in the art. In re Boesch, 617 F.2d 272, 205 USPQ 215 (CCPA 1980).
Claims 7-8 are rejected under 35 U.S.C. 103 as being unpatentable over JP-2008159909 (Katsuhisa) in view of US 5,721,751 (Itaya) and US 4,329,660 (Yano), and further in view of US 2019/0181954 (Kawase).
For claim 7, the previous combination does not teach a temperature control circuit coupled to the optoelectrical semiconductor device and configured to perform temperature control on the optoelectrical semiconductor device; and
a temperature control drive circuit coupled to the temperature control circuit and configured to supply power to the temperature control circuit.
However, Kawase teaches a temperature control circuit (fig. 3, 48 and 49) coupled to the optoelectrical semiconductor device (fig. 3, 44) and configured to perform temperature control on the optoelectrical semiconductor device (fig. 3); and
a temperature control drive circuit coupled to the temperature control circuit and configured to supply power to the temperature control circuit (fig. 3, 47).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the temperature control of Kawase with the previous combination in order to control the temperature of the semiconductor device of the previous combination which had the well-known benefit, before the effective filing date of the claimed invention, of controlling the wavelength of the optoelectrical semiconductor device.
For claim 8, the combination does not teach the temperature control drive circuit is further configured to input a power supply voltage ranging from 2 volts (V) to 18 V. However, it would have been obvious to one having ordinary skill in the art before the effective filing date of the claimed invention to determine the optimal input power supply voltage for the temperature control drive circuit in order to control the temperature of the optoelectrical semiconductor device, since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or workable ranges involves only routine skill in the art. In re Aller, 105 USPQ 233.
Claims 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over JP-2008159909 (Katsuhisa) in view of US 5,721,751 (Itaya) and US 4,329,660 (Yano), and further in view of US 2004/0028099 (Hongo).
For claim 19, Katsuhisa teaches an optoelectrical switching device comprising at least one optoelectrical assembly (fig. 1), comprising:
at least one optoelectrical assembly configured to output light (fig. 1) and comprising:
an optoelectrical semiconductor device configured to output an output optical power (fig. 1, 5; output power monitored by 16; [0020]),
a voltage conversion circuit (fig. 1, 22) coupled to the optoelectrical semiconductor device (5) and configured to:
provide a bias voltage to the optoelectrical semiconductor device (fig. 1, Vld); and adjust, by changing the bias voltage, the output optical power ([0024]);
an optoelectrical detection circuit (fig. 1, 16; [0020]) coupled to the optoelectrical semiconductor device (5) and configured to:
detect the output optical power ([0020]); and
output a detection signal (fig. 1, Impd; [0020]); and
a first controller (fig. 1, 20) coupled to the voltage conversion circuit (22) and the optoelectrical detection circuit (16) and configured to:
receive the detection signal (fig. 1, Impd);
determine a control signal based on the detection signal and to adjust the bias voltage (fig. 1, control signal Impd; [0023]-[0024]); and
output the control signal to the voltage conversion circuit (fig. 1, Vb to 22).
Katsuhisa does not specify a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation.
However, Itaya teaches a differential resistance value of the optoelectrical semiconductor device within a range of a target optical power (Rdiff) satisfies 0.1 ohms (Ω) ≤ Rdiff ≤ 50 Ω, and wherein Rdiff is a ratio of a voltage variation to a current variation corresponding to the voltage variation (fig. 14, approximately 2Ω above laser threshold). An approximately 2Ω Rdiff has the advantage of providing a diode characteristic as taught by Yano (c. 7, l. 33-38).
It would have been obvious to combine the differential resistance characteristics taught by Itaya with the device of Katsuhisa in order to provide an advantageous diode characteristic.
The previous combination does not teach an optical modulator and a switching chip, coupled to the optical modulator and configured to control the optical modulator to modulate light. However, Hongo teaches an optoelectrical switching device (fig. 1 and 3) which includes an optical modulator (fig. 1 and 3, EA modulator 3) and a switching circuit (fig. 1 and 3, 15-19), coupled to the optical modulator and configured to control the optical modulator to modulate light (fig. 3) with the advantage of obtaining optical output with a small amount of chirp ([0006]).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use the modulator and switching circuit of Hongo with the laser of the previous combination in order to obtain optical output with a small amount of chirp.
While the combination does not explicitly teach the switching circuit is a chip, the examiner takes official notice that forming circuits on chips was well-known in the art before the filing date of the claimed invention. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to form the switching circuit of the previous combination on a chip as was well-known in order to provide a small compact switching circuit.
For claim 20, Katsuhisa teaches a second controller configured to: output a signal to the first controller to adjust the output optical power (fig. 1, second controller 18 outputs a signal, Vt, to first controller 18; [0021]-[0022]).
Allowable Subject Matter
Claim 17 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. JP-2008054286 teaches a plurality of lasers with feedback as well as ADC and DAC converters used in automatic power control feedback.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Michael W Carter whose telephone number is (571)270-1872. The examiner can normally be reached M-F, 9:00-5:30.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MinSun Harvey can be reached at 571-272-1835. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Michael Carter/Primary Examiner, Art Unit 2828
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