DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Wu (US9378315B1), in view of NPL “improving scalability of symbolic execution for software with complex environment interfaces” , here on Bucur.
With respect to claim 1, Wu teaches a semiconductor simulation method in which parameter values are received and used to execute sweep simulations using device model parameters under multiple process corner conditions. Wu explains that sweep simulation is performed where “corner number [is] an independent variable” (col.2, lines 29-53), Wu further discloses defining a value selection function, forming a tabular function group, adding the function into a simulation program, and running the simulation to produce results, as described throughout col.5–6. Wu therefore teaches receiving input data comprising parameter values, setting a simulation using parameters, generating tables associated with parameters, and executing simulation jobs that output result data;
Bucur teaches symbolic execution systems that organize computation into branching execution trees where execution states fork based on conditions. Bucur explains that “execution state forks into two states… turning execution into a tree” (Ch.1). Bucur further teaches prioritizing execution paths and grouping equivalent states to reduce redundant computation, as discussed in the description of symbolic execution trees and path prioritization strategies in Chapter 1 and later CUPA prioritization discussions. Bucur also discloses iterative execution control and exploration strategies guided by heuristics;
Wu teaches a simulation method of a semiconductor process including receiving parameter values and executing simulations using a structured parameter table (col.5–6). Wu discloses defining a value selection function and forming a two-dimensional tabular function group that controls simulation execution. Bucur teaches generating a tree structure and organizing jobs based on branching conditions. It would have been obvious to a person of ordinary skill in the art to modify Wu’s simulation workflow to include Bucur’s tree-based execution ordering in order to improve efficiency of exploring multiple parameter combinations, since both references address optimization of large combinational exploration problems.
With respect to claim 2, Wu describes selecting different parameter values associated with process corners and comparing values corresponding to device parameters across simulations (col.3–4). Bucur teaches branching execution paths based on comparisons of symbolic values (Fig.1.2). Combining Wu’s parameter selection with Bucur’s comparison-based branching renders obvious the ordering of parameters based on value comparison.
With respect to claim 3, Bucur teaches prioritization heuristics that group paths into equivalence classes and prioritize exploration of paths sharing similar characteristics (Chapter 4 discussion of CUPA). Assigning higher priority to parameters with repeated values would have been an obvious variation of Bucur’s grouping strategy because it achieves the same goal of reducing redundant computation.
With respect to claim 4, Bucur explicitly discloses a branching execution tree in which paths diverge when conditions differ, thereby suggesting generating a job tree where branches correspond to differing parameter values. Wu provides the semiconductor simulation environment in which such branching structures would be applied.
With respect to claim 5, Wu teaches executing the simulation and outputting result data values, such as waveform charts, as described in the Abstract and in the flowchart associated with FIG.1.
With respect to claim 6, Bucur teaches evaluating execution conditions using constraint solving and determining whether further exploration is required (Ch.1 discussion of path conditions and solver decisions). Applying such evaluation to determine whether a simulation should end would have been obvious.
With respect to claim 7, Bucur teaches iterative execution guided by heuristics and prioritization strategies, thereby suggesting repeating simulation improvement when results exceed a threshold.
With respect to claim 8, Wu teaches generating a table structure associated with parameter values, specifically describing formation of a two-dimensional tabular value selection function group (col.5–6).
With respect to claim 9, Bucur describes distributed symbolic execution and worker-level execution management, implying queue-based execution structures and task separation, thereby suggesting generating and modifying execution queues.
Claims 10–17 recite substantially similar limitations using alternate terminology such as operation nodes and reordered parameters. Wu continues to teach parameter table creation and execution of simulations, while Bucur teaches node merging, execution path prioritization, and grouping equivalent states. The combination of Wu and Bucur renders these limitations obvious because reorganizing parameter structures into prioritized execution nodes is a predictable implementation choice for improving efficiency.
With respect to claim 18, Bucur’s symbolic execution tree directly suggests ordering parameters and generating a job tree based on branching conditions, while Wu provides the semiconductor simulation context. Claim 19’s branching of a job tree when parameter values differ corresponds to Bucur’s branching execution paths described in Chapter 1 and illustrated in the symbolic execution tree diagram.
Claim 20’s repeated execution based on comparison of result values corresponds to Bucur’s iterative exploration using path conditions and solver feedback to determine further execution.
A person of ordinary skill in the art would have been motivated to combine Wu with Bucur because Wu seeks to improve efficiency of semiconductor process corner simulations, while Bucur provides known techniques for organizing computational exploration using tree structures and prioritization heuristics. Applying Bucur’s execution-tree organization to Wu’s simulation workflow would have yielded predictable improvements in computational efficiency, which is a recognized design objective. Therefore, claims 1–20 would have been obvious over Wu in view of Bucur.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD AHMED whose telephone number is (571)270-1315. The examiner can normally be reached M-F 9:00-8:30 PM PST with IFP.
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MASUD . AHMED
Primary Examiner
Art Unit 3657A
/MASUD AHMED/Primary Examiner, Art Unit 3657