DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
The following title is suggested: Light Emitting Display Device that Evenly Distributes Current Density and Avoids Current Concentration on a Specific Point.
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5, and 8-10 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Kim et al’938 (US 2021/0134938).
Regarding Claim 1, Kim et al’938 discloses a light emitting display (transparent display panel 300 [0118] shown in Fig 6) comprising:
a substrate (gate insulating layer 213 [0097] Fig 16) including a display area (display region DA [0051] Fig 6) and a non-display area (non-display region NDA [0051] Fig 6) surrounding the display area (DA);
a low-potential line (data lines 313 [0164] Fig 13, VSS voltage line 321 [0129] Fig 13, VSS voltage line 322 Fig 13, [0128] Fig 13,VSS voltage line 323 [0174] Fig 13, and second reference voltage connection line 345 [0210] Fig 16) including a first low-potential line (321) disposed at an upper side of the substrate (213), and a second low-potential line (345) disposed at a lower side of the substrate (213);
a pad portion (VSS voltage line connection pad 320 [0134] Fig 16) disposed outside the second low-potential line (345) on the substrate (213);
a first region (shown in annotated Fig 13 viewed from 180 degrees) defined at right side of the substrate (213), and a second region (shown in annotated Fig 13 viewed from 180 degrees) defined at left side of the substrate (213);
a plurality of auxiliary lines (auxiliary line 327 [0228] (shown as a plurality of regions 327) Fig 13) connected between the first low-potential line (321) and the second low-potential line (345) in the second region (shown in annotated Fig 13 viewed from 180 degrees); and
a common electrode (first connection electrode 351 [0156] and fourth connection electrode 354 [0289] Fig 16) extended from the display area (DA Fig 6) to be in surface contact with the low- potential line (321 Fig 16).
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Regarding Claim 2, Kim et al’938 discloses the limitations of claim 1 as explained above. Kim et al’938 further discloses
wherein the plurality of auxiliary lines (327 Fig 13) is not disposed in the first region (shown above in annotated Fig 13 viewed from 180 degrees).
Regarding Claim 3, Kim et al’938 discloses the limitations of claim 1 as explained above. Kim et al’938 further discloses
a first low-potential terminal (reference voltage line 341 [0134]) disposed to be corresponding (electrically connected) to the first region (shown in annotated Fig 6) at the pad portion (320), and connected to the second low-potential line (345); and
a second low-potential terminal (left portion of data line connection pad 311 [0134] shown in annotated Fig 6) and a third low-potential terminal (right portion of data line connection pad 311 [0134] shown in annotated Fig 6) disposed to be corresponding to the second region (shown in annotated Fig 6) at the pad portion (320), and connected (electrically connected) to the second low-potential line (345).
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Regarding Claim 4, Kim et al’938 discloses the limitations of claim 3 as explained above. Kim et al’938 further discloses
wherein the second low-potential terminal (left portion of 311 shown above in annotated Fig 6) is disposed at a first side of the second region (shown above in annotated Fig 6), and wherein the third low-potential terminal (right portion of 311 shown above in annotated Fig 6) is disposed at a second side of the second region opposing the first side of the second region (shown above in annotated Fig 6).
Regarding Claim 5, Kim et al’938 discloses the limitations of claim 3 as explained above. Kim et al’938 further discloses
wherein the first low-potential terminal (341) is disposed at a first side (shown in annotated Fig 6) of the first region (shown in annotated Fig 6), and
a gate signal terminal (auxiliary line 327 and gate electrode 214 may constitute the same layer [0228]) for supplying a gate signal is further disposed at a second side (shown in annotated Fig 6) of the first region (shown in annotated Fig 6) opposing the first side of the first region (shown in annotated Fig 6).
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Regarding Claim 8, Kim et al’938 discloses the limitations of claim 1 as explained above. Kim et al’938 further discloses
wherein the plurality of auxiliary lines (327) is disposed to be in contact (electrical contact) with the first low-potential line (321 Fig 16) and the second low-potential line (345) in the second region (shown above in annotated Fig 13 viewed from 180 degrees), and
an electron functional layer (bank 231 [0288]) disposed between the low-potential line (321 and 345) and the common electrode (351 and 354).
Regarding Claim 9, Kim et al’938 discloses the limitations of claim 8 as explained above. Kim et al’938 further discloses
further comprising a light emitting diode (shown in the light-emitting region EA of the sub-pixel [0084] Fig 4) disposed in the display area (DA), wherein the light emitting diode (shown in the light-emitting region EA of the sub-pixel Fig 4) includes:
an anode electrode (anode electrode 221 [0085]); and
an emission layer (organic light-emitting layer 223 [0085]) on the anode electrode (221);
wherein the electron functional layer (231) on the emission layer (223),
wherein the common electrode (351 and 354 Fig 16) on the electron functional layer (231),
wherein the electron functional layer (231) is disposed within the display area (DA) in the first region (shown above in annotated Fig 6), and
wherein the electron functional layer (231) is extended from the display area (DA Fig 6) to be disposed between the low-potential line (data lines 313 [0164] Fig 13, VSS voltage line 321 [0129] Fig 13, VSS voltage line 322 Fig 13, [0128] Fig 13,VSS voltage line 323 [0174] Fig 13, and second reference voltage connection line 345 [0210] Fig 16) and the common electrode (351 and 354 Fig 16) in the second region (shown above in annotated Fig 6).
Regarding Claim 10, Kim et al’938 discloses the limitations of claim 1 as explained above. Kim et al’938 further discloses
further comprising a third low-potential line (data line 313 Fig 13) disposed outside the first low-potential line (321 Fig 16) on the substrate (213 Fig 16), wherein the auxiliary line (327 Fig 13) is connected to the first low-potential line (321 Fig 16) in the first region (shown above in annotated Fig 13 viewed from 180 degrees), and
wherein the auxiliary line (327) is connected (electrically connected) to the third low-potential line (313 Fig 13) in the second region (shown above in annotated Fig 13 viewed from 180 degrees).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al’938 (US 2021/0134938) in view of Kim et al’061 (US 2018/0090061).
Regarding Claim 1, Kim et al’938 does not disclose
further comprising a plurality of dummy auxiliary lines connected to the first low-potential line except the second low-potential line in the second region.
Kim et al’061, in the related art of semiconductor devices that include display devices, discloses
a plurality of dummy auxiliary lines (dummy auxiliary connection line DAUX [0219] and dummy data line DDL [0198] Fig 9) connected to the first low-potential line (data lines Dj [0111] Fig 4).
It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify Kim et al’938 to include a plurality of dummy auxiliary lines connected to the first low-potential line as taught by Kim et al’061 in order to have a region that compensates for a difference in load value [0126]. Further, a person of ordinary skill in the art would have recognized that including a plurality of dummy auxiliary lines connected to the first low-potential line except the second low potential line in the second region would be advantageous in expanding the functional capability of the device while meeting the spatial design requirements of Kim et al’938.
The combination of Kim et al’938 and Kim et al’061 now discloses
a plurality of dummy auxiliary lines connected to the first low-potential line (DDL Fig 9 Kim et al’061/321 Kim et al’938) except the second low-potential line (345 Kim et al’938) in the second region (shown in annotated Fig 6 Kim et al’938 and Fig 13 viewed from 180 degrees Kim et al’938).
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Claim 7 is rejected under 35 U.S.C. 103 as being unpatentable over Kim et al’938 (US 2021/0134938) in view of Kim et al’061 (US 2018/0090061), and in further view of Lee et al (KR 20140087906 A).
Regarding Claim 7, the combination of Kim et al’938 and Kim et al’061 discloses the limitations of claim 6 as explained above. The combination of Kim et al’938 and Kim et al’061 does not directly disclose
wherein the auxiliary lines and the dummy auxiliary lines are arrayed with same intervals.
Lee et al, in the related art of semiconductor devices that include display devices, discloses
wherein the first auxiliary lines (first auxiliary connection portion 112 [page 3, lines 1-5] Fig 6) and the second auxiliary lines (second auxiliary connection portion 123 [page 3, lines 1-5] Fig 6) are arrayed with same intervals (shown in annotated Fig 6).
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It would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to modify the combination of Kim et al’938 and Kim et al’061 to include dummy auxiliary lines arrayed with the same intervals as the auxiliary lines as taught by Lee et al in order to help optimize the electrical current flow through the device by improving the electrical connections [page 3 lines 1-5] in the first region of Kim et al’938. Further, a person of ordinary skill in the art would have recognized that optimizing the electrical functioning capability of the device while minimizing the risk of unwanted damage from undesirable electrical effects would be advantageous in improving the reliability and function of the device (see MPEP 2143.I(D)).
Allowable Subject Matter
Claims 11-13 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
Claim 11:
Regarding Claim 11, Kim et al’938 (US 2021/0134938) discloses the limitations of claim 10 as explained above. Kim et al’938 further discloses
further comprising an insulating layer (passivation layer 218 [0103] Fig 16) covering the first low-potential line (321) and the third low-potential line (data line 313 Fig 13) in the non-display area (NDA),
wherein the insulating layer (218) includes:
a first contact hole (VSS voltage connection line contact hole 325h [0224] Fig 13) disposed in the first region (shown in annotated Fig 6); and
a second contact hole (auxiliary line contact hole 327h [0227]) disposed in the second region (shown in annotated Fig 6).
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The reason for the indication of allowability of Claim 11 is the inclusion of
a first contact hole disposed in the first region except the second region for exposing some of the third low-potential line; and
a second contact hole disposed in the second region except the first region for exposing some of the first low-potential line.
Specifically, the reference Kim et al does not disclose the first contact hole absent from the second region for the purpose of exposing some of the third low-potential line, and the second contact hole absent from the first region for the purpose of exposing some of the first low-potential line. Further, should another reference be found that discloses these limitations, it would not be obvious to a person of ordinary skill in the art to make this alteration to the reference Kim et al’938.
It is these features found in the claim, as they are claimed in the combination that has not been found, taught or suggested by the prior art of record, which makes this claim allowable over the prior art.
Claim 12 would be allowable because of its dependency on Claim 11.
Claim 13 would be allowable because of its dependency on Claim 11.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Related Cited Prior Art
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Kim (US 2008/0123013) which discloses a display device with pixel electrodes formed as a matrix configuration [0007], and Ha et al (US 2002/0085160) which discloses a display device with a display area and a non-display area [0018].
Conclusion
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/D.P.S./Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812