DETAILED ACTION
Claims 1-20 are pending in this application.
Claims 6 and 17 are objected to
Claims 1-5, 7-16 and 18-20 are rejected.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/6/2026 has been entered.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 7-16 and 18-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Hornung et al. (U.S. PGPub No. 2023/0393970) in view of Vick et al. (U.S. PGPub No. 2009/0089537) in view of Godtland et al. (U.S. PGPub No. 2002/0042868).
Claim 1
Hornung (2023/0393970) teaches:
A system comprising: a first node, the first node comprising: a core; and […] P. 0038, 0042 and FIG. 2 CXL device 204 includes accelerator logic 222
the core comprising: a core processing circuit; and P. 0042 accelerator logic 222 may be one or more processors
a memory management unit configured to map local virtual addresses to global virtual addresses, P. 0058 MMU may be logic within any of the processing units shown in FIGS. 1-3 (e.g. accelerator logic 222 of FIG. 2); P. 0048-49 a memory management unit (MMU) determines if the virtual address maps to an address in the global shared region by extracting the virtual device identification (VDID) field from the virtual address [extracting = mapping to local VA, see also P. 0060]
[…] map global virtual addresses to global physical addresses, and […] P. 0045 and FIG. 3 a global virtual region in the virtual address space 365 are mapped to physical addresses in the global physical address space 360
Hornung does not explicitly teach a global address translation circuit external to a processor in addition to a memory management unit within the processor.
Vick (2009/0089537) teaches:
a global address translation circuit, FIG. 3 node virtualization table (310), an address space table (312)
the global address translation circuit being configured to map global virtual addresses to global physical addresses, and P. 0036 and FIG. 2A addresses in remote node A virtualized address space 206 [global virtual addresses] are mapped into remote node A's physical address space 210 [global physical addresses], while addresses in remote node B virtualized address space 208 [global virtual addresses] are mapped into remote node B's physical address space 212 [global physical addresses]
the global virtual addresses comprising global virtual address ranges of a first size corresponding to a portion of a global virtual address space and […] a second portion of the global virtual address space. P. 0033 and FIG. 2B remote node virtualized address spaces 206 and 208 [global virtual address ranges] in FIG. 2A are part of the system address space [global virtual address space]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung with the global address translation circuit external to a processor in addition to a memory management unit within the processor taught by Vick
The motivation being allow a memory access request addressing a virtual memory location on one node to be directly executed in the physical memory of another node (see Vick P. 0016)
The systems of Hornung and Vick do not explicitly teach the global virtual address spaces being of different sizes.
Godtland (2002/0042868) teaches:
the global virtual addresses comprising global virtual address ranges of a first size corresponding to a portion of a global virtual address space and a second size corresponding to a second portion of the global virtual address space. P. 0046 if the base address of a virtual address indicates it is a global address, the boundary is set to a value that corresponds to the boundary for part of the global address space. More than one boundary may be defined, and the size of segments defined by the boundaries can vary.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung and Vick with the global virtual address spaces being of different sizes taught by Godtland.
The motivation being to partition the global address space.
The systems of Hornung, Vick and Godtland are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hornung and Vick with Godtland to obtain the invention as recited in claims 1-9.
Claim 2
Hornung (2023/0393970) teaches:
The system of claim 1, wherein the memory management unit comprises a translation lookaside buffer for mapping local virtual addresses to global virtual addresses. P. 0050 virtual-to-physical translation cache 510 (e.g., a TLB) is part of virtual to physical translation logic 500 (e.g. MMU functions, see P. 0048)
Claim 3
Hornung (2023/0393970) teaches:
The system of claim 1, wherein: the global address translation circuit is configured to map a first global virtual address range having the first size to a first global physical address range having the first size; the global address translation circuit is configured to map a second global virtual address range having the first size to a second global physical address range having the first size; P. 0044 and FIG. 3 A virtual shared global memory region is defined by grouping the same power-of-two memory region size on N devices (e.g., CXL devices 322-352), a physical shared global memory region is defined by grouping the same power-of-two memory region size on N devices
the second global virtual address range is contiguous with the first global virtual address range and the first size is based on the first portion of the global virtual address space; and the second global physical address range is not contiguous with the first global physical address range. FIG. 3 in global physical address space 360, segments 0-3 are non-contiguous while in virtual address space 365 segments 0-3 are contiguous
Claim 4
Hornung (2023/0393970) teaches:
The system of claim 3, further comprising a second node, wherein: FIG. 3 segment 1 corresponds to a different device 340
a first node address range comprises a range of global physical addresses allocated to the first node; a second node address range comprises a range of global physical addresses allocated to the second node; FIG. 3 each segment 0-3 maps to physical address space 360; P. 0055-56 scale egress global range table has an entry for each global unique region ID (GURNGID), the entry including a base address in the Device ID mapping table and the region segment size width W
a lowest global physical address of the second node address range exceeds a lowest global physical address of the first node address range by an inter-node address offset […] and a lowest global physical address of the second global physical address range exceeds a lowest global physical address of the first global physical address range by the inter-node address offset. P. 0056-57 the base address is used to obtain an index into a third table mapping physical device IDs; P. 0061 the system may determine a base address and size for the region corresponding to the GURNGID, then determine a physical segment (dest_phys_segment) and destination physical device ID (dest_did) [collectively analogous to the base address]; P. 0062 the physical address may be created from the dest_phys_segment, dest_did, and an offset within the virtual address. The size W [offset] is used to shift the dest_phys_segment and dest_did
Hornung does not explicitly teach the base addresses of different segments being separated by an offset which is equal to the size of the segment.
Vick (2009/0089537) teaches:
a lowest global physical address of the second node address range exceeds a lowest global physical address of the first node address range by an inter-node address offset equal to a size of the first node address range and equal to a size of the second node address range; and a lowest global physical address of the second global physical address range exceeds a lowest global physical address of the first global physical address range by the inter-node address offset. P. 0028-30 and FIG. 2A process virtual address space (202). The local node physical address space (216) is the range of physical addresses for the local node, global system address space (204) may be used to abstract which node has the physical memory with the requested page; P. 0081 the size of the physical memory is the size of the local node's physical memory with the size of all of the physical memory published by remote nodes; P. 0062 if the physical address is a global system address, then the virtual node identifier and the virtualized address is obtained from the global system address; P. 0069 the virtualized address is translated into a physical address on the remote node, by using a page export table
The rationale to combine Hornung with Vick for claim 1 equally applies for dependent claims 4-5.
Claim 5
Vick (2009/0089537) teaches:
The system of claim 4, wherein the inter-node address offset is greater than the first size. P. 0036 and FIG. 2A the virtualized address space (e.g., remote node A virtualized address space (206), remote node B virtualized address space (208)) for the remote node may have the same size or a smaller size than the physical address space (e.g. remote node A physical address space (210), remote node B physical address space (212)) for the remote node.
Claim 7
Hornung (2023/0393970) teaches:
The system of claim 5, wherein the inter-node address offset is a power of 2. P. 0046 both virtual address blocks and physical address blocks are composed of naturally aligned power-of-two sized memory
Claim 8
Hornung (2023/0393970) teaches:
The system of claim 5, wherein the first size is a power of 2. P. 0046 both virtual address blocks and physical address blocks are composed of naturally aligned power-of-two sized memory
Claim 9
Vick (2009/0089537) teaches:
The system of claim 4, wherein: the global address translation circuit is configured to map a third global virtual address range having the second size, different from the first size and based on the second portion of the global virtual address space different from the first portion, to a third global physical address range having the second size; the global address translation circuit is configured to map a fourth global virtual address range having the second size to a fourth global physical address range having the second size; P. 0036 and FIG. 2A the virtualized address space (e.g., remote node A virtualized address space (206), remote node B virtualized address space (208)) for the remote node may have the same size or a smaller size than the physical address space (e.g. remote node A physical address space (210), remote node B physical address space (212)) for the remote node.
and a lowest global physical address of the fourth global physical address range exceeds a lowest global physical address of the third global physical address range by the inter-node address offset. P. 0028-30 and FIG. 2A process virtual address space (202). The local node physical address space (216) is the range of physical addresses for the local node, global system address space (204) may be used to abstract which node has the physical memory with the requested page; P. 0081 the size of the physical memory is the size of the local node's physical memory with the size of all of the physical memory published by remote nodes; P. 0062 if the physical address is a global system address, then the virtual node identifier and the virtualized address is obtained from the global system address; P. 0069 the virtualized address is translated into a physical address on the remote node, by using a page export table
The rationale to combine Hornung with Vick for claim 1 equally applies for dependent claims 9.
Claim 10
Hornung (2023/0393970) teaches:
The system of claim 2, wherein the global address translation circuit is further configured to map a first global virtual address to a global physical address or to a local physical address, based on a value of a global bit associated with the first global virtual address. P. 0058 MMU may be logic within any of the processing units shown in FIGS. 1-3 (e.g. accelerator logic 222 of FIG. 2); P. 0048-49 a memory management unit (MMU) determines if the virtual address maps to an address in the global shared region by extracting the virtual device identification (VDID) field from the virtual address
Claim 11
Hornung (2023/0393970) teaches:
The system of claim 10, wherein the global bit associated with the first global virtual address is a bit of the first global virtual address. P. 0044 The log base two of N bits above the region's address offset bits is used to identify a virtual device ID of the device
Claim 12
Hornung (2023/0393970) teaches:
A method, comprising: mapping, by a memory management unit of a core of a first node, a local virtual address to a global virtual address, and P. 0038, 0042 and FIG. 2 CXL device 204 includes accelerator logic 222; P. 0042 accelerator logic 222 may be one or more processors; P. 0058 MMU may be logic within any of the processing units shown in FIGS. 1-3 (e.g. accelerator logic 222 of FIG. 2); P. 0048-49 a memory management unit (MMU) determines if the virtual address maps to an address in the global shared region by extracting the virtual device identification (VDID) field from the virtual address [extracting = mapping to local VA, see also P. 0060]
P. 0045 and FIG. 3 a global virtual region in the virtual address space 365 are mapped to physical addresses in the global physical address space 360
Hornung does not explicitly teach a global address translation circuit external to a processor in addition to a memory management unit within the processor.
Vick (2009/0089537) teaches:
mapping […] the global virtual address to a global physical address. FIG. 3 node virtualization table (310), an address space table (312)
mapping, by a global address translation circuit of the first node, the global virtual address to a global physical address, and P. 0036 and FIG. 2A addresses in remote node A virtualized address space 206 [global virtual addresses] are mapped into remote node A's physical address space 210 [global physical addresses], while addresses in remote node B virtualized address space 208 [global virtual addresses] are mapped into remote node B's physical address space 212 [global physical addresses]
the global virtual address is from a global virtual address range having a first size corresponding to a first portion of a global virtual address space and […] a second portion of the global virtual address space. P. 0033 and FIG. 2B remote node virtualized address spaces 206 and 208 [global virtual address ranges] in FIG. 2A are part of the system address space [global virtual address space]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung with the global address translation circuit external to a processor in addition to a memory management unit within the processor taught by Vick
The motivation being allow a memory access request addressing a virtual memory location on one node to be directly executed in the physical memory of another node (see Vick P. 0016)
The systems of Hornung and Vick do not explicitly teach the global virtual address spaces being of different sizes.
Godtland (2002/0042868) teaches:
the global virtual address is from a global virtual address range having a first size corresponding to a first portion of a global virtual address space and a second size corresponding to a second portion of the global virtual address space. P. 0046 if the base address of a virtual address indicates it is a global address, the boundary is set to a value that corresponds to the boundary for part of the global address space. More than one boundary may be defined, and the size of segments defined by the boundaries can vary.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung and Vick with the global virtual address spaces being of different sizes taught by Godtland.
The motivation being to partition the global address space.
The systems of Hornung, Vick and Godtland are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hornung and Vick with Godtland to obtain the invention as recited in claims 12-19.
Claim 13
Hornung (2023/0393970) teaches:
The method of claim 12, wherein the memory management unit comprises a translation lookaside buffer for mapping local virtual addresses to global virtual addresses. P. 0050 virtual-to-physical translation cache 510 (e.g., a TLB) is part of virtual to physical translation logic 500 (e.g. MMU functions, see P. 0048)
Claim 14
Hornung (2023/0393970) teaches:
The method of claim 12, further comprising: mapping, by the global address translation circuit, a first global virtual address range having the first size to a first global physical address range having the first size; and mapping, by the global address translation circuit, a second global virtual address range having the first size to a second global physical address range having the first size, P. 0044 and FIG. 3 A virtual shared global memory region is defined by grouping the same power-of-two memory region size on N devices (e.g., CXL devices 322-352), a physical shared global memory region is defined by grouping the same power-of-two memory region size on N devices
wherein: the second global virtual address range is contiguous with the first global virtual address range and the first size is based on the first portion of the global virtual address space; and the second global physical address range is not contiguous with the first global physical address range. FIG. 3 in global physical address space 360, segments 0-3 are non-contiguous while in virtual address space 365 segments 0-3 are contiguous
Claim 15
Hornung (2023/0393970) teaches:
The method of claim 14, further comprising a second node, wherein: FIG. 3 segment 1 corresponds to a different device 340
a first node address range comprises a range of global physical addresses allocated to the first node; a second node address range comprises a range of global physical addresses allocated to the second node; FIG. 3 each segment 0-3 maps to physical address space 360; P. 0055-56 scale egress global range table has an entry for each global unique region ID (GURNGID), the entry including a base address in the Device ID mapping table and the region segment size width W
a lowest global physical address of the second node address range exceeds a lowest global physical address of the first node address range by an inter-node address offset […] and a lowest global physical address of the second global physical address range exceeds a lowest global physical address of the first global physical address range by the inter-node address offset. P. 0056-57 the base address is used to obtain an index into a third table mapping physical device IDs; P. 0061 the system may determine a base address and size for the region corresponding to the GURNGID, then determine a physical segment (dest_phys_segment) and destination physical device ID (dest_did) [collectively analogous to the base address]; P. 0062 the physical address may be created from the dest_phys_segment, dest_did, and an offset within the virtual address. The size W [offset] is used to shift the dest_phys_segment and dest_did
Hornung does not explicitly teach the base addresses of different segments being separated by an offset which is equal to the size of the segment.
Vick (2009/0089537) teaches:
a lowest global physical address of the second node address range exceeds a lowest global physical address of the first node address range by an inter-node address offset equal to a size of the first node address range and equal to a size of the second node address range; and a lowest global physical address of the second global physical address range exceeds a lowest global physical address of the first global physical address range by the inter-node address offset. P. 0028-30 and FIG. 2A process virtual address space (202). The local node physical address space (216) is the range of physical addresses for the local node, global system address space (204) may be used to abstract which node has the physical memory with the requested page; P. 0081 the size of the physical memory is the size of the local node's physical memory with the size of all of the physical memory published by remote nodes; P. 0062 if the physical address is a global system address, then the virtual node identifier and the virtualized address is obtained from the global system address; P. 0069 the virtualized address is translated into a physical address on the remote node, by using a page export table
The rationale to combine Hornung with Vick for claim 12 equally applies for dependent claims 15-19.
Claim 16
Vick (2009/0089537) teaches:
The method of claim 15, wherein the inter-node address offset is greater than the first size. P. 0036 and FIG. 2A the virtualized address space (e.g., remote node A virtualized address space (206), remote node B virtualized address space (208)) for the remote node may have the same size or a smaller size than the physical address space (e.g. remote node A physical address space (210), remote node B physical address space (212)) for the remote node.
Claim 18
Hornung (2023/0393970) teaches:
The method of claim 16, wherein the inter-node address offset is a power of 2. P. 0046 both virtual address blocks and physical address blocks are composed of naturally aligned power-of-two sized memory
Claim 19
Hornung (2023/0393970) teaches:
The method of claim 16, wherein the first size is a power of 2. P. 0046 both virtual address blocks and physical address blocks are composed of naturally aligned power-of-two sized memory
Claim 20
Hornung (2023/0393970) teaches:
A system comprising: a first node, the first node comprising: a core; and P. 0038, 0042 and FIG. 2 CXL device 204 includes accelerator logic 222
means for global address translation, the core comprising: a core processing circuit; and P. 0042 accelerator logic 222 may be one or more processors
a memory management unit configured to map local virtual addresses to global virtual addresses, P. 0058 MMU may be logic within any of the processing units shown in FIGS. 1-3 (e.g. accelerator logic 222 of FIG. 2); P. 0048-49 a memory management unit (MMU) determines if the virtual address maps to an address in the global shared region by extracting the virtual device identification (VDID) field from the virtual address [extracting = mapping to local VA, see also P. 0060]
[…] map global virtual addresses to global physical addresses. P. 0045 and FIG. 3 a global virtual region in the virtual address space 365 are mapped to physical addresses in the global physical address space 360
Hornung does not explicitly teach a global address translation circuit external to a processor in addition to a memory management unit within the processor.
Vick (2009/0089537) teaches:
[…] the means for global address translation being configured to map global virtual addresses to global physical addresses, and FIG. 3 node virtualization table (310), an address space table (312); P. 0036 and FIG. 2A addresses in remote node A virtualized address space 206 [global virtual addresses] are mapped into remote node A's physical address space 210 [global physical addresses], while addresses in remote node B virtualized address space 208 [global virtual addresses] are mapped into remote node B's physical address space 212 [global physical addresses]
the global virtual addresses comprising global virtual address ranges of a first size corresponding to a first portion of the global virtual address space and a second size corresponding to a second portion of the global virtual address space. P. 0033 and FIG. 2B remote node virtualized address spaces 206 and 208 [global virtual address ranges] in FIG. 2A are part of the system address space [global virtual address space]
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung with the global address translation circuit external to a processor in addition to a memory management unit within the processor taught by Vick
The motivation being allow a memory access request addressing a virtual memory location on one node to be directly executed in the physical memory of another node (see Vick P. 0016)
The systems of Hornung and Vick do not explicitly teach the global virtual address spaces being of different sizes.
Godtland (2002/0042868) teaches:
the global virtual addresses comprising global virtual address ranges of a first size corresponding to a first portion of the global virtual address space and a second size corresponding to a second portion of the global virtual address space. P. 0046 if the base address of a virtual address indicates it is a global address, the boundary is set to a value that corresponds to the boundary for part of the global address space. More than one boundary may be defined, and the size of segments defined by the boundaries can vary.
It would have been obvious to a person with ordinary skill in the art at the effective filing date of the application to include the invention of Hornung and Vick with the global virtual address spaces being of different sizes taught by Godtland.
The motivation being to partition the global address space.
The systems of Hornung, Vick and Godtland are analogous because they are from the “same field of endeavor” and from the same “problem solving area.” Namely, they are both from the field of memory systems.
Therefore it would have been obvious to combine Hornung and Vick with Godtland to obtain the invention as recited in claims 20.
Allowable Subject Matter
Claims 6 and 17 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is an examiner’s statement of reasons for allowance:
Claim 6 recites the limitation “wherein the inter-node address offset is at least a factor of 100 greater than the first size”
Said limitation is taught by the specification of the instant application as originally filed at least at [P. 0010]. Said limitations, in combination with the other recited limitations of claim 6, are not taught or suggested by the prior art of record.
The closest prior art of record is Vick et al. (U.S. PGPub No. 2009/0089537) which teaches that a virtualized address space allocated for a node may have a different size than the physical address space of the node but does not teach the virtualized space allocated to a node being at least 100 times greater than the physical address space of the node.
Claim 17 contains similar limitations to claim 6, and are considered allowable for at least the same reasons as claim 6.
Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.”
Response to Arguments
Applicant’s arguments with respect to claim(s) 1 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
The examiner respectfully notes global virtual address spaces of different sizes are taught by new reference Godtland (2002/0042868).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Das et al. (U.S. PGPub No. 2021/0109879) teaches a plurality of nodes, each node including a cache controller which may perform functions of a shared memory controller, the shared memory controller including a translation structure to translate address values referenced by individual nodes 810 from the independent node-specific address domain to global address values for the pooled memory domain.
Dinan et al. (U.S. PGPub No. 2016/0314073) teaches a partitioned global address space (PGAS) with each node having a segment of its local memory associated with the PGAS, where PGAS segment parameters include a segment start address and segment size, the parameters used as an index to determine a physical address.
Bolkhovitin et al. (U.S. PGPub No. 2019/0294339) teaches dividing a received source logical address in the global logical address space, dividing the source logical address by the segment size to produce a first quotient, determining a segment offset corresponding to the destination segment (e.g., the integer portion of the first quotient).
Any inquiry concerning this communication or earlier communications from the examiner should be directed to STEPHANIE WU whose telephone number is (571)272-0257. The examiner can normally be reached 1pm to 6pm, and 10pm to 1am Eastern time (10am to 3pm, and 7pm to 10pm Pacific time).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio Del Mar Perez-Velez can be reached on (571) 270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/STEPHANIE WU/Primary Examiner, Art Unit 2133
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