DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The office action is responding to the amendments filed on 02/23/2026. Claims 1, 11 and 20 have been amended.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
Claim limitation in Claim 20 “means for processing” invokes 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph. However, the written description discloses the corresponding structure as “central processing units (CPUs) 115”. Therefore, the claim is not indefinite and considered proper.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1-2, 11-12 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khambam et al. [US 2019/0332528 A1] in view of Ivester et al. [US 11,074,113 B1] and in further view of Alsop et al. [US 2017/0371784 A1].
Claim 1 is rejected over Khambam, Ivester and Alsop.
Khambam teaches “A method, comprising: determining that a first data value in a cache is a global data value;” as “If it is determined at the step 506 that the data does meet some other criteria that merits initially loading the data into global cache” [¶0038]
“selectively invalidating one or more portions of the cache, wherein the selective invalidating of the cache comprises: determining, based on the first flag, that the first data value is a global data value; and” as “Following the step 508 is a step 512 where storage of the data in the global cache is cancelled (e.g., by setting an appropriate flag).” [¶0038]
Khambam does not explicitly teach setting a first flag to indicate that the first data value is a global data value; and
based on the determining that the first data value is a global data value, invalidating the first data value to prevent retrieval of the first data value from the cache, and
wherein the cache is configured to cache data from a local memory.
However, Ivester teaches “setting a first flag to indicate that the first data value is a global data value; and” as “To enable local cache operations to be managed independent of the fabric adapter, a cache metadata data structure includes a global flag bit for each cache slot, that is used to designate the cache slot as globally available or temporarily reserved for local IO processing.” [Col 1, lines 29-34]
Khambam and Ivester are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam and Ivester before him/her, to modify the teachings of Khambam to include the teachings of Ivester with the motivation of by relying on intelligent integration with Open Systems and Mainframe hosts, in some embodiments the storage system 100 provides hints to host 102 at an optimized IO path recommendation, to drive incoming sequential write IOs to a single storage engine 118, thus allowing for the exclusive use of these Peterson locks 325 for the duration of the 10 profile pattern. [Ivester, Col 5, lines 40-48]
The combination of Khambam and Ivester does not explicitly teach based on the determining that the first data value is a global data value, invalidating the first data value to prevent retrieval of the first data value from the cache, and
wherein the cache is configured to cache data from a local memory.
However, Alsop teaches “based on the determining that the first data value is a global data value, invalidating the first data value to prevent retrieval of the first data value from the cache, and” as “Conflict between memory scoping and work stealing can be reduced without incurring the costs of global data flushing, invalidation, or blocking of RMW operations using locking tables that indicate locking states of addresses of individual cache lines within caches in a heterogeneous processing system.” [¶0013] (Global data value invalidation is taught)
“wherein the cache is configured to cache data from a local memory.” as “The remote cache can be synchronized on a per-address basis with a cache within a local memory scope using the per-address lock, flush, invalidate, and RMW commands.” [¶0013] (Caching data from local memory is recited)
Khambam, Ivester and Alsop are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam, Ivester and Alsop before him/her, to modify the teachings of combination of Khambam and Ivester to include the teachings of Alsop with the motivation of memory scopes are defined to enforce memory consistency guarantees at different levels in the memory hierarchy allowing programmers to optimize for low-latency synchronization at smaller scopes rather than requiring programmers to always use slower global synchronization, i.e., synchronization at a larger scope. [Alsop, ¶0002]
Claim 2 is rejected over Khambam, Ivester and Alsop.
Khambam does not explicitly teach wherein the first flag is a bit in metadata associated with a cache line including the first data value.
However, Ivester teaches “wherein the first flag is a bit in metadata associated with a cache line including the first data value.” as “To enable local cache operations to be managed independent of the fabric adapter, a cache metadata data structure includes a global flag bit for each cache slot” [Col 1, lines 29-32]
Claim 11 is rejected over Khambam, Ivester and Alsop under the same rationale of rejection of Claim 1.
Claim 12 is rejected over Khambam, Ivester and Alsop under the same rationale of rejection of Claim 2.
Claim 20 is rejected over Khambam, Ivester and Alsop under the same rationale of rejection of Claim 1.
Claim(s) 3 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khambam et al. [US 2019/0332528 A1] in view of Ivester et al. [US 11,074,113 B1] in further view of Alsop et al. [US 2017/0371784 A1] and yet in further view of ELSASSER et al. [CN109983536A].
Claim 3 is rejected over Khambam, Ivester, Alsop and ELSASSER.
The combination of Khambam, Ivester and Alsop does not explicitly teach wherein the determining comprises determining by a hardware comparator.
However, ELSASSER teaches “wherein the determining comprises determining by a hardware comparator.” as “DRAM 64 has a comparison circuit 70” [Description]
Khambam, Ivester, Alsop and ELSASSER are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam, Ivester, Alsop and ELSASSER before him/her, to modify the teachings of combination of Khambam, Ivester and Alsop to include the teachings of ELSASSER with the motivation of memory circuit can more effectively as a set associative cache, because a set of positions can match command in response to a single tag to search the tag without the need for many individual read operation. [Description]
Claim 13 is rejected over Khambam, Ivester, Alsop and ELSASSER under the same rationale of rejection of Claim 3.
Claim(s) 3-4 and 14-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khambam et al. [US 2019/0332528 A1] in view of Ivester et al. [US 11,074,113 B1] in further view of Alsop et al. [US 2017/0371784 A1] in further view of ELSASSER et al. [CN109983536A] and yet in further view of KANNO [US 2022/0405199 A1].
Claim 4 is rejected over Khambam, Ivester, Alsop, ELSASSER and KANNO.
The combination of Khambam, Ivester Alsop and ELSASSER does not explicitly teach wherein the invalidating comprises invalidating by the hardware comparator.
However, KANNO teaches “wherein the invalidating comprises invalidating by the hardware comparator.” as “the invalidation process unit 124, the LBA comparison process unit 125, and the re-validation process unit 126 may be realized by dedicated hardware in the controller 4.” [¶0086]
Khambam, Ivester, Alsop, ELSASSER and KANNO are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam, Ivester, Alsop, ELSASSER and KANNO before him/her, to modify the teachings of combination of Khambam, Ivester, Alsop and ELSASSER to include the teachings of KANNO with the motivation of it is desired to realize a new invalidation process that can deal with a case where a host erroneously issues an invalidation request. [KANNO, ¶0005]
Claim 5 is rejected over Khambam, Ivester, Alsop, ELSASSER and KANNO.
Khambam teaches “wherein the cache is part of an integrated circuit, and” as “all or at least part of the global memory 37 may be provided on one or more of the directors 42a-42c and shared with other ones of the directors 42a-42c. In an embodiment, the features discussed in connection with the storage device 24 may be provided as one or more director boards having CPUs, memory (e.g., DRAM, etc.) and interfaces with Input/Output (I/O) modules.” [¶0033] (DRAM is an integrated circuit, which makes the cache.)
The combination of Khambam, Ivester and Alsop does not explicitly teach the hardware comparator is part of the integrated circuit.
However, ELSASSER teaches “the hardware comparator is part of the integrated circuit.” as “DRAM 64 has a comparison circuit 70” [Description] (DRAM is an integrated circuit)
Claim 14 is rejected over Khambam, Ivester, Alsop, ELSASSER and KANNO under the same rationale of rejection of Claim 4.
Claim 15 is rejected over Khambam, Ivester, Alsop, ELSASSER and KANNO under the same rationale of rejection of Claim 5.
Claim(s) 6-7 and 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khambam et al. [US 2019/0332528 A1] in view of Ivester et al. [US 11,074,113 B1] in further view of Alsop et al. [US 2017/0371784 A1] in further view of ELSASSER et al. [CN109983536A] in further view of KANNO [US 2022/0405199 A1] and yet in further view of HUANG et al. [US 2016/0210231 A1].
Claim 6 is rejected over Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG.
The combination of Khambam, Ivester, Alsop, ELSASSER and KANNO does not explicitly teach further comprising comparing a tag value associated with the first data value to a received tag value, wherein the comparing is performed by the hardware comparator.
However, HUANG teaches “further comprising comparing a tag value associated with the first data value to a received tag value, wherein the comparing is performed by the hardware comparator.” as “The hit/miss test unit 512 includes hardware to compare the requested physical tag with the tags of the cache lines stored in the SRAM 513 for determining the presence of a requested data.” [¶0041]
Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG before him/her, to modify the teachings of combination of Khambam, Ivester, Alsop, ELSASSER and KANNO to include the teachings of HUANG with the motivation of fixed-function pipeline module 230 has special-purpose hardware optimized for graphics pipeline processing. [HUANG, ¶0022]
Claim 7 is rejected over Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG.
The combination of Khambam, Ivester and Alsop does not explicitly teach wherein the integrated circuit further comprises a multiplexer connected to memory storing the first flag and to memory storing the tag value.
However, ELSASSER teaches “wherein the integrated circuit further comprises a multiplexer connected to memory storing the first flag and to memory storing the tag value.” as “the column multiplexer 38 and comparator 70 to implement desired operation.” [Description]
Claim 16 is rejected over Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG under the same rationale of rejection of Claim 6.
Claim 17 is rejected over Khambam, Ivester, Alsop, ELSASSER, KANNO and HUANG under the same rationale of rejection of Claim 7.
Claim(s) 8-9 and 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Khambam et al. [US 2019/0332528 A1] in view of Ivester et al. [US 11,074,113 B1] in further view of Alsop et al. [US 2017/0371784 A1] and yet in further view of JAYASENA et al. [US 2014/0173216 A1].
Claim 8 is rejected over Khambam, Ivester, Alsop and JAYASENA.
The combination of Khambam, Ivester and Alsop does not explicitly teach further comprising setting a second flag corresponding to a plurality of data values including the first data value.
However, JAYASENA teaches “further comprising setting a second flag corresponding to a plurality of data values including the first data value.” as “ Flags 206-212 include one or more validity flags ("V flag"), one or more dirty flags ("D flag"), one or more Alsopsient data flags ("T flag"), and one or more live flags ("L flag"). ” [¶0043]
Khambam, Ivester, Alsop and JAYASENA are analogous arts because they teach cache management in a memory system.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention, having the teachings of Khambam, Ivester, Alsop and JAYASENA before him/her, to modify the teachings of combination of Khambam, Ivester and Alsop to include the teachings of JAYASENA with the motivation of proactively invalidating dead (e.g. expired) data as enabled by embodiments increases the effective available cache capacity and reduces unnecessary writes to external memory, thereby enabling significant energy savings and performance benefits. [JAYASENA, ¶0024]
Claim 9 is rejected over Khambam, Ivester, Alsop and JAYASENA.
The combination of Khambam, Ivester and Alsop does not explicitly teach wherein the selective invalidating further comprises determining, based on the second flag, that at least one of the plurality of data values is a global data value.
However, JAYASENA teaches “wherein the selective invalidating further comprises determining, based on the second flag, that at least one of the plurality of data values is a global data value.” as “A cache line is invalid if neither of the following are true: V flag is set and T flag is not set (i.e. valid non-Alsopsient data); and V, T, and L flags are set (i.e. valid live Alsopsient data). Note that, if the D flag is set in a line that is not invalid, the cached data being overwritten is first written out to the primary memory.” [¶0088]
Claim 18 is rejected over Khambam, Ivester, Alsop and JAYASENA under the same rationale of rejection of Claim 8.
Claim 19 is rejected over Khambam, Ivester, Alsop and JAYASENA under the same rationale of rejection of Claim 9.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant’s arguments with respect to amended claim(s) have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MASUD K KHAN whose telephone number is (571)270-0606. The examiner can normally be reached Monday-Friday (8am-5pm).
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Hosain Alam can be reached at (571) 272-3978. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MASUD K KHAN/Primary Examiner, Art Unit 2132
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