Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statements (IDS) submitted on 04/04/2024, 05/21/2024, 07/16/2024, 03/11/2025,07/10/2025,11/12/2025, and 05/14/2026 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statements are being considered by the examiner.
Specification
The disclosure is objected to because of the following informalities:
Para. [0053] states “a
D
1
LH device” when it should state “a DLH device”
Para. [0055] states “an DLH device” when it should state “a DLH device”
Para. [0384] recites element 3710 which is not in fig. 37
Para. [0390] recites element 3839 which is not in fig. 38
Appropriate correction is required.
Claim Objections
The claims are objected to because of the following informalities:
In claim 1, the abbreviation ICLs should be put in parentheses when recited for the first time
Claim 1 recites “the two or more matrix processing chips” when it should recite “the two or more of the plurality of matrix processing chips”
Claim 1 recites “a matrix processing chip of the plurality of matrix processing chips” when it should recite “a matrix processing chip of the two or more of the plurality of matrix processing chips”
In claim 1, the abbreviation MPUs should be put in parentheses when recited for the first time
In claim 1, the abbreviation HBM should be put in parentheses when recited for the first time
Claim 1 recites “a matrix processing chip of the plurality of matrix processing chips” when it should recite “the matrix processing chip of the two or more of the plurality of matrix processing chips”
Claim 10 recites “the first or second input matrices, A/B” when it should recite “the first input matrix, A” and/or the second input matrix, B”
In claim 11, the abbreviation PCIe should be put in parentheses when recited for the first time
Appropriate correction is required.
Claim Interpretation
The following is a quotation of 35 U.S.C. 112(f):
(f) Element in Claim for a Combination. – An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
The following is a quotation of pre-AIA 35 U.S.C. 112, sixth paragraph:
An element in a claim for a combination may be expressed as a means or step for performing a specified function without the recital of structure, material, or acts in support thereof, and such claim shall be construed to cover the corresponding structure, material, or acts described in the specification and equivalents thereof.
This application includes one or more claim limitations that do not use the word “means,” but are nonetheless being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, because the claim limitation(s) uses a generic placeholder that is coupled with functional language without reciting sufficient structure to perform the recited function and the generic placeholder is not preceded by a structural modifier. Such claim limitation(s) is/are:
MPU is configured to in claim 1;
MPU is configured to in claim 5;
Because this/these claim limitation(s) is/are being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, it/they is/are being interpreted to cover the corresponding structure described in the specification as performing the claimed function, and equivalents thereof.
If applicant does not intend to have this/these limitation(s) interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph, applicant may: (1) amend the claim limitation(s) to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph (e.g., by reciting sufficient structure to perform the claimed function); or (2) present a sufficient showing that the claim limitation(s) recite(s) sufficient structure to perform the claimed function so as to avoid it/them being interpreted under 35 U.S.C. 112(f) or pre-AIA 35 U.S.C. 112, sixth paragraph.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-14 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 1 recites the limitation “the matrix routine.” There is insufficient antecedent basis for this limitation in the claim.
Claims 5 is rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claim 5 recites the limitation “the elements.” There is insufficient antecedent basis for this limitation in the claim.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-12 and 14 are rejected under 35 U.S.C. 103 as being unpatentable over Abellanas et al., US 2016/0179434 Al(“Abellanas”) in view of Zhu, Qiuling, et al. "A 3D-stacked logic-in-memory accelerator for application-specific data intensive computing." 2013 IEEE international 3D systems integration conference (3DIC). IEEE, 2013(“Zhu”).
Regarding claim 1 Abellanas teaches an apparatus, comprising:
a plurality of matrix processing chips integrated on a package, each matrix processing chip to process matrix instructions(Abellanas, paras., [0073-0083], see also figs., 4-5, “FIG. 4, multiprocessor system 400 is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450[a plurality of matrix processing chips integrated on a package]... [p]rocessors 470, 480 may each exchange information with a chipset 490 via individual P-P interfaces 452, 454 using point to point interface circuits 476, 494, 486, 498.” & see also Abellanas, paras. [0102-0104] “FIGS. 12A-B...include a processor 1200[each matrix processing chip]...[with] a neuromorphic accelerator 1230...configured as an external accelerator coupled to the processor... the neuromorphic accelerator 1230 includes a set of PUs 1300-1303 connected to the IO interface 1310...[t]he first bus (1) is used to bring data, kernels and weights to the PUs 1300-1303[to process matrix instructions]....”);
inter-chip links, ICLs, to connect two or more of the plurality of matrix processing chips, the ICLs to enable communication between the two or more matrix processing chips(Abellanas, paras., [0073-0083], see also figs., 4-5, “FIG. 4, multiprocessor system 400 is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450... [p]rocessors 470, 480 may each exchange information with a chipset 490 via individual P-P interfaces 452, 454 using point to point interface circuits 476, 494, 486, 498 [inter-chip links, ICLs, to connect two or more of the plurality of matrix processing chips, the ICLs to enable communication between the two or more matrix processing chips].”);
a matrix processing chip of the plurality of matrix processing chips comprising:
a host interface to couple the matrix processing chip to a host processor(Abellanas, paras. [0103-0130], see also figs., 12-22, “[A] neuromorphic
accelerator 1230...is configured as an external accelerator coupled to the processor via a bus or communication fabric[a host interface to couple the matrix processing chip to a host processor].”),
a plurality of matrix processing units, MPUs, wherein each MPU is to perform matrix multiplication operations(Abellanas, paras. [0103-0130], see also figs., 12-22, “[T]he neuromorphic accelerator 1230 includes a set of PUs 1300-1303[a plurality of matrix processing units, MPUs,]... input neurons are shared among PUs 1300-1303...all the PUs 1300-1303 have both the inputs and weights required for the computation...so they can perform the dot-product operation[wherein each MPU is to perform matrix multiplication operations]....”);
a memory to store tensor data used in the matrix multiplication operations(Abellanas, paras. [0103-0130], see also figs., 12-22, “Convolutional Neural Networks (CNNs )... make extensive use of 2D convolutions[used in the matrix multiplication operations]...[f]IG. 18A illustrates one embodiment of the memory organization where memory banks 1801-1806 and interconnects 1811-1816 are shared among different types of data ( e.g. the input image and partial results)[a memory to store tensor data]executed within an execution cluster 1800 ( e.g., comprising a plurality of processing units (PUs)).”); and
a controller to cause one or more of the matrix multiplication operations to be performed with the tensor data by one or more of the MPUs based on a matrix multiplication instruction(Abellanas, paras. [0103-0130], see also figs., 12-22, “A global control unit 1305[a controller] is in charge of driving the data from the IO interface 1310 to the PUs 1300-1303, as well as configuring each PU to execute the appropriate fully-connected configuration[by one or more of the MPUs based on a matrix multiplication instruction] at any point of time... input neurons are shared among PUs 1300-1303...all the PUs 1300-1303 have both the inputs and weights required for the computation...so they can perform the dot-product operation[to cause one or more of the matrix multiplication operations to be performed with the tensor data]....”);
[a plurality of high bandwidth memory, HBM, modules] associated with the matrix processing chip, [an HBM module of the plurality of HBM modules to store matrix data for processing] by a matrix processing chip of the plurality of matrix processing chips(Abellanas, paras., [0073-0083], see also figs., 4-5, “FIG. 4, multiprocessor system 400 is a point-to-point interconnect system, and includes a first processor 470 and a second processor 480 coupled via a point-to-point interconnect 450[associated with the matrix processing chip; by a matrix processing chip of the plurality of matrix processing chips]....”),1
wherein each MPU is configured to perform matrix multiplication operations based on a matrix multiplication instruction from the matrix routine, based on the matrix multiplication instruction including matrix operands(Abellanas, paras., [0138-0164], see also figs. 25-32, “Convolution operations[based on a matrix multiplication instruction] multiply together two arrays of numbers[perform matrix multiplication operations; from the matrix routine]...the selection logic 2820-2823 is in charge of creating the output data in a format ready to be consumed by the processing units... [t]he logic employed[based on the matrix multiplication instruction]...is shown in the table in FIG. 31. The first column refers to the image access mode being considered: row, colunms or squares. The four next colunms refers to the output packet. Note that,
C
x
refers to container number X, and
A
O
x
refers to the container aligned output in position X. As it is shown, the output is generated by reading the four aligned outputs of a single container in the 4B row mode[including matrix operands]... [t]his provides the convolution patterns to the execution cluster 2830....”),
the matrix operands to indicate a first input matrix, A and a second input matrix, B, the one or more MPUs to produce an output matrix, C, by multiplying the first input matrix, A and the second input matrix, B; the one or more MPUs to perform one or more post-multiplication operations(Abellanas, paras., [0138-0164], see also figs. 25-32, “Mathematically, the convolution may be described as:
O
x
,
y
=
∑
k
m
∑
l
n
I
x
+
k
-
1
,
y
+
l
-
1
K
(
k
,
l
)
where I is the input image, K is the kernel, and O(x,y) represents the pixel in coordinates x, y of the output image... several processing units (PU) to perform very efficiently a large number of multiplications[the one or more MPUs]...[f]IG. 26 shows an image 2600[the matrix operands to indicate a first input matrix, A] where a kernel of 4x4 pixels 2601[and a second input matrix, B,]...when the convolution operation starts, the kernel is applied over a squared image region of 4x4 pixels 2601. Once the first output pixel is computed[to produce an output matrix, C, by multiplying the first input matrix, A and the second input matrix, B;], the kernel is shifted to the right as indicated by dotted line region 2602 in the image[to perform one or more post-multiplication operations].”).
Abellanas does not teach: a plurality of high bandwidth memory, HBM, modules; an HBM module of the plurality of HBM modules to store matrix data for processing.
However, Zhu teaches:
a plurality of high bandwidth memory, HBM, modules(Zhu, pg., 2, see also fig. 2 and 6, “As shown in Fig. 2(b), a fine-grained die-stacked DRAM has
N
s
t
a
c
k
DRAM dies stacked vertically and each die implements
N
b
a
n
k
of DDR3 DRAM bank, and each bank has its own
N
i
o
-bit data TSV I/O[a plurality of high bandwidth memory, HBM, modules]. Every
N
s
t
a
c
k
stacked banks form a 3D vertical rank. Therefore, the overall system is composed of
N
b
a
n
k
of vertical ranks. All the banks in a 3D vertical rank share a single TSV bus....”);
an HBM module of the plurality of HBM modules to store matrix data for processing(Zhu, pg., 4, see also fig. 2, 4, and 6, “Fig. 6 shows the corresponding functional diagram of the 3D-stacked core architecture[an HBM module of the plurality of HBM modules]... each LiM core is composed of two local memory arrays for the storage of the source matrix block A and B, as well as a SpGEMM core which has arithmetic units tightly integrated with SRAM and content addressable memory (CAM) arrays to compute and assemble the resulting matrix block[to store matrix data for processing].”)
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Abellanas with the teachings of Zhu the motivation to do so would be to include high-bandwidth memory with in-memory computations to bypass the traditional memory bottleneck associated with processor-based architectures especially for high-throughput machine learning applications(Zhu, pg., 1, “In this paper we extend the 3D DRAM technology to accelerate application-specific data intensive computing that have notoriously inefficient memory access patterns. To achieve that, we customize the logic layer to be highly specialized and particularly optimized for a specific application.”).
Regarding claim 2, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein the first input matrix, A, and/or the second input matrix, B, are to be modified prior to multiplying the first input matrix, A and the second input matrix, B(Abellanas, paras., [0155-0164], see also figs. 28-32, “[T]he outputs from the row containers are connected to the alignment logic 2810-2813 which gives access to individual pixels of a row entry. The alignment
logic 2810-2813 makes it possible to apply simple data transformations, such as the data transpose required to generate image columns... [t]his provides the convolution patterns to the execution cluster 2830....”).2
Regarding claim 3, Abellanas in view of Zhu teaches the apparatus of claim 2, wherein to modify the first input matrix A, and/or the second input matrix, B, positions of one or more elements of the first input matrix A, and/or the second input matrix, B, are to be shifted or shuffled(Abellanas, paras., [0155-0164], see also figs. 28-32, “The output of the
bitmask shifter 2902 selects a buffer entry into which the input data is written. Although pixels are always written in sequence (like in a FIFO buffer), they can be read randomly... [t]his provides the convolution patterns to the execution cluster 2830....”).
Regarding claim 4, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein the post-multiplication operations are unary operations on data elements(Abellanas, paras., [0138-0164], see also figs. 25-32, “[W]hen the convolution operation starts, the kernel is applied over a squared image region of 4x4 pixels 2601. Once the first output pixel is computed, the kernel is shifted to the right as indicated by dotted line region 2602 in the image[wherein the post-multiplication operations are unary operations on data elements].”).
Regarding claim 5, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein each MPU is configured to perform a matrix-wide operation to process data among the elements of a single matrix(Abellanas, paras. [0104-0109], see also figs., 13-14, “Turning first to FIGS. 14A-B, the fully connected l-to-1 operation maps one logical neuron to one physical neuron that is computed in a single PU 1300-1303[wherein each MPU is configured to]. To perform the dot-product operation, both the input neurons and the synapses (weights) 1400-1403 are sent... [n]onetheless, input neurons are shared among PUs 1300-1303[perform a matrix-wide operation to process data among the elements of a single matrix...so they can perform the dot-product operation and accumulate the result with the previous computation if the neuron has many inputs.”).
Regarding claim 6, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein a pre-matrix multiplication operation is performed on one or more elements of the first input matrix, A, or the second input matrix, B, prior to the matrix multiplication(Abellanas, paras., [0155-0164], see also figs. 28-32, “[T]he outputs from the row containers are connected to the alignment logic 2810-2813 which gives access to individual pixels of a row entry[one or more elements of the first input matrix, A,]. The alignment logic 2810-2813 makes it possible to apply simple data transformations, such as the data transpose required to generate image columns[wherein a pre-matrix multiplication operation is performed prior to the matrix multiplication]... [t]his provides the convolution patterns to the execution cluster 2830....”).3
Regarding claim 7, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein the one or more matrix processing units, MPUs, are included in matrix processing clusters(Abellanas, paras., [0130-0137], see also figs., 22 and 28, “[T]he PWBB 2204 is a set of
buffers responsible for keeping the partial results provided by the PU s of the execution cluster 1800[wherein the one or more matrix processing units, MPUs, are included in matrix processing clusters]....”),
and wherein the apparatus further comprises: a cluster controller to control matrix operations within a corresponding matrix processing cluster(Abellanas, paras., [0130-0137], see also figs., 22 and 28, “[T]he PWBB 2204 is a set of buffers responsible for keeping the partial results provided by the PU s of the execution cluster 1800[within a corresponding matrix processing cluster] while the destination banks are busy... the control unit 2205[a cluster controller] is responsible for...grants permission to the PWBB 2204 to write partials in the idle buses and banks[to control matrix operations].”).
Regarding claim 8, Abellanas in view of Zhu teaches the apparatus of claim 7, wherein the cluster controller causes the matrix multiplication instruction to be executed using one or more MPUs in a corresponding cluster(Abellanas, paras. [0153-0164], see also figs., 28-32, “A high-level block diagram...of an accelerator with 4 clusters is shown in FIG. 28. This embodiment of the invention includes four components: (1) input and distribution logic 2850[the cluster controller]...[t]he processing units 2830 collaborate to traverse the image, applying the convolution operations[matrix multiplication instruction] to the pixels (multiplications and additions), and grouping the results to generate the final output image. In this process, each cluster of processing units 2830 works with a subset of pixels from the input image. The input logic 2850 gets the image data from upper cache levels, and selectively broadcasts it...according to the computation requirements of each cluster of processing units[causes to be executed using one or more MPUs in a corresponding cluster].”).
Regarding claim 9, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein at least one MPU is to receive matrix data(Abellanas, paras. [0153-0164], see also figs., 28-32, “In this process, each cluster of processing units 2830 works with a subset of pixels from the input image. The input logic 2850 gets the image data from upper cache levels, and selectively broadcasts it...according to the computation requirements of each cluster of processing units[wherein at least one MPU is to receive matrix data].”)
from the HBM module of the plurality of HBM modules(Zhu, pgs., 3-4, see also fig. 2, 4, and 6, “As matrix blocks are mapped to DRAM rows which are accessed in the sequential order, for each LiM core computation, we can access the two source blocks from the carefully scheduled active row buffers via TSV bus[from the HBM module of the plurality of HBM modules].”),
wherein the matrix data is associated with the matrix operands of the matrix multiplication instruction(Abellanas, paras. [0153-0164], see also figs., 28-32, “The processing units 2830 collaborate to traverse the image, applying the convolution operations[of the matrix multiplication instruction] to the pixels[wherein the matrix data is associated with the matrix operands] (multiplications and additions), and grouping the results to generate the final output image.”).4
Regarding claim 10, Abellanas in view of Zhu teaches the apparatus of claim 1, further comprising a slicing engine to: interface with the memory; read data elements in a set of one or more rows of the first or second input matrices, A/B, from the memory; and provide the data elements to one or more MPUs of the plurality of MPUs(Abellanas, paras. [0153-0164], see also figs., 28-32, “[T]he accelerator handles two types of information when performing convolutions: input image data (pixels) and kernel weights. Both types of information
are stored in the containers 2800-2803[a slicing engine to:], which may be implemented as tag-less storage units[interface with the memory;] that allow reading and writing multiple consecutive pixels in parallel[read data elements in a set of one or more rows of the first or second input matrices, A/B, from the memory]... [t]o do so...the selection logic 2820-2823 reads the aligned outputs from one or multiple containers 2800-2803, and places this information into the output packet for the execution cluster 2830[and provide the data elements to one or more MPUs of the plurality of MPUs].”).5
Regarding claim 11, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein the host interface is to couple the matrix processing chip to a Peripheral Component Interconnect Express, PCIe, bus(Abellanas, para. 0077, see also figs. 3-4, “Chipset 490 may be coupled to a first bus 416 via an interface 496[wherein the host interface is to couple the matrix processing chip]...first bus 416 may be...a bus such as a PCI Express bus[to a Peripheral Component Interconnect Express, PCIe, bus].”).
Regarding claim 12, Abellanas in view of Zhu teaches the apparatus of claim 7, wherein the controller is to control and/or manage matrix operations in conjunction with the cluster controller(Abellanas, paras. [0103-0137], see also figs., 12-22 and 28, “A global control unit 1305[wherein the controller] is in charge of driving the data from the IO interface 1310 to the PUs...[to] execute the appropriate fully-connected configuration[is to control and/or manage matrix operations]...the PWBB 2204 is a set of buffers responsible for keeping the partial results provided by the PUs of the execution cluster 1800 while the destination banks are busy... the control unit 2205[in conjunction with the cluster controller] is responsible for...grant[ing] permission to the PWBB 2204 to write partials in the idle buses and banks.).
Regarding claim 14, Abellanas in view of Zhu teaches the apparatus of claim 1, wherein the controller comprises a chip-level controller(Abellanas, paras. [0102-0104], see also figs. 12 and 13, “[]uncore[] component 1210[a chip-level controller]comprising a communication bus structure or fabric for interconnecting the cores 1201-1203, N...a neuromorphic accelerator 1230...coupled to the processor via a bus or communication fabric.”).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. US 10,929,944 B2(details a GPU co-processor with HBM modules)
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ADAM C STANDKE whose telephone number is (571)270-1806. The examiner can normally be reached Gen. M-F 9-9PM EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Michael J Huntley can be reached at (303) 297-4307. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Adam C Standke/
Primary Examiner
Art Unit 2129
1 Examiner Notes: The claim limitations that are not in bold and contained within square brackets (i.e., [ ]) are
claim limitations that are not taught by the prior art of Abellanas.
2 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
3 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
4 It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the teachings of Abellanas with the above teachings of Zhu for the same rationale stated at Claim 1.
5 According to the broadest reasonable interpretation (BRI), the use of alternative language amounts to the claim requiring one or more elements but not all.
Prosecution Insights