DETAILED ACTION
The current Office Action is in response to the papers submitted 12/03/2025. Claims 1 – 10, 12 - 20 are pending.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1 – 3 and 12 - 14 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Smalley (Pat 5,907,862) referred to as Smalley.
Regarding claim 1, Smalley teaches a method for sharing a storage device [15, Fig 1] among multiple processors [12 and 14, Fig 1], comprising:
controlling a first processor [12, Fig 1] among the multiple processors [12 and 14, Fig 1] to operate in an access mode [102, 104, 106, and 108, Fig 3A, The access mode is processing that happens after a YES outcome in step 102], and controlling a second processor [14, Fig 1] among the multiple processors [12 and 14, Fig 1] to operate in a detection mode [120 and 122, Fig 3B; The NO loop is a detection mode of the second processor detecting when it can access the storage device];
in response to the first processor [12, Fig 1] operating in the access mode [102, 104, 106, and 108, Fig 3A], utilizing the first processor [12, Fig 1] to control a logic value of a busy signal [REQ E, Fig 2; 104, 106, and 108, Fig 3A; Processor 12 changes the busy signal REQ E in step 104], to indicate that the first processor [12, Fig 1] has permission to access the storage device [15, Fig 1], wherein the busy signal is a single-bit signal [REQ E, Fig 2; The signal is a single logical bit value such as 1 or 0];
in response to at least one first predetermined condition, controlling the first processor [12, Fig 1] to enter the detection mode [100 and 102, Fig 3A; Column 7, Lines 1 – 23; The NO loop is a detection mode based on the predetermined condition in step 102] from the access mode [102, 104, 106, and 108, Fig 3A];
in response to at least one second predetermined condition, controlling the second processor [14, Fig 1] to enter the access mode [122, 124, 126, and 128, Fig 3B; The second processor enters the access mode based on the YES outcome of step 122] from the detection mode [120 and 122, Fig 3B; Column 7, Lines 24 – 56; The second processor switch modes based on the outcome of step 122]; and
in response to the second processor [14, Fig 1] operating in the access mode [122, 124, 126, and 128, Fig 3B], utilizing the second processor [14, Fig 1] to control the logic value of the busy signal [REQ E, Fig 2; 124, Fig 3B; Column 5, Lines 49 – 67; Column 6, Lines 1 – 29; Column 7, Lines 1 – 23; Processor 14 setting the REQ H bit signal also controls the busy signal REQ E due to the logical configuration of the access control logic of figure 2], to indicate that the second processor [14, Fig 1] has the permission to access the storage device [15, Fig 1].
Regarding claim 2, Smalley teaches the first processor and the second processor [12 and 14, Fig 1] are alternately switched between the access mode and the detection mode, to make the first processor and the second processor control the logic value of the busy signal by turns [Figs 3A – 3B; Column 6, Lines 48 – 67, Column 7, Lines 1 – 56; The processors alternate modes based on the values of REQ E].
Regarding claim 3, Smalley teaches utilizing the first processor [12, Fig 1] to control the logic value of the busy signal [104, Fig 3A; Column 7, Lines 1 – 23; The busy signal is the logic value of REQ E bit] to indicate that the first processor [12, Fig 1] has the permission to access the storage device [15, Fig 1] in response to the first processor [12, Fig 1] operating in the access mode [102, 104, 106, and 108, Fig 3A] comprises:
in response to the first processor operating in the access mode [102, 104, 106, and 108, Fig 3A], utilizing the first processor [12, Fig 1] to pull the busy signal from a first logic value to a second logic value [106, Fig 3A; Column 7, Lines 1 – 23; The first processor changes the REQ E bit from 0 to 1].
Claims 12 - 14 are device claims corresponding to method claims 1 – 3 and are thus rejected using the same prior art and similar reasoning. The system [10, Fig 1] is a device that contains storage [15, Fig 1] and is configured to store any type of information requested to be stored.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 4, 6 – 8, 15, and 17 - 19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smalley (Pat 5,907,862) referred to as Smalley as applied to claims 1, 3, 12, 14 above, and further in view of Disegni et al. (Pub. No.: US 2019/0317902) referred to as Disegni.
Regarding claim 4, Smalley teaches controlling the first processor [12, Fig 1] to enter the detection mode [100 and 102, Fig 3A] from the access mode [102, 104, 106, and 108, Fig 3A] in response to the at least one first predetermined condition [Column 7, Lines 1 – 23; The NO loop is a detection mode based on the predetermined condition in step 102];
the first processor pulling the busy signal from the first logic value to the second logic value [106, Fig 3A; Column 7, Lines 1 – 23; The first processor changes the REQ E logic value].
However, Smalley may not specifically disclose the limitations of starting counting time at a time point of the first processor entering an access mode, to generate an access time, wherein the first processor comprises a state machine, and the state machine controls the first processor to enter the detection mode from the access mode in response to the access time reaching a predetermined access time threshold.
Disegni discloses starting counting time at a time point of the first processor [12, 8, and 15, Fig 2] entering a mode [104, Fig 3], to generate an access time, wherein the first processor [12, 8, and 15, Fig 2] comprises a state machine and the state machine [15, Fig 2; Fig 3] is configured to control the first processor [12, 8, and 15, Fig 2] to enter the detection mode [SUSPENSION, Figs 4A – 4B; The suspension indicates a detection mode based on time thresholds or prior operations completing, whichever occurs first] from the access mode [104, 3] in response to the access time reaching a predetermined access time threshold [Paragraphs 0035; A timer is started when a processor starts accessing shared memory and when the timer reaches a threshold the processor access is suspended which is considered the detection mode].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Disegni in Smalley, because it prevents a given processor from being starved of access to memory but limiting how much time a given processor can access the memory before another processor is granted access to the memory.
Regarding claim 6, Smalley teaches controlling the first processor [12, Fig 1] to enter the detection mode [100 and 102, Fig 3A] from the access [102, 104, 106, and 108, Fig 3A] mode in response to the at least one first predetermined condition [100 and 102, Fig 3A; Column 7, Lines 1 – 23; The NO loop is a detection mode based on the predetermined condition in step 102] comprises:
the first processor [12, Fig 1] pulling the busy signal from the first logic value to the second logic value [106, Fig 3A; Column 7, Lines 1 – 23; The first processor changes the REQ E logic value].
wherein the first processor [12, Fig 1] comprises a signal control circuit [12, Fig 1; Processors contain circuits that control their operations], and the signal control circuit controls the first processor [12, Fig 1] to enter the detection mode [100 and 102, Fig 3A] from the access mode [102, 104, 106, and 108, Fig 3A] and make the busy signal be released back to the first logic value from the second logic value [Figs 3A – 3B; Column 6, Lines 48 – 67, Column 7, Lines 1 – 56; The processors alternate modes based on the values of REQ E and REQ H being changed by the processors when a given access request is started and ended].
Disegni discloses starting counting time at a time point of the first processor [12, 8, and 15, Fig 2] entering a mode [104, Fig 3], to generate an access time [Paragraphs 0035; A timer is started when a processor starts accessing shared memory and when the timer reaches a threshold the processor access is suspended which is considered the detection mode], the first processor [12, 8, and 15, Fig 2] further comprises a signal control circuit [15, Fig 2; Fig 3], and the signal control circuit [15, Fig 2; Fig 3] is configured to control the first processor [12, 8, and 15, Fig 2] to enter the detection mode [SUSPENSION, Figs 4A – 4B] from the access mode [104, 3] in response to the first processor not sending any access instruction and the access time reaching a minimum access time threshold, in order to make the busy signal be released back to the first logic value from the second logic value [Paragraphs 0052 – 0056; The “in order” limitation is an intended use of switching modes. The time threshold can be changed as needed such that one threshold causes a processor to transition modes before another processor switch modes independent of access requests from the processor and based on time].
Regarding claim 7, Smalley teaches controlling the second processor [14, Fig 1] to enter the access mode [122, 124, 126, and 128, Fig 3B] from the detection mode [120 and 122, Fig 3B] in response to the at least one second predetermined condition [Column 7, Lines 24 – 56; The second processor switch modes based on the outcome of step 122] comprises:
the second processor pulling the busy signal to the first logical value from the second logic value REQ E, Fig 2; 124, Fig 3B; Column 5, Lines 49 – 67; Column 6, Lines 1 – 29; Column 7, Lines 1 – 23; Processor 14 setting the REQ H bit signal also controls the busy signal REQ E due to the logical configuration of the access control logic of figure 2].
However, Smalley may not specifically disclose the limitations of starting counting at a time point of the first processor entering a mode, to generate a debounce time, wherein the second processor comprises a state machine, and the state machine is configured to control the second processor to enter the access mode from the detection mode in response to the debounce time reaching a debounce time threshold.
Disegni discloses starting counting time at a time point of the first processor [12, 8, and 15, Fig 2] entering a mode, to generate a debounce time, wherein the second processor [14, 10, and 15, Fig 2] comprises a state machine [Fig 3], and the state machine [Fig 3] controls the second processor [14, 10, and 15, Fig 2] to enter the access mode [108, Fig 3] from the detection mode [SUSPENSION, Figs 4A – 4B; The suspension indicates is a detection mode based on time thresholds or prior operations completing, whichever occurs first], in response to the debounce time reaching a debounce time threshold [Fig 4B; Paragraphs 0055 – 0056; The time between t4 and t5 and the time between t6 and t6+δ are examples of debounce times caused by a processor entering a certain mode dictating when another processor can enter a certain mode. When the debounce time threshold is reached the modes of the processors are changed accordingly].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Disegni in Smalley, because it prevents a given processor from being starved of access to memory but limiting how much time a given processor can access the memory before another processor is granted access to the memory and provides delay is signal changes to make sure signals are at a steady state.
Regarding claim 8, Smalley teaches controlling the second processor [14, Fig 1] to enter the access mode [122, 124, 126, and 128, Fig 3B] from the detection mode [120 and 122, Fig 3B] in response to the at least one second predetermined condition [Lines 24 – 56; The second processor switch modes based on the outcome of step 122] comprises:
wherein the second processor [14, Fig 1] comprises a signal control circuit, and the signal control circuit [12, Fig 1; Processors contain circuits that control their operations] controls the second processor [14, Fig 1] to enter the access mode [122, 124, 126, and 128, Fig 3B] from the detection mode [120 and 122, Fig 3B] in response to the at least one first predetermined condition [Column 7, Lines 24 - 56; The NO loop is a detection mode based on the predetermined condition in step 122];
the second processor pulling the busy signal from the first logic value to the second logic value [REQ E, Fig 2; 124, Fig 3B; Column 5, Lines 49 – 67; Column 6, Lines 1 – 29; Column 7, Lines 1 – 23; Processor 14 setting the REQ H bit signal also controls the busy signal REQ E due to the logical configuration of the access control logic of figure 2].
However, Smalley may not specifically disclose the limitations of starting counting time at a time point of the second processor starting operating in the detection mode, to generate a detection time, wherein the second processor comprises a signal control circuit, and the signal control circuit is configured to control the second processor to enter the access mode from the detection mode in response to the detection time reaching a detection time threshold, in order to pull the busy signal from a first logic value to a second logic value.
Disegni discloses starting counting at a time point of the second processor starting [14, 10, and 15, Fig 2] operating in the detection mode [SUSPENSION, Figs 4A – 4B; The suspension indicates is a detection mode based on time thresholds or prior operations completing, whichever occurs first], to generate a detection time, wherein the second processor [14, 10, and 15, Fig 2] comprises a signal control circuit [15, Fig 2], and the signal control circuit [15, Fig 2] is configured to control the second processor [14, 10, and 15, Fig 2] to enter the access mode [108, Fig 3] from the detection mode [SUSPENSION, Figs 4A – 4B] in response to the detection time reaching a detection time threshold [SUSPENSION, Figs 4A – 4B; The suspension indicates is a detection mode based on time thresholds or prior operations completing, whichever occurs first].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Disegni in Smalley, because it prevents a given processor from being starved of access to memory but limiting how much time a given processor can access the memory before another processor is granted access to the memory and provides delay is signal changes to make sure signals are at a steady state.
Claims 15and 17 - 19 are device claims corresponding to claims 4 – 8 and are thus rejected using the same prior art and similar reasoning. The system [10, Fig 1] is a device that contains storage [15, Fig 1] and is configured to store any type of information requested to be stored.
Claim(s) 9 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smalley (Pat 5,907,862) referred to as Smalley as applied to claims 1 and 12 above, and further in view of Disegni et al. (Pub. No.: US 2019/0317902) referred to as Disegni in view of Albot et al. (Pub. No.: US 2017/0123780) referred to as Albot.
Regarding claim 9, Smalley an electronic device [10, Fig 1] comprises the multiple processors [12 and 14, Fig 1] and the storage device [15, Fig 1], an update equipment [16 – 20, Fig 1; The items 16 – 20 write data to memory 15 based on signals from the processors 12 and 14] writes data into the storage device [15, Fig 1] to perform a data update of the electronic device [10, Fig 1] during a period of the first processor operating in the access mode [102, 104, 106, and 108, Fig 3A; The first processor having controls means the processor reads and writes data from and to the memory], and the method further comprises:
after the updated data is written into the storage device, utilizing the update equipment [16 – 20, Fig 1] to perform a soft reset on the first processor [12, Fig 1], and releasing the busy signal back to a first logic value from a second logic value [100 and 102, Fig 3A; Column 7, Lines 1 – 23; Resetting the bits so the first processor enters the NO loop is a soft reset letting the other processor gain control of the memory]; and
performing the soft reset of the second processor [14, Fig 1] in response to the busy signal being released back to the first logic value from the second logic value [REQ E, Fig 2; 124, Fig 3B; Column 5, Lines 49 – 67; Column 6, Lines 1 – 29; Column 7, Lines 1 – 56; Processor 14 setting the REQ H bit signal also controls the busy signal REQ E due to the logical configuration of the access control logic of figure 2 which puts the second processor in a soft reset mode in the NO loop in figure 3B].
However, Smalley may not specifically disclose the limitations of update equipment that writes an updated program code into the storage device to perform a firmware update of the electronic device, after the updated program code is completely written into the storage device, utilizing the update equipment to perform a soft reset on the first processor, and utilizing at least one counter of the second processor to start counting at a time point of starting the firmware update to generate an update time, and performing the soft reset of the second processor in response to the update time reaching an update time threshold.
Disegni discloses utilizing at least one counter of the second processor [14, 10, and 15, Fig 2] to start counting time at a time point of starting a software update to generate an update time, and performing the soft reset of the second processor in response to the update time reaching an update time threshold [Fig 4B, Time t4 is the start of counting time to perform the programming between t5 and t6. Reaching time t5 performs a soft reset of the processor by allowing the processor to be reset into a programming mode].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Disegni in Smalley, because it prevents a given processor from being starved of access to memory but limiting how much time a given processor can access the memory before another processor is granted access to the memory and provides delay is signal changes to make sure signals are at a steady state.
However, Smalley in view of Disegni may not specifically disclose the limitations of update equipment that writes an updated program code into the storage device to perform a firmware update of the electronic device, after the updated program code is completely written into the storage device, utilizing the update equipment to perform a soft reset on the first processor.
Albot discloses update equipment that writes an updated program code into the storage device to perform a firmware update of the electronic device, after the updated program code is completely written into the storage device, utilizing the update equipment to perform a soft reset on the first processor [Fig 5; Firmware is completely written into memory in step 510. Steps 520, 530, and 540 occur after the firmware is completely written into memory and constitute a soft reset since the accelerator/processor is paused, the processor/accelerator is updated with the new firmware, and then the processor/accelerator is resumed using the updated firmware].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Albot in Smalley in view of Disegni, because it allows for new features to be added to hardware overtime [Paragraphs 0005 – 0006].
Claim 20 is a device claim corresponding to claim 9 and is thus rejected using the same prior art and similar reasoning. The system [Smalley; 10, Fig 1 ] is a device that contains storage [Smalley; 15, Fig 1] and is configured to store any type of information requested to be stored.
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Smalley (Pat 5,907,862) referred to as Smalley as applied to claim 1 above, and further in view of Disegni et al. (Pub. No.: US 2019/0317902) referred to as Disegni in view of Kulkarni et al (Pat 9,477,257) referred to as Kulkarni.
Regarding claim 10, Smalley teaches a first processor [12, Fig 1] and a second processor [14, Fig 1].
However, Smalley may not specifically disclose the limitations of a first processor comprising at least one first counter, the second processor comprises at least one second counter, the at least one first counter performs counting time based on a clock signal, and the at least one second performs counting based on the clock signal.
Disegni discloses a first processor [12, 8, and 15, Fig 2] and a second processor [14, 10, and 15, Fig 2] along with the use of at least one counter [24, Fig 2] in one of the processors [12, 8, and 15, Fig 2].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Disegni in Smalley, because it prevents a given processor from being starved of access to memory but limiting how much time a given processor can access the memory before another processor is granted access to the memory and provides delay is signal changes to make sure signals are at a steady state.
However, Smalley in view of Disegni may not specifically disclose the limitation of a first processor [100, Fig 1; Item 100 represents any number of processors in a system] comprising at least one first counter [120, Fig 1; 226, Fig 2], the second processor [100, Fig 1; Item 100 represents any number of processors in a system] containing at least one second counter [120, Fig 1; 226, Fig 2], there at least one first counter performs counting time based on a clock signal, and the at least one second counter performs counting time based on the clock signal [Column 7, Lines 14 – 34; This shows a processor contains a counter based on a clock signal that is the same since each processor has the same clock module that generates a clock signal].
Therefore, it would have been obvious to a person of ordinary skill in the art before the effective filing date of the claimed invention to incorporate Kulkarni in Smalley in view of Disegni, because it allows for improved systems and methods of clock gating for power saving while limiting current surges compared [Column 2, Lines 7 – 23].
Allowable Subject Matter
Claims 5 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
Response to Arguments
Applicant's arguments filed 12/03/2025 have been fully considered but they are not persuasive.
The applicant argues on pages 14 – 15 that Smalley fails to teach the amended limitations of the busy signal being a single bit. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The amendments changes the scope of the claims regarding what the scope of the busy signal is. Smalley teaches the use of a REQ E signal and a REQ H signal that are each a single bit. Further, Smalley discloses due to the relationship of the logical configuration of figure 2 that the second processor changes REQ E by changing REQ H as disclosed in column 7 lines 1 – 23. This shows the second processor changes the busy signal REQ E by changing REQ H.
The applicant argues on pages 15 – 16 that all remaining claims are allowable for being dependent on claim 1 which is argued allowable on pages 14 – 15. After careful consideration of the applicant’s arguments the examiner respectfully disagrees.
The examiner has responded to the arguments against claim 1 above showing how the prior art reads on the newly argued amended limitations. The rejections of the dependent claims are maintained based in part on the new interpretation of Smalley.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to CHRISTOPHER D BIRKHIMER whose telephone number is (571)270-1178. The examiner can normally be reached 8-5 Hoteling.
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/Christopher D Birkhimer/ Primary Examiner, Art Unit 2136