DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 102
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claims 1-5 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Tsai et al. 20200058606.
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Regarding claim 1, fig. 16 of Tsai discloses a semiconductor package, comprising:
an antenna structure 400 which comprises a dielectric layer 100A that is made of a transparent material (par [0016] – glass), an active antenna pattern 408 (par [0068]) that is formed on one surface of the dielectric layer and a parasitic antenna pattern 410 (par [0068]) that is formed on the other surface of the dielectric layer opposite to the one surface;
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a first rewiring structure (fig. 12 above - 409/118/402/116) which is electrically connected to the active antenna pattern of the antenna structure;
a molding body 302 which is formed on one surface of the first rewiring structure;
a semiconductor chip 220 which is placed within the molding body;
a second rewiring structure 210 which is formed on one surface of the molding body;
a vertical connection conductor 214 (fig. 14) which is laterally spaced from the semiconductor chip, penetrates the molding layer, and electrically connects the second rewiring structure and the first rewiring structure; and
an external connection terminal 306 which is formed on one surface of the second rewiring structure.
Regarding claim 2, Tsai discloses wherein the dielectric layer of the antenna structure is made of a glass material (par [0016] – glass).
Regarding claim 3, fig. 16 of Tsai disclose wherein the dielectric layer of the antenna structure is a carrier on which the first rewiring structure, the molding body and the second rewiring structure are formed.
Regarding claim 4, Tsai discloses wherein the thickness of the dielectric layer is between 100 micrometers and 500 micrometers (par [0016] …The core substrate 101 may have a thickness between about 200 μm and about 1000 μm, such as about 400 μm or about 900 μm).
Regarding claim 5, fig. 16 of Tsai discloses further comprising: a protective layer 116 for covering and protecting the other surface of the dielectric layer and the parasitic antenna pattern (see 116 surround 410 and acts as protecting walls).
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tsai in view of Kim et al. 20200211976.
Regarding claim 6, Tsai discloses a method for manufacturing a semiconductor package, comprising:
an active antenna pattern formation step of forming an active antenna pattern on one surface of a carrier that is made of a transparent glass material (figs. 1-3);
a first rewiring step of forming a first rewiring structure on the surface of the carrier on which the antenna pattern is formed (figs. 4-5);
a chip placement step of placing a semiconductor chip on the first rewiring structure (fig. 10A);
a molding step of forming a molding body 302 by molding a molding agent on the first rewiring structure on which the semiconductor chip is disposed (fig. 10A);
a second rewiring step of forming a second rewiring structure on one surface of the molding body (fig. 10A); and
Tsai does not disclose of an individualization step of individualizing the first rewiring structure, molding body, semiconductor chip and second rewiring structure by cutting the same together with the carrier that is made of the glass material.
However, fig. 2E discloses a method of forming a semiconductor package comprising an individualization step of individualizing a semiconductor package in order to form individual package.
In view of such teaching, it would have been obvious to form a method further comprising an individualization step of individualizing the first rewiring structure, molding body, semiconductor chip and second rewiring structure by cutting the same together with the carrier that is made of the glass material such as taught by Kim in order to form many package at once and then separate them into individual.
Regarding claim 7, par [0020] of Tsai discloses wherein after the active antenna pattern formation step, a parasitic antenna pattern formation step is performed by inverting the carrier to form a parasitic antenna pattern on the other surface opposite to the one surface of the carrier (par [0020] -A similar process may then be performed on the opposite side of the core substrate 101 to form conductive features (or remaining portions of through-vias) on the opposite side of the core substrate 101. In this manner, the conductive material may form conductive features and through-vias).
Regarding claim 8, par [0020] of Tsai discloses wherein before the active antenna pattern formation step, a parasitic antenna pattern formation step is performed by inverting the carrier to form a parasitic antenna pattern on the other surface opposite to the one surface of the carrier (par [0020] -A similar process may then be performed on the opposite side of the core substrate 101 to form conductive features (or remaining portions of through-vias) on the opposite side of the core substrate 101. In this manner, the conductive material may form conductive features and through-vias).
Allowable Subject Matter
Claim 9 is allowed.
Claim 9 recites “an inversion step of inverting the carrier and the first rewiring structure, molding body, semiconductor chip and second rewiring structure that are built up on the carrier; a parasitic antenna pattern formation step of forming a parasitic antenna pattern on the other surface of the inverted carrier by aligning the same with the active antenna pattern”, this limitation is not taught by prior of record.
Conclusion
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/VONGSAVANH SENGDARA/ Primary Examiner, Art Unit 2893