Prosecution Insights
Last updated: April 19, 2026
Application No. 18/535,221

SEMICONDUCTOR MEMORY DEVICE AND METHOD OF MANUFACTURING SEMICONDUCTOR MEMORY DEVICE

Non-Final OA §103
Filed
Dec 11, 2023
Examiner
AMER, MOUNIR S
Art Unit
2818
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
Kioxia Corporation
OA Round
1 (Non-Final)
88%
Grant Probability
Favorable
1-2
OA Rounds
2y 2m
To Grant
97%
With Interview

Examiner Intelligence

Grants 88% — above average
88%
Career Allow Rate
531 granted / 602 resolved
+20.2% vs TC avg
Moderate +9% lift
Without
With
+8.6%
Interview Lift
resolved cases with interview
Typical timeline
2y 2m
Avg Prosecution
24 currently pending
Career history
626
Total Applications
across all art units

Statute-Specific Performance

§103
55.1%
+15.1% vs TC avg
§102
24.4%
-15.6% vs TC avg
§112
8.2%
-31.8% vs TC avg
Black line = Tech Center average estimate • Based on career data from 602 resolved cases

Office Action

§103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Status of the Application This Office Action is in response to Applicant’s application 18/535,221 filed on December 11 2023 in which claims 1 to 20 are pending. Drawings The drawings submitted on December 11 2023 have been reviewed and accepted by the Examiner. Information Disclosure Statement The Information Disclosure Statement (IDS), filed on December 11, 2023 is in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosed therein has been considered by the Examiner. Priority Receipt is acknowledged of paper submitted under 35 U.S.C. 119(a)-(d) or under 35 U.S.C. 120, 121, 365(c), or 386(c) which has been placed of record in the file. Notation References to patents will be in the form of (C: L) where C is the column number and L is the line number. References to pre-grant patent publications will be to the paragraph number in the form of (¶ XXXX). Election/Restrictions Applicant’s election without traverse of claims 1-9 in the reply filed on March 10 2026 is acknowledged. Claims 10-20 withdrawn from further consideration pursuant to 37 CFR 1.142(b) as being drawn to a nonelected invention, there being no allowable generic or linking claim. Claim Rejections - 35 USC § 103 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claims 1-3 and 5 are rejected under 35 U.S.C. 103 as being unpatentable over Lee (US 2017/0373088 A1; hereinafter “Lee”). Regarding claim 1, Lee teaches a semiconductor memory device (Fig.8) comprising: a stacked body in which a plurality of conductive layers and a plurality of insulating layers are alternately stacked one by one (42-56; Fig.8B; alternative layers can be made of the first material C conductive layer and second material D insulative material; ¶ 0071) a stepped portion in which the plurality of conductive layers is processed into a stepped shape (layers 41-56 are step structure; Fig.8B); and a plurality of portions (71; Fig. 8B; ¶ 0078) that extends in the stacked body in a stacking direction of the stacked body (Stacked on Y-axis; Fig. 8B) and a first direction (X-direction parallel to the top surface of the substrate 60; Fig. 8B) intersecting the stacking direction (Y-axis) and divides the stacked body and the stepped portion of the stacked body in a second direction (Z-axis) intersecting the stacking direction and the first direction (71 divides the stacked Portions ST into multiple regions), wherein the stepped portion includes first to third regions (R1-R3; annotated Fig.8B attached below) that are divided by the plurality of portions (71) and are adjacent in an order of the first to third regions in the second direction (Z-axis), and PNG media_image1.png 423 874 media_image1.png Greyscale when viewed in a cross section along the second direction (Z-axis), each of the first to third regions has a plurality of terrace surfaces arrayed in the second direction and having different height positions (Each of R1 and R2 has a terrace level as annotated by the dotted line and R3 has a terrace surface that is annotated by the solid line above the dotted line, Fig.8B attached above), in the first and second regions (R1 and R2; Fig.8B), the height positions of the plurality of terrace surfaces are arranged in line-symmetry with respect to a plate-like portion dividing the first and second regions among the plurality of portions (R1 and R2 are symmetrical with respect to line 71 in which layers 41-44 have the same height), and in the second and third regions, the height positions of the plurality of terrace surfaces are arranged in line-asymmetry with respect to a portion dividing the second and third regions among the plurality of plate-like portions (R2 and R3 are asymmetrical with respect to line 71 in which layers 41-47 have different heights and etched differently). Lee does not explicit state a plurality of plate-like portions that extends in the stacked body direction. However, Lee teaches the at the insulting layer (71; Fig.8B) extends in the stacked body direction (Z-axis) and the insulating layer (71) have thickness, width and length and can be treated like a plate. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filling date of the invention, was to recognize that the insulation layer in the device of Lee can be a plate-like portion because the length of the insulation layer is bigger than the width of the insulation layer and looks like a line. Regarding claim 2, Lee teaches wherein the stepped portion further includes a fourth region (R4; annotated in the attached figure of Fig.8B below) that is divided by the plurality of plate-like portions (71) and is adjacent to the third region (R3) on an opposite side of the second region (R2), and PNG media_image2.png 423 874 media_image2.png Greyscale when viewed in a cross section along the second direction (Z-axis), the fourth region (R4) has a plurality of terrace surfaces arrayed in the second direction and having different height positions (R4 has different terrace that is arranged than R3; can be shown in the top dotted line), and in the third (R3) and fourth (R4) regions, the height positions of the plurality of terrace surfaces are arranged in line-asymmetry with respect to a plate-like portion dividing the third and fourth regions among the plurality of plate-like portions (R3 and R4 each have layers of 41-56 in which height of the terrace surfaces are asymmetric with respect to 71). Regarding claim 3, Lee teaches wherein the stepped portion further includes a fifth region (R4; annotated in the attached figure of Fig.8B below) that is divided by the plurality of plate-like portions (71) and is adjacent to the fourth region (R4) on an opposite side of the third region (R3), and PNG media_image3.png 423 874 media_image3.png Greyscale when viewed in a cross section along the second direction (Z-axis), the fifth region (R5) has a plurality of terrace surfaces (polarity of terrace surfaces annotated by the dotted and solid lines) arrayed in the second direction and having different height positions (different height positions), and in the fourth (R4) and fifth regions (R5), the height positions of the plurality of terrace surfaces are arranged in line-symmetry with respect to a plate-like portion (71) dividing the fourth and fifth regions among the plurality of plate-like portions (the height of the terrace surfaces of R4 and R5 are symmetric with respected to 71 as shown in the attached image of claim 3). Regarding claim 5, Lee teaches when viewed in the cross section along the second direction, each of the first to fifth regions (R1-R5) has three terrace surfaces in which conductive layers continuous in the stacking direction among the plurality of conductive layers serve as the terrace surfaces (the conductive layers (i.e. 41 and 43; Fig.8B) each serves as a terrace surface in each of R1-R5; Fig.8B). Allowable Subject Matter Claims 4 and 6-9 objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. Claims 4 only be allowed if the dependency is followed and ALL THE LIMITATIONS OF CLAIMS 3 AND 2 are also incorporated to claim 1. Claims 6-9 follows the same interpretation of claim 4. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to Mounir S Amer whose telephone number is (571)270-3683. The examiner can normally be reached Monday-Friday 9:00-5:30. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Eva Montalvo can be reached at (571) 270-3829. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /Mounir S Amer/Primary Examiner, Art Unit 2818
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Prosecution Timeline

Dec 11, 2023
Application Filed
Mar 21, 2026
Non-Final Rejection — §103 (current)

Precedent Cases

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Study what changed to get past this examiner. Based on 5 most recent grants.

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Prosecution Projections

1-2
Expected OA Rounds
88%
Grant Probability
97%
With Interview (+8.6%)
2y 2m
Median Time to Grant
Low
PTA Risk
Based on 602 resolved cases by this examiner. Grant probability derived from career allow rate.

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