DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically teaches d as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-6, 8-16, 19-20 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. US 20220130793 A1 in view of PARK US 20220059473 A1
Regarding claim 1, KANG teaches,
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A semiconductor package (FIG. 14), comprising:
a package substrate (11, para [0062]);
a first spacer chip (23, para [0062]) and a second spacer chip (22, para [0062]) attached to an upper surface of the package substrate, the first and second spacer chips being spaced apart from each other (as seen);
a first semiconductor chip (21, para [0062]) on the upper surface of the package substrate and between the first and second spacer chips (as seen);
a plurality of second semiconductor chips (including T1 & T2 comprising memory chips 31 to 38 and 51 to 58, para [0015]) sequentially stacked on the first and second spacer chips by adhesive films (including 72 & 73, para [0015]) to cover the first semiconductor chip;
and a sealing member (encapsulation 91, para [0015]) on the package substrate and covering the first and second spacer chips, the first semiconductor chip, and the plurality of second semiconductor chips (as seen),
wherein at least a portion of the first spacer chip (23) protrudes from one side of a lowermost second semiconductor chip (51) among the plurality of second semiconductor chips.But KANG does not explicitly teach,
and wherein the first spacer chip includes a groove at an upper surface of the protruded portion.
Meanwhile , PARK teaches,
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the first spacer chip (220S2, para [0060], FIG. 10) includes a groove (G) and the groove G provide a non-flat bonding interface to enhance bonding strength between the non-conductive adhesive layer 317 and the spacer chip 220 (para [0033]).
Furthermore, FIG. 6B shows the groove G/G’ may include groove G1 & G2 (para [0047], FIG. 6B).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify KANG such that the first spacer chip (23/220S2) includes a groove at its upper surface such that the groove (e.g. G1/G2) is formed at its protruding portion, according to teaching of KANG, in order to enhance bonding between the adhesive film 72 and the first spacer chip 23 (as well as enhance bonding between the sealing member 91 and the first spacer chips 23), as taught by PARK.
Regarding claim 2, KANG & PARK teaches the semiconductor package of claim 1 and further teaches , wherein the lowermost second semiconductor chip (51) is attached to the first spacer chip (23) by a first adhesive film (72) among the adhesive films,
and the first adhesive film at least partially fills the groove of the first spacer chip (the first adhesive film (72/317, APRK FIG. 10) obviously would have spilled into the groove G at its protruding portion while bonding the first spacer chip 23 with the second semiconductor chip 51).
Regarding claim 3, KANG & PARK teaches the semiconductor package of claim 2 and further teaches ,wherein remaining chips (52 to 58, KANG FIG. 14) of the plurality of second semiconductor chips are sequentially attached to the lowermost second semiconductor chip (51) by second adhesive films (73) among the adhesive films.
Regarding claim 4, KANG & PARK teaches the semiconductor package of claim 1 and further teaches , wherein the groove extends in a first direction (X ) along a peripheral region (top peripheral region) of the first spacer chip (23/220S2, PARK Fig. 10).
Regarding claim 5, KANG & PARK teaches the semiconductor package of claim 4 but does not explicitly teach, further comprising: a second groove extending across the groove.
However, it would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to form a second grove across the first grove in direction Z (such that first grove and second grove forms a cross + shape), in order to further enhance bonding between the adhesive film 72 and the spacer chip 23 and further enhance bonding between the sealing member 91 and the spacer chip 23)
Regarding claim 6, KANG & PARK teaches the semiconductor package of claim 1 and further teaches ,wherein a depth of the groove is within a range of 10 um to 80 um , and a width of the groove is within a range of 20 um to 120 um
But PARK additionally teaches,
a width (w) of each of the groove G may have a range of 15 μm to 30 μm ( para [0037]).
However, it is to be noted here that the claimed width range of 20 μm to 120 μm and the width range 15 μm to 30 μm taught by PARK overlaps each other. In the case where the claimed ranges “overlap or lie inside ranges teaches d by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
But KANG & PARK still does not explicitly teach, wherein a depth of the groove is within a range of 10 um to 80 um.
PARK additionally teaches, depth (d) of each of the groove’s G may be in a range from 0.5 μm to 3 μm (para [0037]).
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the depth of groove G with routine experiment and optimization (such that a depth of the groove is within a range of 10 um to 80 um), according to the teaching of PARK, since the depth of the groove is important, in order to enhance bonding between the adhesive film 72 and the first spacer chip 23/220S2, as taught by PARK (see para [0033]).In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 8, KANG & PARK teaches the semiconductor package of claim 1 but does not explicitly teach, further comprising: a third spacer chip and a fourth spacer chip attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other , the first semiconductor chip being interposed between the third and fourth spacer chips , wherein the third and fourth spacer chips are arranged in a first direction that is perpendicular to a second direction in which the first and second spacer chips are arranged.
But PARK further teaches,
a first spacer chip (220S2, Figs. 9-10) and a second spacer chip (220S1) attached to the upper surface of the package substrate (101), the first and second spacer chips being spaced apart from each other (in direction X) , a first semiconductor chip (210, para [0024]) on the upper surface of the package substrate and between the first and second spacer chips (as seen);
a third spacer chip (230S1, FIG. 9) and a fourth spacer chip (230S2)attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other ,the first semiconductor chip being interposed between the third and fourth spacer chips (FIG. 9), wherein the third and fourth spacer chips are arranged in a first direction (Z, see annotated above) that is perpendicular to a second direction (X) in which the first and second spacer chips are arranged.
spacer chips 220S1, 220S2, 230S1, and 230S2 are employed to provide a lower structure that stably supports the upper semiconductor chip 300 (para [0059]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify KANG such that a third spacer chip (230S1) and a fourth spacer chip (230S2) attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction (Z), the first semiconductor chip (21/210) being interposed between the third and fourth spacer chips, wherein the third and fourth spacer chips are arranged in a first direction (Z) that is perpendicular to a second direction (X) in which the first and second spacer chips are arranged, according to teaching of PARK, in order to stably support the upper second semiconductor chip, as taught by PARK above.
Regarding claim 9, KANG & PARK teaches the semiconductor package of claim 8 and further teaches , wherein the plurality of second semiconductor chips (T1 & T2) are sequentially offset aligned in the first direction on the third and fourth spacer chips (T1 & T2 obviously would be sequentially offset aligned in direction Z on the third and fourth spacer chips 230S1, 230S2 in view of Fig. 9 of PARK and Fig. 14 of Kang).
Regarding claim 10, KANG & PARK teaches the semiconductor package of claim 1 and further teaches ,wherein the adhesive films include a die attach film (72 may include DAF (die attach film), KANG, para [0033])
Regarding claim 11, KANG teaches,
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A semiconductor package (FIG. 14 as annotated above), comprising:
a package substrate (11, para [0062]) extending in a first direction (Z) ;
a first semiconductor chip (21, para [0062]) on an upper surface of the package substrate;
a first spacer chip (23, para [0062]) and a second spacer chip (22, para [0062]) attached to the upper surface of the package substrate, the first and second spacer chips being spaced apart from each other in a second direction (X) perpendicular to the first direction, the first semiconductor chip being interposed between the first and second spacer chips (as seen);
….……a plurality of second semiconductor chips (including T1 & T2 comprising memory chips 31 to 38 and 51 to 58, para [0015]) sequentially stacked on the first, second, third and fourth spacer chips by adhesive films (including 72 & 73, para [0015]) to cover the first semiconductor chip;
and a sealing member (91, para [0015]) on the package substrate and covering the first, second, third and fourth spacer chips, the first semiconductor chip and the plurality of second semiconductor chips,
wherein at least a portion of the first spacer chip (23) protrudes from one side of a lowermost second semiconductor chip (51) among the plurality of second semiconductor chips…..
But KANG does not explicitly teach,
……...a third spacer chip and a fourth spacer chip attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction, the first semiconductor chip being interposed between the third and fourth spacer chips;
……and wherein the first spacer chip includes a groove at an upper surface of the protruded portion.
Meanwhile, PARK teaches,
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a first spacer chip (220S2, Figs. 9-10) and a second spacer chip (220S1) attached to the upper surface of the package substrate (101), the first and second spacer chips being spaced apart from each other in a second direction (X, FIG. 10) perpendicular to the first direction (Z), the first semiconductor chip being interposed between the first and second spacer chips (as seen);
a third spacer chip (230S1, see FIG. 9 as annotated above) and a fourth spacer chip (230S2) attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction (Z), the first semiconductor chip (210) being interposed between the third and fourth spacer chips (FIG. 9)
spacer chips 220S1, 220S2, 230S1, and 230S2 are employed to provide a lower structure that stably supports the upper semiconductor chip 300 (para [0059]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify KANG such that a third spacer chip (230S1, FIG. 9 as annotated above) and a fourth spacer chip (230S2) attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction (Z), the first semiconductor chip (21/210) being interposed between the third and fourth spacer chips, according to teaching of PARK, in order to provide a lower structure that stably support the upper second semiconductor chips (T1 & T2), as taught by PARK above.
KANG & PARK still does not explicitly teach,
……and wherein the first spacer chip includes a groove at an upper surface of the protruded portion.
PARK further teaches,
and wherein the first spacer chip (220S2, FIG. 10) includes a groove (G) to provide a non-flat bonding interface to enhance bonding strength between the non-conductive adhesive layer 317 and the spacer chip 220 (para [0033]).
And FIG. 6B shows the groove may include groove G/G’ including G1 & G2 (para [0047], FIG. 6B).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify KANG such that the first spacer chip (23/220S2) includes a groove at its upper surface such that the groove G1/G2 is formed at its protruding portion, according to teaching of KANG, in order to enhance bonding strength between the adhesive film 72 and the first spacer chip 23 (as well as enhance bonding between the sealing member 91 and the first spacer chips 23), as taught by PARK above.
Regarding claim 12, KANG & PARK teaches the semiconductor package of claim 11 and further teaches, wherein the lowermost second semiconductor chip (51) is attached to the first spacer chip (23) by a first adhesive film (72) among the adhesive films, and the first adhesive film at least partially fills the groove of the first spacer chip (adhesive film 72 would have obviously spilled into the groove G of 23 while bonding the first spacer chip 23 with the second semiconductor chip 51 with adhesive film 72 in combined device).
Regarding claim 13, KANG & PARK teaches the semiconductor package of claim 12 and KANG further teaches , wherein remaining chips (52 to 58, KANG FIG. 14) of the plurality of second semiconductor chips are sequentially attached to the lowermost second semiconductor chip (51) by second adhesive films (73, para [0015]) among the adhesive films.
Regarding claim 14, KANG & PARK teaches the semiconductor package of claim 11 and further teaches, wherein the groove extends in the first direction (X) along a peripheral region (top peripheral region) of the first spacer chip (23/220S2, PARK Fig. 10).
Regarding claim 15, KANG & PARK teaches the semiconductor package of claim 14 but does not explicitly teach, further comprising: a second groove extending across the groove.
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to form a second grove across the first grove in direction Z (such that first grove and second grove forms a cross + shape), in order to further enhance bonding between the adhesive film 72 and the spacer chip 23 and further enhance bonding between the sealing member 91 and the spacer chip 23.
Regarding claim 16, KANG & PARK teaches the semiconductor package of claim 11 and further teaches , wherein a depth of the groove is within a range of 10 um to 80 um, and a width of the groove is within a range of 20 um to 120 um.
But PARK additionally teaches,
a width (w) of each of the grooves G may have a range of 15 μm to 30 μm ( para [0037]).
However, it is to be noted here that the claimed width range of 20 um to 120 um and the width range 15 μm to 30 μm taught by PARK overlaps each other. In the case where the claimed ranges “overlap or lie inside ranges teaches d by the prior art” a prima facie case of obviousness exists. In re Wertheim, 541 F.2d 257, 191 USPQ 90 (CCPA 1976); In re Woodruff, 919 F.2d 1575, 16 USPQ2d 1934 (Fed. Cir. 1990).
But KANG & PARK still does not explicitly teach, wherein a depth of the groove is within a range of 10 um to 80 um.
PARK additionally teaches, depth (d) of each of the groove’s G may be in a range from 0.5 μm to 3 μm (para [0037])
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the depth of groove G, with routine experiment and optimization (such that a depth of the groove is within a range of 10 um to 80 um), according to the teaching of PARK, since the depth of the groove is important, in order to enhance bonding strength between the adhesive film 72 and the spacer chip 23, as taught by PARK (see para [0033]).. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 18, KANG & PARK teaches the semiconductor package of claim 11 and further teaches, wherein the plurality of second semiconductor chips are sequentially offset aligned in the first direction (T1 & T2 obviously would be sequentially offset aligned in direction Z on the third and fourth spacer chips 230S1, 230S2 in view of Fig. 9 of PARK and Fig. 14 of Kang).
Regarding claim 19, KANG & PARK teaches the semiconductor package of claim 11 but does not explicitly teach, wherein at least one of the first, second, third, and fourth spacer chips includes a silicon material.
But KANG additionally teaches, 22 and 23 are semiconductor chip (para [0062]) but is silent about the material used to form the chip.
But, PARK further teaches, the spacer chip 220S may include a silicon (Si) substrate (para [0032])
Thus, it would have been obvious to try by one of ordinary skill in the art before the effective filing date of the claimed invention to form the first, second, third, and fourth spacer chips with a silicon substrate, according to the teaching of PARK, in order to form the spacer chips as a semiconductor chip, since it has been held that choosing from a finite number of identified, predictable solutions such spacer chip includes silicon substrate, with a reasonable expectation of success is obvious. KSR Int'l v. Teleflex Inc., 127 S.Ct. 1727 (2007).
Regarding claim 20, KANG & PARK teaches,
A semiconductor package (FIG. 14 as annotated above), comprising:
a package substrate (11, para [0062]) extending in a first direction (Z), having an upper surface and a lower surface opposite to the upper surface, and having a plurality of substrate pads (15, para [0017]) on the upper surface;
a first semiconductor chip (21, para [0062]) on the upper surface of the package substrate;
a first spacer chip (23, para [0062]) and a second spacer chip (22, para [0062]) attached to the upper surface of the package substrate, the first and second spacer chips being spaced apart from each other in a second direction (X) perpendicular to the first direction, the first semiconductor chip being interposed between the first and second spacer chips (as seen);
…….a plurality of second semiconductor chips (including T1 & T2 comprising memory chips 31 to 38 and 51 to 58, para [0015]) sequentially stacked on the first, second, third and fourth spacer chips by adhesive films (including 72 & 73, para [0015]) to cover the first semiconductor chip;
conductive connection members (83, para [0015]) electrically connecting chip pads (85, para [0019]) of the plurality of second semiconductor chips to the substrate pads (via chip 23 and conductive connection 81), respectively;
and a sealing member (91, para [0015]) on the package substrate and covering the first, second, third and fourth spacer chips, the first semiconductor chip, and the plurality of second semiconductor chips,
wherein at least a portion of the first spacer chip (23) protrudes from one side of a lowermost second semiconductor chip (51) among the plurality of second semiconductor chips………
BUT KANG does not explicitly teach,
a third spacer chip and a fourth spacer chip attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction, the first semiconductor chip being interposed between the third and fourth spacer chips;
wherein the first spacer chip includes a groove having a depth and a width at an upper surface of the protruded portion,
and wherein the adhesive film on a bottom surface of the lowermost second semiconductor chip at least partially fills the groove of the first spacer chip.
Meanwhile, PARK teaches,
a first spacer chip (220S2, Figs. 9-10) and a second spacer chip (220S1) attached to the upper surface of the package substrate (101), the first and second spacer chips being spaced apart from each other in a second direction (X, FIG. 10 above) perpendicular to the first direction (Z), the first semiconductor chip being interposed between the first and second spacer chips (as seen);
a third spacer chip (230S1, see FIG. 9 annotated above) and a fourth spacer chip (230S2) attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction (Z), the first semiconductor chip (210) being interposed between the third and fourth spacer chips (FIG. 9)
spacer chips 220S1, 220S2, 230S1, and 230S2 are employed to provide a lower structure that stably supports the upper semiconductor chip 300 (para [0059]).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention, to modify KANG such that a third spacer chip (230S1) and a fourth spacer chip (230S2) attached to the upper surface of the package substrate, the third and fourth spacer chips being spaced apart from each other in the first direction (Z), the first semiconductor chip (21/210) being interposed between the third and fourth spacer chips, according to teaching of PARK, in order to stably support the second semiconductor chips (T1 & T2), as taught by PARK above.
KANG & PARK still does not explicitly teach,
wherein the first spacer chip includes a groove having a depth and a width at an upper surface of the protruded portion,
and wherein the adhesive film on a bottom surface of the lowermost second semiconductor chip at least partially fills the groove of the first spacer chip.
PARK further teaches,
and wherein the first spacer chip (220S2, para [0060], FIG. 10) includes a groove (G) to provide a non-flat bonding interface to enhance bonding strength between the non-conductive adhesive layer 317 and the spacer chip 220 (para [0033]).
And FIG. 6B shows the groove G/G’ including G1 & G2 (para [0047], FIG. 6B).
It would have been obvious to one of ordinary skill in art before the effective filing date of the claimed invention to modify KANG such that the first spacer chip (23/220S2) includes a groove having a depth (depth d of G, para [0037]) and a width (width w of G, para [0037]) at an upper surface of the protruded portion according to teaching of KANG such that the adhesive film (72/317) on a bottom surface of the lowermost second semiconductor chip (51) at least partially fills the groove of the first spacer chip (adhesive film 72 would have obviously spilled into the groove G at the protruding portion while bonding the first spacer chip 23 with the second semiconductor chip 51 with adhesive film 72/317), in order to enhance bonding strength between the adhesive film 91 and the first spacer chip 23 (as well as enhance bonding between the sealing member 91 and the first spacer chips 23), as taught by PARK above.
Claims 7 & 17 are rejected under 35 U.S.C. 103 as being unpatentable over KANG et al. in view of PARK and further in view of CHUNG et al. (US 2022/0068887 A1)
Regarding claim 7, KANG & PARK teaches the semiconductor package of claim 1 but does not explicitly teach, wherein the first spacer chip has a thickness of 40 um to 120 um.
Meanwhile, CHUNG teaches,
a thickness of a semiconductor chip is within a range of 40 μm to 60 μm (para [0005])
the number, thickness, area, arrangements, etc. of the spacer chip 400 may be modified, e.g., adjusted, in order to prevent warpage of the lower package structure 200 including the semiconductor chip 300 and the spacer chip 400 ( para [0068])
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the thickness of the first spacer chip 23 with routine experiment and optimization (such that the first spacer chip has a thickness of 40 um to 120 um), according to the teaching of CHUNG, since the thickness of the spacer is important, in order to prevent warpage of the lower package structure including the first semiconductor chip and the spacer chip , as taught by CHUNG. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Regarding claim 17, KANG & PARK teaches the semiconductor package of claim 11 but does not explicitly teach, wherein the first spacer chip has a thickness of 40 um to 120 um.
Meanwhile, CHUNG teaches,
a thickness of a semiconductor chip is within a range of 40 μm to 60 μm (para [0005])
the number, thickness, area, arrangements, etc. of the spacer chip 400 may be modified, e.g., adjusted, in order to prevent warpage of the lower package structure 200 including the semiconductor chip 300 and the spacer chip 400 ( para [0068])
Thus, it would have been obvious to one of the ordinary skill in the art before the effective filing date of the claimed invention to vary the thickness of the first spacer chip 23 with routine experiment and optimization (such that the first spacer chip has a thickness of 40 um to 120 um), according to the teaching of CHUNG, since the thickness of the spacer is important, in order to prevent warpage of the lower package structure including the first semiconductor chip and the spacer chip , as taught by CHUNG. In re Woodruff, 16 USPQ2d 1935, 1937 (Fed. Cir. 1990). See also In re Boesch, 205 USPQ 215 (CCPA) (discovery of optimum value of result effective variable in known process is ordinarily within skill of art) and In re Aller, 105 USPQ 233 (CCPA 1955) (selection of optimum ranges within prior art general conditions is obvious).
Conclusion
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/K.A.R/Examiner, Art Unit 2813
/STEVEN B GAUTHIER/Supervisory Patent Examiner, Art Unit 2813