DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-5, 8-11, 13-17, and 19-20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by US Patent Application Publication Number 2019/0391761 to Brief et al. (“Brief”).
In reference to Claim 1, Brief discloses an apparatus, comprising: a memory device (See Figure 1 Number 115); and a controller external to the memory device and coupled with the memory device (See Figure 1 Number 113 and Paragraph 24), wherein the controller is configured to cause the apparatus to: receive, from a host device (See Figure 1 Number 102), a first request message for a recovery configuration associated with power recovery (See Paragraphs 40-41) of a peripheral of the memory device (See Figure 1 Number 118); and transmit, to the host device based at least in part on the first request message, a first response message comprising the recovery configuration associated with the power recovery of the peripheral of the memory device, the recovery configuration comprising parametric data associated with the peripheral of the memory device to store at the host device (See Paragraphs 41 and 47 [in order to write back the parametric data from the host, the host must necessarily store the read parametric data]).
In reference to Claim 2, Brief discloses the limitations as applied to Claim 1 above. Brief further discloses that the controller is further configured to cause the apparatus to: operate the peripheral of the memory device in a power mode of a set of power modes based at least in part on the first request message, or the first response message, or a combination thereof (See Paragraphs 38-41).
In reference to Claim 3, Brief discloses the limitations as applied to Claim 1 above. Brief further discloses that the controller is further configured to cause the apparatus to: generate the recovery configuration comprising the parametric data associated with the peripheral of the memory device based at least in part on the first request message (See Paragraph 41).
In reference to Claim 4, Brief discloses the limitations as applied to Claim 2 above. Brief further discloses that the controller is further configured to cause the apparatus to: receive, from the host device, a second request message to operate the peripheral of the memory device in a power mode, the second request message indicating timing information to switch the peripheral of the memory device to the power mode (See Paragraph 38 [message instructs entry into a power mode at a timing following receipt]), and the second request message comprising a Start-Stop-Unit (SSU) request Universal Flash Storage (UFS) Protocol Information Unit (UPIU), wherein the controller is configured to cause the apparatus to receive the first request message, or transmit the first response message, or a combination thereof, based at least in part on the second request message (See Paragraphs 7, 20, and 38).
In reference to Claim 5, Brief discloses the limitations as applied to Claim 4 above. Brief further discloses that the controller is further configured to cause the apparatus to: process one or more operations associated with the peripheral of the memory device based at least in part on the second request message; and operate the peripheral of the memory device in the power mode based at least in part on the one or more operations associated with the peripheral of the memory device (See Paragraphs 38 and 42).
In reference to Claim 8, Brief discloses the limitations as applied to Claim 1 above. Brief further discloses that the controller is further configured to cause the apparatus to: receive, from the host device, a second request message comprising the recovery configuration associated with the power recovery of the peripheral of the memory device (See Paragraphs 45-47); and operate the peripheral of the memory device in a first power mode by switching to the first power mode from a second power mode based at least in part on the second request message (See Paragraphs 47-48).
In reference to Claim 9, Brief discloses the limitations as applied to Claim 8 above. Brief further discloses that the controller is further configured to cause the apparatus to: reconfigure the peripheral of the memory device based at least in part on the second request message comprising the recovery configuration comprising the parametric data associated with the peripheral of the memory device and switching to the first power mode from the second power mode (See Paragraphs 47-48).
In reference to Claim 10, Brief discloses the limitations as applied to Claim 9 above. Brief further discloses that the controller is further configured to cause the apparatus to: transmit, to the host device, a second response message comprising an acknowledgment based at least in part on the second request message, wherein the controller is configured to cause the apparatus to operate the peripheral of the memory device in the first power mode by switching to the first power mode from the second power mode based at least in part on the second response message (See Paragraph 54).
In reference to Claim 11, Brief discloses the limitations as applied to Claim 10 above. Brief further discloses that the controller is further configured to cause the apparatus to: perform a boot operation for the power recovery of the peripheral of the memory device based at least in part on the second request message, or the second response message, or a combination thereof; and initialize a connection path between the peripheral of the memory device and the host device based at least in part on the boot operation (See Paragraph 48).
In reference to Claim 13, Brief discloses the limitations as applied to Claim 1 above. Brief further discloses that the recovery configuration comprising the parametric data is associated with a physical layer of the peripheral of the memory device, or a physical layer of a peripheral of the host device, or a combination thereof (See Paragraph 41 [flash tables are “associated” with the physical layers of the interfaces in accordance with the broadest reasonable interpretation of the term]).
In reference to Claim 14, Brief discloses the limitations as applied to Claim 1 above. Brief further discloses that the peripheral of the memory device comprises a peripheral memory (See Figure 1 Number 118) associated with one or more input/output (I/O) devices (See Figure 1 Number 112 [a memory that communicates through an I/O interface is “associated” with the I/O interface in accordance with the broadest reasonable interpretation of the term]).
In reference to Claim 15, Brief discloses an apparatus, comprising: a controller (See Figure 1 Number 103 and Paragraph 21) external to a memory device (See Figure 1 Numbers 111 and 115) and configured to couple with the memory device (See Figure 1), wherein the controller is configured to cause the apparatus to: transmit, to the memory device, a first request message for a recovery configuration associated with power recovery (See Paragraphs 40-41) of a peripheral of the memory device (See Figure 1 Number 118); and receive, from the memory device based at least in part on the first request message, a first response message comprising the recovery configuration associated with the power recovery of the peripheral of the memory device, the recovery configuration comprising parametric data associated with the peripheral of the memory device to store at the apparatus (See Paragraphs 41 and 47 [in order to write back the parametric data from the host, the host must necessarily store the read parametric data]).
In reference to Claim 16, Brief discloses the limitations as applied to Claim 15 above. Brief further discloses that the controller is further configured to cause the apparatus to: store the recovery configuration comprising the parametric data associated with the peripheral of the memory device based at least in part on the first response message (See Paragraphs 41 and 47 [in order to write back the parametric data from the host, the host must necessarily store the read parametric data]).
In reference to Claim 17, Brief discloses the limitations as applied to Claim 15 above. Brief further discloses that the controller is further configured to cause the apparatus to: transmit, to the memory device, a second request message to operate the peripheral of the memory device in a power mode, the second request message indicating timing information to switch the peripheral of the memory device to the power mode (See Paragraph 38 [message instructs entry into a power mode at a timing following receipt]), and the second request message comprising a Start-Stop-Unit (SSU) request Universal Flash Storage (UFS) Protocol Information Unit (UPIU),wherein the controller is configured to cause the apparatus to transmit the first request message, or receive the first response message, or a combination thereof, based at least in part on the second request message (See Paragraphs 7, 20, and 38).
In reference to Claim 19, Brief discloses the limitations as applied to Claim 15 above. Brief further discloses that the controller is further configured to cause the apparatus to: transmit, to the memory device, second request message comprising the recovery configuration associated with the power recovery of the peripheral of the memory device (See Paragraphs 45-47); and receive, from the memory device, a second response message comprising an acknowledgment based at least in part on the second request message (See Paragraph 54).
In reference to Claim 20, Brief discloses an apparatus, comprising: a memory device (See Figure 1 Number 115); and a controller external to the memory device and coupled with the memory device (See Figure 1 Number 113 and Paragraph 24), wherein the controller is configured to cause the apparatus to: receive, from a host device (See Figure 1 Number 102), a first request message for a recovery configuration associated with power recovery (See Paragraphs 40-41) of a peripheral of the memory device (See Figure 1 Number 118), the recovery configuration comprising parametric data associated with the peripheral of the memory device (See Paragraphs 41 and 47); transmit, to the host device, a first response message based at least in part on the first request message (See Paragraph 41); reconfigure the peripheral of the memory device based at least in part on the recovery configuration comprising the parametric data associated with the peripheral of the memory device (See Paragraphs 47-48); and operate the peripheral of the memory device in a power mode based at least in part on the first request message, or the first response message, or a combination thereof (See Paragraphs 38-41).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brief as applied to Claim 4 above, and further in view of US Patent Application Publication Number 2022/0043586 to Liang et al. (“Liang”).
In reference to Claim 7, Brief discloses the limitations as applied to Claim 4 above. Brief further discloses that the controller operates according the UFS Specification and uses UPIU SSU commands (See Paragraphs 7 and 20). However, Brief does not explicitly disclose that the controller is further configured to cause the apparatus to: enable a timer based at least in part on the timing information, wherein the controller is configured to cause the apparatus to operate the peripheral of the memory device in the power mode based at least in part on an expiration of the timer. Liang discloses a UFS Specification compliant system that uses UPIU SSU commands (See Paragraphs 15 and 46) and has a controller (See Figure 1 Number 120) that is configured to cause an apparatus to: enable a timer based at least in part on timing information, wherein the controller is configured to cause the apparatus to operate a device in the power mode based at least in part on an expiration of the timer (See Paragraph 46).
It would have been obvious to one of ordinary skill in the art to construct the UFS Specification compliant system of Brief using the UFS compliant power mode timer of Liang, resulting in the invention of Claim 7, in order to yield the predictable result of enabling entry into the reduced power mode when further commands are not received, such as when a command is lost due to fault (See Paragraph 46 of Liang).
Claim(s) 12 is/are rejected under 35 U.S.C. 103 as being unpatentable over Brief as applied to Claim 11 above, and further in view of US Patent Application Publication Number 2024/0094948 to Hamo et al. (“Hamo”).
In reference to Claim 12, Brief discloses the limitations as applied to Claim 11 above. Brief further discloses that the controller operates according the UFS Specification and uses UPIU SSU commands (See Paragraphs 7 and 20). However, Brief does not explicitly disclose that the controller is further configured to cause the apparatus to: receive, from the host device, a first ping message over the connection path between the peripheral of the memory device and the host device; and transmit, to the host device, a second ping message over the connection path between the peripheral of the memory device and the host device and based at least in part on the first ping message. Hamo discloses a UFS Specification compliant system that uses UPIU SSU commands (See Paragraphs 52 and 123) and has a controller (See Figure 1 Number 120) that is configured to receive, from a host device (See Figure 1 Number 130), a first ping message (See Paragraph 123) over a connection path between a connected device and the host device (See Figure 1 Number 150); and transmit, to the host device, a second ping message over the connection path between the connected device and the host device and based at least in part on the first ping message (See Paragraph 123).
It would have been obvious to one of ordinary skill in the art to construct the UFS Specification compliant system of Brief using the UFS compliant ping messages of Hamo, resulting in the invention of Claim 12, in order to yield the predictable result of complying with the UFS Specification and checking for a functional connection path between the host and the connected device (See Paragraphs 52-53 and 123 of Hamo).
Allowable Subject Matter
Claim(s) 6 and 18 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: Claim 6 is allowable because the prior art fails to disclose, either alone or in combination, all of the claimed limitations in the combinations as claimed. The most relevant prior art is Brief as applied in the above rejections. However, while Brief discloses that the controller is further configured to cause the apparatus to: transmit, to the host device, a second response message based at least in part on the second request message and the one or more operations associated with the peripheral of the memory device, the second response message indicating that the peripheral of the memory device is operating in the power mode, and the second response message comprising an SSU response UPIU (See Paragraph 52 [SSU Response (Good)]), such a second response message is sent after, and is caused by, the communication of the first request message and first response message. Thus Brief does not disclose that the controller is further configured to cause the apparatus to: transmit, to the host device, a second response message based at least in part on the second request message and the one or more operations associated with the peripheral of the memory device, the second response message indicating that the peripheral of the memory device is operating in the power mode, and the second response message comprising an SSU response UPIU, wherein the controller is configured to cause the apparatus to receive the first request message, or transmit the first response message, or a combination thereof, based at least in part on the second response message, in the combinations as claimed. Furthermore, such features would not have been obvious to one of ordinary skill in the art, as the device of Brief would be inoperable as the apparatus would be unable to retrieve/generate/transfer the parametric data if the peripheral of the memory device were already in the reduced power mode. Claim 18 is allowable for substantially similar reasons as Claim 6.
Drawings
The drawings were received on 14 May 2026. These drawings are acceptable.
Response to Arguments
Applicant's arguments filed 14 May 2026 have been fully considered but they are not persuasive.
Applicant has argued that the UTP engine of Brief is not a controller, as it does not control anything (See Pages 12-13). In response, the Examiner notes that, as is well known in the art, an “engine”, such as the UTP engine of Brief, is a type of specialized control unit. Brief discloses that the UTP engine 113 receives commands and data from and delivers responses and data to the UTP engine 105 of the UFS host controller (See Paragraph 24). It is thus a controller in accordance with the broadest reasonable interpretation of the term, as it is controlling the receipt of commands and data and the transmission of responses and data. In particular, the UTP engine 113 of Brief causes the apparatus to receive, from t host device, a first request message for a recovery configuration associated with power recovery of a peripheral of the memory device(See Paragraphs 40-41); and transmit, to the host device based at least in part on the first request message, a first response message comprising the recovery configuration associated with the power recovery of the peripheral of the memory device, the recovery configuration comprising parametric data associated with the peripheral of the memory device to store at the host device (See Paragraphs 41 and 47 [in order to write back the parametric data from the host, the host must necessarily store the read parametric data]). Thus, the UTP engine 113 of Brief performs all of the claimed control functionality.
Applicant has argued that the UTP engine of Brief is not external to the memory device, as both the volatile memory and the UTP engine reside within the storage device controller (See Page 13). In response, the Examiner notes that the broadest reasonable interpretation of the word “external” is “situated outside, apart, or beyond”. As clearly indicated in Figure 2, the UTP engine 113 is a separate component from the volatile memory 115, and is thus external to it in accordance with the broadest reasonable interpretation of the term. That the UTP engine 113 and the volatile memory 115 both may be part of another component is irrelevant as to their relationship to each other. It is noted that Figure 1 of Applicant’s disclosure clearly shows that the controller 115, which is “external” to the memory device 130, is part of the same memory system 110 as the memory device 130., and likewise Figure 2 of Applicant’s disclosure clearly shows that the controllers 215 and 230, which are “external” to the memory device 240, are part of the same memory system 210 as the memory device 240.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to THOMAS J CLEARY whose telephone number is (571)272-3624. The examiner can normally be reached Monday-Friday 8AM-5PM.
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/THOMAS J. CLEARY/Primary Examiner, Art Unit 2175
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