Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 1/6/2026 has been entered.
As per the instant application having Application No. 18/535,697, the examiner acknowledges the amendment filed on 12/4/2025 with subsequent request for continued examination (RCE) filed on 1/6/2026. Claims 1, 5-9 and 15 have been amended. Claims 1-20 are pending.
In the response to this Office action, the Examiner respectfully requests that support be shown for language added to any original claims on amendment and any new claims. That is, indicate support for newly added claim language by specifically pointing to page(s) and line numbers in the specification and/or drawing figure(s). This will assist the Examiner in prosecuting this application.
Examiner cites particular columns and line numbers in the references as applied to the claims below for the convenience of the applicant. Although the specified citations are representative of the teachings in the art and are applied to the specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested that, in preparing responses, the applicant fully consider the references in entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the examiner.
TERMINAL DISCLAIMER
The terminal disclaimer filed on 9/9/2025 disclaiming the terminal portion of any patent granted on this application which would extend beyond the expiration date of US 11,704,245 has been reviewed and is accepted. The terminal disclaimer has been recorded.
REJECTIONS NOT BASED ON PRIOR ART
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-8 and 15-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
As per claim 1, Applicant’s Specification does not provide support for “based on a memory transaction received via the second virtual channel that is a read directed to a location within the one or more of the first set of cache lines,…” since while the Specification describes different virtual channels in paragraphs 0063, 0064, 0066, 0124, 0126 and 0140 of (US 20240126457, corresponding to the instant application), the Specification does not describe that the read memory transaction directed to a location within the one or more of the first set of cache lines is received via the second virtual channel. Appropriate correction is required.
Dependent claims 2-8 are rejected for the reasons indicated above with respect to claim 1.
As per claim 15, Applicant’s Specification does not provide support for the limitations “based on a particular read transaction received via the second set of virtual channels that is directed to an address within the first set of ways, return a default value, wherein the default value is indicative of an address that is currently in use for cache operations” since while the Specification describes different virtual channels in paragraphs 0063, 0064, 0066, 0124, 0126 and 0140 of (US 20240126457, corresponding to the instant application), the Specification does not describe that the read memory transaction directed to an address within the first set of ways is received via the second set of virtual channels. Appropriate correction is required.
Additionally, Applicant’s Specification does not provide support for the limitations “return a default value, wherein the default value is indicative of an address that is currently in use for cache operations” since while the Specification (see US 20240126457, corresponding to the instant application) recites:
[0046] Cache controller circuit 201 is further configured to map cache lines 250b-257b in way 240b for use in the identified address region 215b. Address region 215b, as illustrated, includes a number of addresses that may be reserved for use with reallocated cache lines 250b-257b, and therefore, may not be mapped to any other memory locations or registers. When address region 215b is inactive, an attempt to access these addresses may result in generation of an exception, and/or return of a default value. Cache controller circuit 201 may further be configured to set respective real-time indicators in the cache tags corresponding to the particular cache lines 250b-257b. Such real-time indicators may denote that cache lines 250b-257b and, therefore, addresses in address region 215b, are associated with real-time transactions with higher priorities than bulk transactions. Accordingly, a memory accesses to any of the reallocated cache lines 250b-257b may be treated as real-time transactions even if a real-time transaction is not explicitly used in the memory access.
[0054] At time t1, memory transaction 350 is issued by an agent to access a value in address region 115b. Cache controller circuit 101 is configured, in response to memory transaction 350 being received after deallocating address region 115b, to generate error message 355. In some embodiments, error message 355 may be generated if memory transaction 350 includes a write to, or modification of, an address in address region 115b. Otherwise, if memory transaction 350 includes only read accesses to address region 115b, then cache controller circuit 101 may, instead of, or in addition to, generating error message 355, return a particular default value, such as all zero bits or all one bits, to the requesting agent. Generating error message 355 may be implemented using a variety of techniques. For example, error message 355 may be generated by asserting an exception signal that, in turn, causes a particular process to be executed by one or more processor cores in system 100. Generating error message 355 may include returning a particular value that indicates to the agent that issued memory transaction 350 that address region 115b has been deallocated.
[0088] The method, at block 850, further includes returning a default value in response to a read request for an address in address region 115b received after deallocating cache line 123 of cache memory circuit 105. As illustrated, if memory transaction 350 is directed to an address in address region 115b after deallocation request 345 has been performed, then a default value, indicative of an access to an inactive address, is returned to an agent that issued memory transaction 350.
it does not provide support for the default value is indicative of an address that is currently in use for cache operations as set forth in claim 15 as in the Specification, the default value is indicative of address regions that have been deallocated from one cache section to another, or to inactive addresses. Claim 15 should be amended in accordance with applicant’s Specification to first recite the deallocation of cache lines and then the read access directed to addresses of cache lines that have been deallocated, for which a default value is returned. Note portions of the set of cache ways dedicated to cache operations which have not been deallocated from the second set of cache ways used as directly-addressable random-access memory (RAM) would not return default values. Appropriate correction is required.
Dependent claims 16-20 are rejected for the reasons indicated above with respect to claim 15.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-8 and 15-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
As per claim 1, the limitations “in response to the particular request, convert the one or more of the second set of cache lines to cache memory by including the one or more of the second set of cache lines in cache operations; and based on a memory transaction received via the second virtual channel that is a read directed to a location within the one or more of the first set of cache lines, return a default value to fulfill the memory transaction, wherein the default value is indicative of a deallocated address” render claim 1 indefinite since claim 1 first states that the one or more first virtual channels are for access to the first of cache lines and the second virtual channel is for access to the second set of cache lines; thus, it is not clear how the second set of virtual channels access the one or more of the first set of cache lines. Additionally, as claimed, it appears the read access to the one or more of the first set of cache lines may be to any of the first set of cache lines, which may include cache lines which have not been deallocated and claim 1 states “return a default value to fulfill the memory transaction, wherein the default value is indicative of a deallocated address;” thus, claim 1 should clarify that the read is directed to addresses of the one or more of the second cache lines which have been deallocated from the directly addressable RAM and converted to first cache lines in cache memory. See paragraphs 0046, 0054 and 0088 of Applicant’s Specification. Appropriate correction/clarification is required.
Dependent claims 2-8 are rejected for the reasons indicated above with respect to claim 1.
As per claim 15, the limitations “based on a particular read transaction received via the second set of virtual channels that is directed to an address within the first set of ways, return a default value, wherein the default value is indicative of an address that is currently in use for cache operations” render the claim indefinite since claim 15 states memory transactions directed to addresses within the system memory circuit are received via first virtual channels and transactions directed to addresses in the second set of the plurality of ways are received via the second set of virtual channels. It is thus not clear how the read transaction directed to an address within the first set of ways is received via the second set of virtual channels. Additionally, the limitations “return a default value, wherein the default value is indicative of an address that is currently in use for cache operations” renders the claim unclear since it appears that cache lines being used for cache operations may be read and thus would not return a default value. Note Applicant’s Specification recites returning a default value for reads directed to cache lines that have been deallocated or inactive within a certain cache section. See pars. 0046, 0045 and 0088 of (US 2024/0126457). Appropriate correction/clarification is required.
Dependent claims 16-20 are rejected for the reasons indicated above with respect to claim 15.
ACKNOWLEDGEMENT OF ISSUES RAISED BY APPLICANT
Response to Amendment
The double patenting rejections in the non-final rejection mailed on 4/4/2025 have been overcome by filing of a terminal disclaimer on 9/9/2025 and have thus been withdrawn.
Applicant’s arguments filed on 12/4/2025 with respect to claims 8-14 are deemed persuasive. Thus, the rejection of claims 9-14 is herein withdrawn.
Applicant’s arguments filed on 12/4/2025 with respect to claims 1-8 and 15-20 have been fully considered but they are moot in view of the new grounds of rejection presented above.
As required by M.P.E.P. § 707.07(f), a response to these arguments appears below.
CLOSING COMMENTS
a. STATUS OF CLAIMS IN THE APPLICATION
a(1) CLAIMS REJECTED IN THE APPLICATION
Per the instant office action, claims 1-8 and 15-20 have received an action on the merits and are subject to a non-final rejection.
a(2) ALLOWABLE SUBJECT MATTER
Claims 9-14 are allowed.
The reasons for allowance of claim 9 are the following: In interpreting the pending claim(s), in light of the Specification and Applicant’s argument(s) filed on 12/4/2025, the Examiner finds the claimed invention to be patentably distinct from the prior art of record. The prior art of record, including the references noted above; neither anticipates, nor renders obvious the recited combination as a whole; including the limitations of “using, by a cache controller circuit, a first set of cache lines in a cache memory circuit to cache values stored in a higher-level memory circuit; using, by the cache controller circuit, a second set of cache lines in the cache memory circuit as a directly-addressable address region, wherein the second set of cache lines are associated with a particular address range within a system memory map, and wherein the second set of cache lines are not available for cache operations; receiving, by the cache controller circuit via a first set of virtual channels, memory transactions directed to addresses outside of the particular address range; and receiving, by the cache controller circuit via a second set of virtual channels, memory transactions directed to addresses within the particular address range; receiving, by the cache controller circuit, a request to deallocate one of the second set of cache lines; receiving, by the cache controller circuit, a memory transaction received via the second set of virtual channels, wherein the memory transaction is a read directed to a location within the particular address range corresponding to the deallocated cache line; and returning, by the cache controller circuit, a default value in response to the memory transaction, wherein the default value is indicative of a deallocated address.”
Dependent claims 10-14 are allowed for the reasons indicated with respect to claim 9 above.
b. DIRECTION OF FUTURE CORRESPONDENCES
Any inquiry concerning this communication or earlier communications from the examiner should be directed to YAIMA RIGOL whose telephone number is (571)272-1232. The examiner can normally be reached Monday-Friday 9:00AM-5:00PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Jared I. Rutz can be reached on (571) 272-5535. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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February 25, 2026
/YAIMA RIGOL/
Primary Examiner, Art Unit 2135