DETAILED ACTION
This office action is in response to the amendment filed on 12/30/2025.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant’s cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1, 3-6 and 12-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walter US20090108677 in view of Wu US 2011/0187336.
Regarding Claim 1, Walter teaches (Figures 5-6) a control circuit (205 and 209) for a bidirectional buck/boost converter (at 200), comprising: a buck/boost detection unit (209) configured to detect and output a mode of operation of the bidirectional buck/boost converter selected from buck mode and boost mode(par. 61-63); a voltage/current regulator unit (320-324 and 352) configured to receive the mode of operation output from the buck/boost detection unit (309) and configured to output a corresponding regulating signal based on the mode of operation (with 352); a PWM control unit (at 305, par. 61) configured to receive the voltage and/or current regulating signal from the voltage/current regulator unit and configured to output a PWM control signal based on the voltage and/or current regulating signal (par. 61-64); and a gate drive signal toggle unit (drive circuitry, par. 61) configured to receive the PWM control signal and the mode of operation (from 305) and configured to generate and output gate drive signals for driving switching operations of a plurality of switches (302-304) of the buck/boost converter based on the mode of operation and on the PWM control signal (par. 61-64 and 67-60). (For Example: Par. 56-71)
Walter does not teach further comprising a high-side/low-side driver unit configured to receive the gate drive signals output from the gate drive signal toggle unit and configured to amplify the gate drive signals and output the amplified gate drive signals to the switches; further comprising a plurality of current sensing units, in which each of the plurality of current sensing units senses current of one of the plurality of switches, and further comprising a current sense toggle unit configured to receive a current value output by each of the current sensing units, to receive the mode of operation, and to output the current value sensed by one of the current sensing units based on the mode of operation to the PWM control unit.
Wu teaches (Figures 2-4) further comprising a high-side/low-side driver unit (drivers at 330 and 332) configured to receive the gate drive signals output from the gate drive signal toggle unit (sent to 330 and 332) and configured to amplify the gate drive signals and output the amplified gate drive signals to the switches (HD and LD signals sent to switches); further comprising a plurality of current sensing units (306, Fig. 3), in which each of the plurality of current sensing units senses current of one of the plurality of switches (S1-S4), and further comprising a current sense toggle unit configured to receive a current value output by each of the current sensing units (with 344-348), to receive the mode of operation (at 344), and to output the current value sensed by one of the current sensing units based on the mode of operation (par.19-22) to the PWM control unit (350). (For Example: Par. 14-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include further comprising a high-side/low-side driver unit configured to receive the gate drive signals output from the gate drive signal toggle unit and configured to amplify the gate drive signals and output the amplified gate drive signals to the switches; further comprising a plurality of current sensing units, in which each of the plurality of current sensing units senses current of one of the plurality of switches, and further comprising a current sense toggle unit configured to receive a current value output by each of the current sensing units, to receive the mode of operation, and to output the current value sensed by one of the current sensing units based on the mode of operation to the PWM control unit, as taught by Wu to provide a dynamic line transient response.
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 3, Walter teaches (Figures 5-6) wherein the gate drive signal toggle unit (at 305, par. 61) is configured to output one drive signal for each of the plurality of switches (control signals for 302-304). (For Example: Par. 56-71)
Regarding Claims 4-5, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein, based on the mode of operation, the gate drive signal toggle unit is configured to generate a first drive signal by inverting the PWM control signal an odd number of times, and wherein the first drive signal is a synchronous rectification signal; and wherein the gate drive signal toggle unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times.
Wu teaches (Figures 2-4) wherein, based on the mode of operation, the gate drive signal toggle unit (with 330-338 and 362-370) is configured to generate a first drive signal by inverting the PWM control signal an odd number of times (from 350, with 362, par. 22), and wherein the first drive signal is a synchronous rectification signal (for LD Buck); and wherein the gate drive signal toggle (with 303-332) unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times (from 350 with 362 and 370, par. 22). (For Example: Par. 14-22)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include w wherein, based on the mode of operation, the gate drive signal toggle unit is configured to generate a first drive signal by inverting the PWM control signal an odd number of times, and wherein the first drive signal is a synchronous rectification signal; and wherein the gate drive signal toggle unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 6, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein the gate drive signal toggle unit comprises an on-time-duration limitation unit configured to limit a time-duration of at least one of the gate drive signals to a maximum threshold value, wherein the on-time-duration limitation unit is configured to set said gate drive signal to low when the maximum threshold value is reached.
Wu teaches (Figures 2-4) wherein the gate drive signal toggle unit (with 330-338 and 362-370) comprises an on-time-duration limitation unit (366 and 364) configured to limit a time-duration of at least one of the gate drive signals (with Max_D) to a maximum threshold value (Max Duty cycle, Fig. 4), wherein the on-time-duration limitation unit is configured to set said gate drive signal to low when the maximum threshold value is reached (e.g. with 366 inputting a signal to the reset terminal of 334, par. 22). (For Example: Par. 14-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include wherein the gate drive signal toggle unit comprises an on-time-duration limitation unit configured to limit a time-duration of at least one of the gate drive signals to a maximum threshold value, wherein the on-time-duration limitation unit is configured to set said gate drive signal to low when the maximum threshold value is reached, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 12, Walter teaches (Figures 5-6) the buck/boost conversion device (at fig. 5), comprising a bidirectional buck/boost converter and the control circuit according to claim 1 (with 400), wherein the control circuit is configured to control the buck/boost converter so as to buck a voltage input into the buck/boost conversion device (Fig. 5) or so as to boost a voltage output by the buck/boost conversion device (Figure 6). (For Example: Par. 56-71)
Regarding Claims 13 and 14, Walter teaches (Figures 5-6) wherein the gate drive signal toggle unit (at 305, par. 61) is configured to output one drive signal for each of the plurality of switches (control signals for 302-304). (For Example: Par. 56-71)
Walter does not teach wherein, based on the mode of operation, the gate drive signal toggle unit is configured to generate a first drive signal by inverting the PWM control signal an odd number of times, and wherein the first drive signal is a synchronous rectification signal; and wherein the gate drive signal toggle unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times.
Wu teaches (Figures 2-4) wherein, based on the mode of operation, the gate drive signal toggle unit (with 330-338 and 362-370) is configured to generate a first drive signal by inverting the PWM control signal an odd number of times (from 350, with 362, par. 22), and wherein the first drive signal is a synchronous rectification signal (for LD Buck); and wherein the gate drive signal toggle (with 303-332) unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times (from 350 with 362 and 370, par. 22). (For Example: Par. 14-22)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include w wherein, based on the mode of operation, the gate drive signal toggle unit is configured to generate a first drive signal by inverting the PWM control signal an odd number of times, and wherein the first drive signal is a synchronous rectification signal; and wherein the gate drive signal toggle unit is configured to generate a second drive signal by inverting the PWM control signal an even number of times, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 15, Walter teaches (Figures 5-6) wherein the buck/boost converter comprises a first switch and a second switch (302-304), the first switch is connected in series with an inductor (306), and wherein in the buck mode (Fig. 5): the second switch is driven with the synchronous rectification signal (304 on state) and the first switch is driven with the PWM control signal (at 305). (For Example: Par. 56-71)
Walter does not teach the even inverted PWM control signal.
Wu teaches (Figures 2-4) the even inverted PWM control signal (with signal from 370). (For Example: Par. 14-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include the even inverted PWM control signal, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 16, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein in the boost mode: the first switch is driven with the synchronous rectification signal, and the second switch is driven with the even inverted PWM control signal.
Wu teaches (Figures 2-4) wherein in the boost mode (boost): the first switch is driven with the synchronous rectification signal (S4 with LD boost), and the second switch (S3) is driven with the even inverted PWM control signal (from 370). (For Example: Par. 14-23)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include wherein in the boost mode: the first switch is driven with the synchronous rectification signal, and the second switch is driven with the even inverted PWM control signal, as taught by Wu to provide a dynamic line transient response.
Regarding Claim 17, Walter teaches (Figures 5-6) wherein the buck/boost conversion device is connected to a battery pack comprising at least one battery (e.g. 314). (For Example: Par. 56)
Claim(s) 2, 7 and 20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walter in view of Moussaoui US 2012/0049820.
Regarding Claims 2 and 20, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein the PWM control unit is a single-ended PWM controller which provides only one output signal.
Moussaoui teaches (Figure 2) wherein the PWM control unit is a single-ended PWM controller which provides only one output signal (from 106). (For Example: Par. 17-18)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include wherein the PWM control unit is a single-ended PWM controller which provides only one output signal as taught by Moussaoui to avoid the reverse transient inductor current during start-up, prevent system damage and make the design of the bidirectional DC-to-DC converter more robust.
Regarding Claim 7, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein the gate drive signal toggle unit comprises a dead-time generation unit configured to generate a dead-time between the gate drive signals.
Moussaoui teaches (Figure 2) wherein the gate drive signal toggle unit (controlling switches Q1-Q2) comprises a dead-time generation unit (see par. 17) configured to generate a dead-time between the gate drive signals. (For Example: Par. 17-18 and 30)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include wherein the gate drive signal toggle unit comprises a dead-time generation unit configured to generate a dead-time between the gate drive signals, as taught by Moussaoui to avoid the reverse transient inductor current during start-up, prevent system damage and make the design of the bidirectional DC-to-DC converter more robust.
Claim(s) 10-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walter in view of Zhao US 2012/0049820.
Regarding Claims 10-11, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach further comprising a buck/boost DC sensing unit configured to sense a current output during buck mode and/or current input during boost mode of the buck/boost converter and configured to feed the sensed current back to the voltage/current regulator unit; and wherein the voltage/current regulator unit is configured to regulate the voltage and/or current regulating signal based on the fed back sensed current.
Zhao teaches (Figures 6-8) further comprising a buck/boost DC sensing unit (11) configured to sense a current output during buck mode and/or current input during boost mode of the buck/boost converter (Fig. 6 with 11) and configured to feed the sensed current back to the voltage/current regulator unit (121 and 1223); and wherein the voltage/current regulator unit is configured to regulate the voltage and/or current regulating signal (output sent to 131 and 1221) based on the fed back sensed current (see fig. 6). (For Example: Par. 33-37)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include further comprising a buck/boost DC sensing unit configured to sense a current output during buck mode and/or current input during boost mode of the buck/boost converter and configured to feed the sensed current back to the voltage/current regulator unit; and wherein the voltage/current regulator unit is configured to regulate the voltage and/or current regulating signal based on the fed back sensed current, as taught by Zhao to reduce the power consumption of the system.
Claim(s) 18-19 is/are rejected under 35 U.S.C. 103 as being unpatentable over Walter in view of Davison US 2019/0356227.
Regarding Claims 18-19, Walter teaches (Figures 5-6) the control circuit.
Walter does not teach wherein the buck/boost conversion device further comprises a bidirectional blocking circuit; and wherein the bidirectional blocking circuit is a back-to-back ORing circuit.
Davison teaches (Figure 16) wherein the buck/boost conversion device (at fig. 16) further comprises a bidirectional blocking circuit (Fig. 16, protection switches at the input and output of the system); and wherein the bidirectional blocking circuit is a back-to-back ORing circuit (see fig. 16). (For Example: Par. 90)
It would have been obvious to one of ordinary skill in the art before the effective filling date of the claimed invention to modify the circuit of Walter to include wherein the buck/boost conversion device further comprises a bidirectional blocking circuit; and wherein the bidirectional blocking circuit is a back-to-back ORing circuit, as taught by Davison to provide protection to the system.
Response to Arguments
Applicant's arguments filed 12/30/2025 have been fully considered but they are not persuasive.
Applicant argue that “Moussaoui does not disclose how the PWM signal is generated, let alone the feature that the PWM control signal is generated based on the voltage and/or current regulating signal from the voltage/current regulator unit 4”. In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). The examiner would like to mentioned that how the PWM signal is generated is not mentioned in claim 2.
Applicant argued that “Moussaoui remains silent on the gate drive signal toggle unit and the gate drive signal toggle unit for further processing the PWM control signal, and thus fails to disclose the combination structure”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., further processing the PWM control signal) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Examiner’s Note: Claim 2 does not mentioned any limitations about further processing the PWM signal.
Applicant argued that “In contrast to the present invention, Wu does not disclose a gate drive signal toggle unit 8 and simultaneously a PWM control unit in accordance with claim 1”. However, as seen in claim 1 rejection the toggle unit and the PWM control unit limitations are covered by the Walters reference; it is not clear what the applicant meant by mentioning that the WU reference does not cover the above limitations.
Applicant argued that “On the contrary, in the present application, the PWM control unit is configured to output a PWM control signal based on the inputs from two components, that is, the input from the voltage/current regulator unit and the input from the current sense toggle unit”. In response to applicant's argument that the references fail to show certain features of the invention, it is noted that the features upon which applicant relies (i.e., a PWM control signal based on the inputs from two components) are not recited in the rejected claim(s). Although the claims are interpreted in light of the specification, limitations from the specification are not read into the claims. See In re Van Geuns, 988 F.2d 1181, 26 USPQ2d 1057 (Fed. Cir. 1993). Examiner’s Note: Claims 10-11 does not recite the above limitations.
Applicant argued that “Nowhere throughout Davison mentions anything about the synergistic interconnection between the PWM control unit, the gate drive signal toggle unit, the high-side/low-side driver unit, the plurality of current sensing units, and the current sense toggle unit as claimed in claim 1”. However, the Davison reference is used to shown the use of a back-to-back Oring Circuit not the interconnections between the different elements of the system.
Conclusion
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to GUSTAVO A ROSARIO-BENITEZ whose telephone number is (571)270-7888. The examiner can normally be reached M-F 9AM-5PM.
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/GUSTAVO A ROSARIO-BENITEZ/Primary Examiner, Art Unit 2838