DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claim s 1-25 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Sharma (US 20190267319 A1) . Regarding claim 1, Sharma teaches a semiconductor structure (170, Fig 3) comprising: a first transistor (140) stacked under (shown stacked under) a second transistor (100) ; and an interconnect layer (134) between (shown between) the first (140) and second (100) transistors, the interconnect layer (134) comprising a conductive via (112) and a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) . Regarding claim 2, Sharma teaches the structure of claim 1 and goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100) . Regarding claim 3, Sharma teaches the structure of claim 1 and goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) a first gate (116) of the first transistor (140) to a second gate (106) of the second transistor (100) . Regarding claim 4, Sharma teaches the structure of claim 1 and goes on to teach wherein the conductive via (112, Fig 3) connects (shown connected) the first transistor (140) to the conductive line (114A) . Regarding claim 5, Sharma teaches the structure of claim 4 and goes on to teach wherein another conductive via (114B, Fig 3) connects (shown connected) the second transistor (100) to the conductive line (114A) . Regarding claim 6, Sharma teaches the structure of claim 5 and goes on to teach wherein a space (134S: space for layer 134, Fig 3) between (shown between) the first transistor (140) and the second transistor (100) comprises the conductive via (112) , the conductive line (114A) , and the another conductive via (114B) . Regarding claim 7, Sharma teaches the structure of claim 1 and goes on to teach a first gate (116, Fig 3) of the first transistor (140) is connected (shown connected) to a conductive connection (114C) , another conductive via (114B) being connected (shown connected) to both the conductive connection (114C) and the conductive line (114A) , the conductive line (114A) being connected to the conductive via (112) ; and a second gate (106) of the second transistor (100) is connected (shown connected) to the conductive via (112) . Regarding claim 8, Sharma teaches the structure of claim 1 and goes on to teach wherein a first gate (116, Fig 3) of the first transistor (140) and a second gate (106) of the second transistor (100) are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]) . Regarding claim 9, Sharma teaches the structure of claim 1 and goes on to teach a first gate (116, Fig 3) of the first transistor (140) is directly under (shown directly under) a second gate (106) of the second transistor (100) ; or the first gate (116) of the first transistor (140) is diagonally offset under (shown diagonally offset and under) the second gate (106) of the second transistor (100) . Regarding claim 10, Sharma teaches the structure of claim 1 and goes on to teach a top tier (130, Fig 3) comprises the second transistor (100) and a fourth transistor (100B: when interconnect structure 150 is repeated to create a device, there would be additional fourth transistors in the top tier horizontally adjacent to 100; may include more than one TFT 100, [0050]) , the fourth transistor (100B) being laterally adjacent (laterally adjacent) to the second transistor (100) ; a bottom tier (138) comprises the first transistor (140) and a third transistor (140B: when interconnect structure 150 is repeated to create a device, there would be additional third transistors in the bottom tier horizontally adjacent to 140) , the first transistor (140) being directly below (shown directly below) the second transistor (100) , the third transistor (140B) being directly below (directly below) the fourth transistor (100B) ; and gates (116/106B) of the first (140) and fourth transistors (100B) are connected (shown connected) and other gates (106/116B) of the second (100) and third transistors (140B) are connected (shown connected) . Regarding claim 11, Sharma teaches a method comprising: providing a first transistor (140, Fig 3) ; and forming an interconnect layer (134) between (shown between) the first transistor (140) and a second transistor (100) , the first transistor (140) being under (shown under) the second transistor (100) , the interconnect layer (134) comprising a conductive via (112) and a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) . Regarding claim 12, Sharma teaches the method of claim 11 and goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100) . Regarding claim 13, Sharma teaches the method of claim 11 and goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) a first gate (116) of the first transistor (140) to a second gate (106) of the second transistor (100) . Regarding claim 14, Sharma teaches the method of claim 11 and goes on to teach wherein the conductive via (112, Fig 3) connects (shown connected) the first transistor (140) to the conductive line (114A) . Regarding claim 15, Sharma teaches the method of claim 14 and goes on to teach wherein another conductive via (114B, Fig 3) connects (shown connected) the second transistor (100) to the conductive line (114A) . Regarding claim 16, Sharma teaches the method of claim 15 and goes on to teach wherein a space (134S: space for layer 134, Fig 3) between (shown between) the first transistor (140) and the second transistor (100) comprises the conductive via (112) , the conductive line (114A) , and the another conductive via (114B) . Regarding claim 17, Sharma teaches the method of claim 11 and goes on to teach wherein: a first gate (116, Fig 3) of the first transistor (140) is connected (shown connected) to a conductive connection (114C) , another conductive via (114B) being connected (shown connected) to both the conductive connection (114C) and the conductive line (114A) , the conductive line (114A) being connected (shown connected) to the conductive via (112) ; and a second gate (106) of the second transistor (100) is connected (shown connected) to the conductive via (112) . Regarding claim 18, Sharma teaches the method of claim 11 and goes on to teach wherein a first gate (116, Fig 3) of the first transistor (140) and a second gate (106) of the second transistor (100) are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]) . Regarding claim 19, Sharma teaches a semiconductor structure (170, Fig 3) comprising: a first transistor (140) having a first gate (116) ; a second transistor (100) having a second gate (106) , the second transistor (100) being stacked above (shown stacked above) the first transistor (140) ; and an interconnect layer (134) formed between (shown between) the first (140) and second (100) transistors, the interconnect layer (134) electrically connecting (shown electrically connected) the first gate (116) and the second gate (106) . Regarding claim 20, Sharma teaches the structure of claim 19 and goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112) , a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) , and a second conductive via (114B) . Regarding claim 21, Sharma teaches the structure of claim 19 and goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112) that connects (shown connected) to the first gate (116) , a second conductive via (114B: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) that connects (shown connected) to the second gate (106) , and a conductive line (114A) connected (shown connected) to both the first (112) and second (114B) conductive vias. Regarding claim 22, Sharma teaches the structure of claim 19 and goes on to teach wherein: a conductive connection (114C: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) connects (shown connected) the first gate (116) to a first conductive via (112) ; and the interconnect layer (134) comprises the first conductive via (112) connected (shown connected) to the conductive connection (114C) , a second conductive via (114B) connected (shown connected) to the second gate (106) , and a conductive line (114A) connected (shown connected) to both the first (112) and second (114B) conductive vias. Regarding claim 23, Sharma teaches the structure of claim 19 and goes on to teach wherein the first (116, Fig 3) and second (106) gates are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]) . Regarding claim 24, Sharma teaches a method comprising: providing a first transistor (140, Fig 3) having a first gate (116) ; and providing a second transistor (100) having a second gate (106) , the second transistor (100) being stacked above (shown stacked above) the first transistor (140) , wherein an interconnect layer (134) is formed between (shown between) the first (140) and second (100) transistors, the interconnect layer (134) electrically connecting (shown electrically connected) the first gate (116) and the second gate (106) . Regarding claim 25, Sharma teaches the method of claim 24 and goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112) , a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) , and a second conductive via (114B) . Conclusion The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Li (US 20150061148 A1) - Stacked TFTs with gates electrically connected. Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT Jeremy D Watts whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (703)756-1055 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT M-R 8:00am-4:30pm, F 8:00-3pm EST . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Chad Dicke can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT (571) 270-7996 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /JEREMY DANIEL WATTS/ Examiner, Art Unit 2897 /CHAD M DICKE/ Supervisory Patent Examiner, Art Unit 2897