DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Amendment
The response filed 06/09/2026 is accepted, in which, claims 1-2, 11-12, 19-22, and 24-25 are amended. Claims 1, 11, 19, and 24 are independent with claims 1-25 awaiting an action on the merits as follows.
Response to Arguments
Applicant’s arguments with respect to claims 1, 11, 19, and 24 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claims 1-25 are rejected under 35 U.S.C. 103 as being unpatentable over Sharma (US 20190267319 A1), and further in view of Xie (US 20230335585 A1).
Regarding claim 1, Sharma teaches a semiconductor structure (170, Fig 3) comprising:
a first transistor (140) stacked under (shown stacked under) a second transistor (100); and
an interconnect layer (134) between (shown between) the first (140) and second (100) transistors,
the interconnect layer (134) comprising a conductive via (112) and a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106);
wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100).
Sharma fails to explicitly teach the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor.
However, Xie teaches wherein the conductive line horizontally extends (conductive line 2530 shown extending horizontally from first transistor, T1, on bottom left to directly above another first transistor, T1A, on the right, Fig 25; please see annotated figure below) from the first transistor to be disposed directly above (shown directly above) another first transistor (T1A, please see annotated figure below) stacked directly under (shown directly under second transistor, T2) the second transistor; and
wherein the conductive line is electrically isolated (conductive line 2530 is shown electrically isolated from the another first transistor, T1A; ) from the another first transistor (T1A).
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Sharma and Xie are considered analogous to the claimed invention because both are from the same field of endeavor of stacked semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Sharma with the features of Xie to create a structure wherein the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor that overcomes the challenges at nodes beyond 5 nm for final devices having cross-connections enabling the formation of latch circuits; forming comparable cross-connections for stacked CMOS structure compared to such cross connections easily formed for planar arrays of transistors, (Xie, [0047]).
Regarding claim 2, the combination of Sharma and Xie discloses the structure of claim 1. Sharma teaches the conductive line (114A, Fig 3), and the first transistor (140).
Xie goes on to teach a middle spacer layer (410, Fig 25) is above (shown above) the conductive line, the first transistor, and the another first transistor (T1A, please see annotated figure above).
Regarding claim 3, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) a first gate (116) of the first transistor (140) to a second gate (106) of the second transistor (100).
Regarding claim 4, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach wherein the conductive via (112, Fig 3) connects (shown connected) the first transistor (140) to the conductive line (114A).
Regarding claim 5, the combination of Sharma and Xie discloses the structure of claim 4. Sharma goes on to teach wherein another conductive via (114B, Fig 3) connects (shown connected) the second transistor (100) to the conductive line (114A).
Regarding claim 6, the combination of Sharma and Xie discloses the structure of claim 5. Sharma goes on to teach wherein a space (134S: space for layer 134, Fig 3) between (shown between) the first transistor (140) and the second transistor (100) comprises the conductive via (112), the conductive line (114A), and the another conductive via (114B).
Regarding claim 7, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach a first gate (116, Fig 3) of the first transistor (140) is connected (shown connected) to a conductive connection (114C),
another conductive via (114B) being connected (shown connected) to both the conductive connection (114C) and the conductive line (114A),
the conductive line (114A) being connected to the conductive via (112); and
a second gate (106) of the second transistor (100) is connected (shown connected) to the conductive via (112).
Regarding claim 8, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach wherein a first gate (116, Fig 3) of the first transistor (140) and a second gate (106) of the second transistor (100) are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]).
Regarding claim 9, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach a first gate (116, Fig 3) of the first transistor (140) is directly under (shown directly under) a second gate (106) of the second transistor (100); or
the first gate (116) of the first transistor (140) is diagonally offset under (shown diagonally offset and under) the second gate (106) of the second transistor (100).
Regarding claim 10, the combination of Sharma and Xie discloses the structure of claim 1. Sharma goes on to teach a top tier (130, Fig 3) comprises the second transistor (100) and a fourth transistor (100B: when interconnect structure 150 is repeated to create a device, there would be additional fourth transistors in the top tier horizontally adjacent to 100; may include more than one TFT 100, [0050]), the fourth transistor (100B) being laterally adjacent (laterally adjacent) to the second transistor (100);
a bottom tier (138) comprises the first transistor (140) and a third transistor (140B: when interconnect structure 150 is repeated to create a device, there would be additional third transistors in the bottom tier horizontally adjacent to 140), the first transistor (140) being directly below (shown directly below) the second transistor (100), the third transistor (140B) being directly below (directly below) the fourth transistor (100B); and
gates (116/106B) of the first (140) and fourth transistors (100B) are connected (shown connected) and other gates (106/116B) of the second (100) and third transistors (140B) are connected (shown connected).
Regarding claim 11, Sharma teaches a method comprising:
providing a first transistor (140, Fig 3); and
forming an interconnect layer (134) between (shown between) the first transistor (140) and a second transistor (100),
the first transistor (140) being under (shown under) the second transistor (100),
the interconnect layer (134) comprising a conductive via (112) and a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106);
wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100).
Sharma fails to explicitly teach the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor.
However, Xie teaches wherein the conductive line horizontally extends (conductive line 2530 shown extending horizontally from first transistor, T1, on bottom left to directly above another first transistor, T1A, on the right, Fig 25; please see annotated figure below) from the first transistor to be disposed directly above (shown directly above) another first transistor (T1A, please see annotated figure below) stacked directly under (shown directly under second transistor, T2) the second transistor; and
wherein the conductive line is electrically isolated (conductive line 2530 is shown electrically isolated from the another first transistor, T1A; ) from the another first transistor (T1A).
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Sharma and Xie are considered analogous to the claimed invention because both are from the same field of endeavor of stacked semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Sharma with the features of Xie to create a structure wherein the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor that overcomes the challenges at nodes beyond 5 nm for final devices having cross-connections enabling the formation of latch circuits; forming comparable cross-connections for stacked CMOS structure compared to such cross connections easily formed for planar arrays of transistors, (Xie, [0047]).
Regarding claim 12, the combination of Sharma and Xie discloses the method of claim 11. Sharma teaches the conductive line (114A, Fig 3), and the first transistor (140).
Xie goes on to teach a middle spacer layer (410, Fig 25) is above (shown above) the conductive line, the first transistor, and the another first transistor (T1A, please see annotated figure above).
Regarding claim 13, the combination of Sharma and Xie discloses the method of claim 11. Sharma goes on to teach wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) a first gate (116) of the first transistor (140) to a second gate (106) of the second transistor (100).
Regarding claim 14, the combination of Sharma and Xie discloses the method of claim 11. Sharma goes on to teach wherein the conductive via (112, Fig 3) connects (shown connected) the first transistor (140) to the conductive line (114A).
Regarding claim 15, the combination of Sharma and Xie discloses the method of claim 14. Sharma goes on to teach wherein another conductive via (114B, Fig 3) connects (shown connected) the second transistor (100) to the conductive line (114A).
Regarding claim 16, the combination of Sharma and Xie discloses the method of claim 15. Sharma goes on to teach wherein a space (134S: space for layer 134, Fig 3) between (shown between) the first transistor (140) and the second transistor (100) comprises the conductive via (112), the conductive line (114A), and the another conductive via (114B).
Regarding claim 17, the combination of Sharma and Xie discloses the method of claim 11. Sharma goes on to teach wherein:
a first gate (116, Fig 3) of the first transistor (140) is connected (shown connected) to a conductive connection (114C),
another conductive via (114B) being connected (shown connected) to both the conductive connection (114C) and the conductive line (114A),
the conductive line (114A) being connected (shown connected) to the conductive via (112); and
a second gate (106) of the second transistor (100) is connected (shown connected) to the conductive via (112).
Regarding claim 18, the combination of Sharma and Xie discloses the method of claim 11. Sharma goes on to teach wherein a first gate (116, Fig 3) of the first transistor (140) and a second gate (106) of the second transistor (100) are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]).
Regarding claim 19, Sharma teaches a semiconductor structure (170, Fig 3) comprising:
a first transistor (140) having a first gate (116);
a second transistor (100) having a second gate (106),
the second transistor (100) being stacked above (shown stacked above) the first transistor (140); and
an interconnect layer (134) formed between (shown between) the first (140) and second (100) transistors,
the interconnect layer (134) comprising a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) and electrically connecting (shown electrically connected) the first gate (116) and the second gate (106);
wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100).
Sharma fails to explicitly teach the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor.
However, Xie teaches wherein the conductive line horizontally extends (conductive line 2530 shown extending horizontally from first transistor, T1, on bottom left to directly above another first transistor, T1A, on the right, Fig 25; please see annotated figure below) from the first transistor to be disposed directly above (shown directly above) another first transistor (T1A, please see annotated figure below) stacked directly under (shown directly under second transistor, T2) the second transistor; and
wherein the conductive line is electrically isolated (conductive line 2530 is shown electrically isolated from the another first transistor, T1A; ) from the another first transistor (T1A).
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Sharma and Xie are considered analogous to the claimed invention because both are from the same field of endeavor of stacked semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Sharma with the features of Xie to create a structure wherein the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor that overcomes the challenges at nodes beyond 5 nm for final devices having cross-connections enabling the formation of latch circuits; forming comparable cross-connections for stacked CMOS structure compared to such cross connections easily formed for planar arrays of transistors, (Xie, [0047]).
Regarding claim 20, the combination of Sharma and Xie discloses the structure of claim 19. Sharma goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112), the conductive line (114A), and a second conductive via (114B).
Regarding claim 21, the combination of Sharma and Xie discloses the structure of claim 19. Sharma goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112) that connects (shown connected) to the first gate (116), a second conductive via (114B: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) that connects (shown connected) to the second gate (106), and the conductive line (114A) connected (shown connected) to both the first (112) and second (114B) conductive vias.
Regarding claim 22, the combination of Sharma and Xie discloses the structure of claim 19. Sharma goes on to teach wherein:
a conductive connection (114C: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) connects (shown connected) the first gate (116) to a first conductive via (112); and
the interconnect layer (134) comprises the first conductive via (112) connected (shown connected) to the conductive connection (114C),
a second conductive via (114B) connected (shown connected) to the second gate (106), and
the conductive line (114A) connected (shown connected) to both the first (112) and second (114B) conductive vias.
Regarding claim 23, the combination of Sharma and Xie discloses the structure of claim 19. Sharma goes on to teach wherein the first (116, Fig 3) and second (106) gates are connected (shown connected) by the interconnect layer (134) for simultaneous control (simultaneous control, [0032]).
Regarding claim 24, Sharma teaches a method comprising:
providing a first transistor (140, Fig 3) having a first gate (116); and
providing a second transistor (100) having a second gate (106),
the second transistor (100) being stacked above (shown stacked above) the first transistor (140), wherein
an interconnect layer (134) is formed between (shown between) the first (140) and second (100) transistors,
the interconnect layer (134) comprising a conductive line (114A: conductor 114 is comprised of three subparts, 114A is the lower third directly connected to 112, 114B is the middle third, 114C is the top third directly connected to 106) and electrically connecting (shown electrically connected) the first gate (116) and the second gate (106);
wherein the interconnect layer (134, Fig 3) electrically connects (shown electrically connected) the first transistor (140) to the second transistor (100).
Sharma fails to explicitly teach the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor.
However, Xie teaches wherein the conductive line horizontally extends (conductive line 2530 shown extending horizontally from first transistor, T1, on bottom left to directly above another first transistor, T1A, on the right, Fig 25; please see annotated figure above) from the first transistor to be disposed directly above (shown directly above) another first transistor (T1A, please see annotated figure above) stacked directly under (shown directly under second transistor, T2) the second transistor; and
wherein the conductive line is electrically isolated (conductive line 2530 is shown electrically isolated from the another first transistor, T1A; ) from the another first transistor (T1A).
Sharma and Xie are considered analogous to the claimed invention because both are from the same field of endeavor of stacked semiconductor transistor devices. Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine the device of Sharma with the features of Xie to create a structure wherein the conductive line horizontally extends from the first transistor to be disposed directly above another first transistor stacked directly under the second transistor; and wherein the conductive line is electrically isolated from the another first transistor that overcomes the challenges at nodes beyond 5 nm for final devices having cross-connections enabling the formation of latch circuits; forming comparable cross-connections for stacked CMOS structure compared to such cross connections easily formed for planar arrays of transistors, (Xie, [0047]).
Regarding claim 25, the combination of Sharma and Xie discloses the method of claim 24. Sharma goes on to teach wherein the interconnect layer (134, Fig 3) comprises a first conductive via (112), the conductive line (114A), and a second conductive via (114B).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Li (US 20150061148 A1) - Stacked TFTs with gates electrically connected.
Xie (US 20230343821 A1) - IBM cross-coupled transistors
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Jeremy D Watts whose telephone number is (703)756-1055. The examiner can normally be reached M-R 8:00am-4:30pm, F 8:00-3pm EST.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Chad Dicke can be reached at (571) 270-7996. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/JEREMY DANIEL WATTS/Examiner, Art Unit 2897 /CHAD M DICKE/Supervisory Patent Examiner, Art Unit 2897
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