DETAILED ACTION
This action is responsive to claims filed on 25 January 2024.
Claims 37-54 are pending for examination.
Allowable Subject Matter
Claim 37 and analogous Claim 46 would be allowable if rewritten or amended to overcome the rejection under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), 2nd paragraph, set forth in this Office Action.
Claims 38-45, 47-54, which depend directly or indirectly from Claims 37, 46, would be allowable.
The following is a statement of reasons for the indication of allowable subject matter.
The prior art, made of record, does not teach, make obvious, or suggest the claim limitations of Claim 37 and analogous Claim 46 required elements, as disclosed in Applicant’s claims. Specifically, the limitations directed to
“applying spin reversal transformations to the problem to generate a plurality of replicas of the problem”
“determining a respective embedding of each replica of the problem to the hardware graph to produce respective embedded replica problem graphs”
“adding the plurality of replicas of the problem to a problem Hamiltonian so that each embedded replica problem graph is embedded in a respective one of the non-overlapping regions on the hardware graph of the analog processor”
in exemplary Claim 37 and analogous Claim 46 limitations.
The closest prior arts, listed below, discloses:
Maassen van den Brink et al. (U.S. Pre-Grant Publication No. 20140229705) teaches analog processors comprising a plurality of quantum devices, arranged in a lattice, together with a plurality of coupling devices.
Roy et al. (U.S. Pre-Grant Publication No. 20140250288) teaches systems and methods allowing for formulation of embeddings of problems via targeted hardware (e.g., particular quantum processor).
Macready et al. (U.S. Pre-Grant Publication No. 20110060711) teaches association graphs solved for a clique, providing results to a query or problem and/or an indication of a level of responsiveness of the results, using analog processors such as quantum processors.
Rose et al. (U.S. Pre-Grant Publication No. 20080176750) teaches an analog processor, for example a quantum processor, including a plurality of elongated qubits that are disposed with respect to one another such that each qubit may selectively be directly coupled to each of the other qubits via a single coupling device.
Amin et al. (U.S. Pre-Grant Publication No. 20150032993) teaches orthogonal control of non-orthogonal qubit parameters of a logical qubit allowing for increasing the length of a qubit chain thereby increasing the effective connectivity of the qubit chain.
In summary, the references made of record, fail to disclose the required claimed technical features recited by the Claim 37 and analogous Claim 46 limitations as a whole.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 37-54 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
The term “small in relation” in line 2 of claim 37 and analogous claim 46 is a relative term which renders the claim indefinite. The term “small in relation” is not clearly defined by the claim and one of ordinary skill in the art would not be reasonably apprised of the scope of the invention. It is indefinite as to the degree and scope of what is being measured to be considered small when referring to the problem in relation to the topology of the analog processor. For examination purposes, “small in relation” has been construed as “problem small in relation to the size of the analog processor or be a portion of a problem that is small in relation to the size of the analog processor”, as outlined in Specification [0183]. Claims 38-45, 47-54, which depend directly or indirectly from claims 37, 46, are similarly rejected.
Claim 38 and analogous claim 47 recites the limitation "the spin reversal transformation" in line 3. There is insufficient antecedent basis for this limitation in the claim. For examination purposes, "the spin reversal transformation" has been construed to be “the spin reversal transformations”. Claims 48-54, which depend directly or indirectly from claim 47, are similarly rejected.
Conclusion
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/MM/Examiner, Art Unit 2129
/MICHAEL J HUNTLEY/Supervisory Patent Examiner, Art Unit 2129
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