CTNF 18/537,211 CTNF 85929 DETAILED ACTION Notice of Pre-AIA or AIA Status 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Election/Restrictions 08-25-01 AIA Applicant’s election without traverse of Species 4, FIG. 4B, Claims 1 – 20 in the reply filed on 04/10/2026 is acknowledged. Drawings Objections The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, In claim 7 and 14 the “virtual center line” recitations; and In claims 4-6, 15 and 17-19, the recitations of the recited 1 st – 4 th portions must be shown or the feature(s) canceled from the claim(s). No new matter should be entered. 06-22 Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance. Claim Rejections - 35 USC § 112 07-30-02 AIA The following is a quotation of 35 U.S.C. 112(b): (b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention. The following is a quotation of 35 U.S.C. 112 (pre-AIA), second paragraph: The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention. 07-34-01 Claims 1-10 and 12-20 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention. Claims 1 and 12 recites “turned upside down” is vague and unclear and indefinite because it is not defined along which axis or orientation, flipped upside down or right side up or north to south or south to north or east to west or west to east direction or at which point the second cell should be mirrored compared to the first cell. As the claim is unclear and indefinite. Claims 5, 15 and 18 recites “wherein the 1.sup.st portion is symmetrical to the 4th portion” is unclear and indefinite as what part of the portion are symmetrical? Physical feature or features and what are the feature or features or electrical features such as current of voltage? Furthermore, symmetrical in what axis or direction, or translational symmetry? As the claims are unclear and indefinite. Claim Rejections - 35 USC § 102 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-07-aia AIA 07-07 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – 07-08-aia AIA (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. 07-15 AIA Claim s 1-2, 4-6 10 and 18-20 are rejected under 35 U.S.C. 102( a)(a ) as being anticipated by ISODA 20090146693 . PNG media_image1.png 477 748 media_image1.png Greyscale Regarding claim 1, fig.23 together with fig. 8, and associated text in par [0164]-[0170] of ISODA discloses a semiconductor device based on a cell architecture which comprises: a 1st semiconductor cell C01; and a 2nd semiconductor cell C02 which is connected to the 1st semiconductor cell in a 1st direction such that an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell (fig. 23 is an implementation of the inverter chain, see schematic in fig. 8), wherein the 2nd semiconductor cell is in a form in which the 1st semiconductor cell is turned upside down (see fig. 23). Regarding claim 2, fig. 23 of ISODA disclose wherein the output pin of the 1st semiconductor cell comprises a 1st metal line M1, and the input pin of the 2nd semiconductor cell comprises a 2nd metal line M1, and wherein at least one the 1st and 2nd metal lines is extended in the 1st direction, and connected to each other. Regarding claims 4-5 (see examiner rejection of claim 18 below), ISODA discloses wherein the 1st semiconductor cell comprises a 1st portion and a 2nd portion below the 1st portion in a 2nd direction intersecting the 1st direction, the 1st portion comprising a 1st source/drain region and a 1st interconnect structure, wherein the 2nd semiconductor cell comprises a 3rd portion and a 4th portion below the 3rd portion in the 2nd direction, the 4th portion comprising a 2nd source/drain region and a 2nd interconnect structure, and wherein the 1st portion is the same as the 4th portion (fig. 23 which can virtually be divided into different parts as claimed. Insofar as the term can be understood, C01 and C02 are symmetrical to each other. In all cases, the polarity of the source/drain regions in the NMOS part will be n-type, in the PMOS part it will be p-type in both cells, as is generally the case in CMOS based logic.). PNG media_image2.png 702 980 media_image2.png Greyscale Regarding claim 6. The semiconductor device of claim 5, wherein the 1.sup.st portions and the 3.sup.rd portion are respectively divided from the 2.sup.nd portion and the 4.sup.th portion by a virtual horizontal center line extended in the 1.sup.st direction on the 1.sup.st and 2.sup.nd semiconductor cells. Regarding claim 10, ISODA discloses wherein the 1st and 2nd semiconductor cells comprise a same logic circuit. PNG media_image3.png 469 741 media_image3.png Greyscale Regarding claim 18, fig. 23 of ISODA discloses a semiconductor device comprising: a 1st semiconductor cell C01; and a 2nd semiconductor cell C02 adjacent and connected to the 1st semiconductor cell in a 1st direction Y, wherein the 1st semiconductor cell comprises a 1st portion (NMOS left side – examiner consider NMOS to be top toward top of page) and a 2nd portion (PMOS both left and right side) below (examiner consider PMOS to be below as it is below NMOS and this is relative) the 1st portion in a 2nd direction X intersecting the 1st direction, the 1st portion comprising a 1st source/drain region (NMOS source or drain) and a 1st interconnect structure M1 (see fig. 24), wherein the 2nd semiconductor cell comprises a 3rd portion (PMOS left side – examiner consider PMOS top of the page) and a 4th portion (NMOS both left and right side) below the 3rd portion in the 2nd direction, the 4th portion comprising a 2nd source/drain region and a 2nd interconnect structure M1, and wherein the 1st portion is symmetrical to the 4th portion (both are NMOS). Regarding claim 19, ISODA discloses wherein the 1st and the 2nd semiconductor cells comprise a same logic circuit, and wherein a polarity of the 1st source/drain region in the 1st portion is the same as a polarity of the 2nd source/drain region in the 4th portion (both are NMOS polarity). Regarding claim 20, fig.23 together with fig. 8, and associated text in par [0164]-[0170] of ISODA discloses further comprising a 3rd semiconductor cell C03 adjacent and connected to the 2nd semiconductor cell in the 1st direction (the C03 cell extends in the first direction), wherein the 1st to 3rd semiconductor cells comprise a same logic circuit, and wherein an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell, and an output pin of the 2nd semiconductor cell is connected to an input pint of the 3rd semiconductor cell (see fig. 8 configuration) Claim Rejections - 35 USC § 103 07-06 AIA 15-10-15 In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status. 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-21-aia AIA Claim (s) 3, 7-9 and 11-17 are rejected under 35 U.S.C. 103 as being unpatentable over ISODA in view of Chen et al. 20230036522 . Regarding claim 3, ISODA does not disclose wherein each of the 1st and 2nd semiconductor cells comprises a source/drain region connected to a backside power rail formed at a back side of the cell architecture. However, fig. 1A and par [0046] of Chen discloses source terminal of the PMOS transistor T1p is conductively connected to a front-side power rail 30F through a top via-connector VT, and the source terminal of the NMOS transistor T2n is conductively connected to a back-side power rail 30B through a bottom via-connector VB. As such it would have been obvious to form a device of ISODA further comprising wherein each of the 1st and 2nd semiconductor cells comprises a source/drain region connected to a backside power rail formed at a back side of the cell architecture in order to form power line the back side of the structure. Regarding claim 7, ISODA discloses claim 1, but does not discloses comprising: a 1st backside power rail along a 1st boundary of the cell architecture; a 2nd backside power rail along a virtual center line of the cell architecture; and a 3rd backside power rail along a 2nd boundary of the cell architecture opposite to the 1st boundary in a 2nd direction intersecting the 1st direction, wherein the 1st to 3rd backside power rails are extended in the 1st direction. However, fig. 1A of Chen discloses three backside power rail along cell architecture for different purpose. It would have been obvious to form a device of ISODA further comprising: a 1st backside power rail along a 1st boundary of the cell architecture; a 2nd backside power rail along a virtual center line of the cell architecture; and a 3rd backside power rail along a 2nd boundary of the cell architecture opposite to the 1st boundary in a 2nd direction intersecting the 1st direction, wherein the 1st to 3rd backside power rails are extended in the 1st direction in order provide power to the cell architecture. Regarding claim 8, Chen discloses wherein the 1st and 3rd backside power rails are connected to a 1st voltage source, and the 2nd backside power rail is connected to a 2nd voltage source different from the 1st voltage source. Regarding claim 9, ISODA discloses wherein the 1st semiconductor cell comprises a 1st transistor comprising a 1st source/drain region, and a 2nd transistor comprising a 2nd source/drain region, wherein the 2nd semiconductor cell comprises a 3rd transistor comprising a 3rd source/drain region, and a 4th transistor comprising a 4th source/drain region. It would have been obvious to form a device wherein the 1st source/drain region is connected to the 1st backside power rail, and the 4th source/drain region is connected to the 3rd backside power rail, and wherein the 2nd and 3rd source/drain regions are connected to the 2nd backside power rail in order to provide power as desired. Regarding claim 11, ISODA discloses a semiconductor device based on a cell architecture which comprises: a 1st semiconductor cell; a 2nd semiconductor cell which is connected to the 1st semiconductor cell such that an output pin of the 1st semiconductor cell is connected to an input pin of the 2nd semiconductor cell in a 1st direction;, wherein the 1st semiconductor cell and the 2nd semiconductor cell comprise a same logic circuit. ISODA does not disclose of at least one backside power rail formed at a back side of the cell architecture wherein the 1st semiconductor cell and the 2nd semiconductor cell are both connected to at least one backside power rail. However, fig. 1A and par [0046] of Chen discloses source terminal of the PMOS transistor T1p is conductively connected to a front-side power rail 30F through a top via-connector VT, and the source terminal of the NMOS transistor T2n is conductively connected to a back-side power rail 30B through a bottom via-connector VB. As such it would have been obvious to form a device of ISODA further comprising of at least one backside power rail formed at a back side of the cell architecture wherein the 1st semiconductor cell and the 2nd semiconductor cell are both connected to at least one backside power rail in order to form power line the back side of the structure. Regarding claim 12, ISODA discloses wherein the 2nd semiconductor cell is in a form in which the 1st semiconductor cell is turned upside down. Regarding claim 13, ISODA discloses wherein the output pin and the input pint are aligned with each other in the 1st direction. Regarding claim 14, fig. 1A of Chen discloses at least three backside power rails (30B, 120B and 140B). As such it would have been obvious to form a device wherein the at least one backside power rail comprises: a 1st backside power rail along a 1st boundary of the cell architecture; a 2nd backside power rail along a virtual center line of the cell architecture; and a 3rd backside power rail along a 2nd boundary of the cell architecture opposite to the 1st boundary in a 2nd direction intersecting the 1st direction, wherein the 1st to 3rd backside power rails are extended in the 1st direction in order to meet the applicant desire specification. Regarding claim 15 (see rejection of claim 18) The semiconductor device of claim 11, wherein the 1st semiconductor cell comprises a 1st portion and a 2nd portion below the 1st portion in a 2nd direction intersecting the 1st direction, the 1st portion comprising a 1st source/drain region and a 1st interconnect structure, wherein the 2nd semiconductor cell comprises a 3rd portion and a 4th portion below the 3rd portion in the 2nd direction, the 4th portion comprising a 2nd source/drain region and a 2nd interconnect structure, and wherein the 1st portion is symmetrical to the 4th portion. Regarding claim 16, ISODA discloses wherein the output pin of the 1st semiconductor cell comprises a 1st metal line, and the input pin of the 2nd semiconductor cell comprises a 2nd metal line, and wherein at least one the 1st and 2nd metal lines is extended in the 1st direction, and connected to each other (see fig. 23-24). Regarding claim 17, fig. 23-24 of ISODA discloses wherein the 1st metal line is on one of the 1st and 2nd portions, and the 2nd metal line is on one of the 3rd and 4th portions aligned with the one of the 1st and 2nd portions in the 1st direction. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to VONGSAVANH SENGDARA whose telephone number is (571)270-5770. The examiner can normally be reached 9AM-6PM M-F EST. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached on (571)272-1236 . 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If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /VONGSAVANH SENGDARA/Primary Examiner, Art Unit 2893 Application/Control Number: 18/537,211 Page 2 Art Unit: 2893 Application/Control Number: 18/537,211 Page 3 Art Unit: 2893 Application/Control Number: 18/537,211 Page 4 Art Unit: 2893 Application/Control Number: 18/537,211 Page 5 Art Unit: 2893 Application/Control Number: 18/537,211 Page 6 Art Unit: 2893 Application/Control Number: 18/537,211 Page 7 Art Unit: 2893 Application/Control Number: 18/537,211 Page 8 Art Unit: 2893 Application/Control Number: 18/537,211 Page 9 Art Unit: 2893 Application/Control Number: 18/537,211 Page 10 Art Unit: 2893 Application/Control Number: 18/537,211 Page 11 Art Unit: 2893
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