DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-12 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkner et al (US PG Pub # 2018/0252594) in view of Sakano (US PG Pub # 2016/0363487). The Jenkner reference discloses an integrated circuit1, comprising a temperature sensor (para. # 0053) that includes:
first and second diode-connected transistors (para. # 0045);
a buffer circuit (12; Fig. 1);
a switching circuit (70, 72; Fig. 6);
a control unit (26; Fig. 2) configured to control the switching circuit to successively apply a voltage generated across the first diode-connected transistor (22) and a voltage generated across the second diode-connected transistor (24) to an input of the buffer circuit (para. # 0041 & 0045);
an analog-to-digital converter (para. # 0044) having an input connected to an output of the buffer circuit, the analog-to-digital converter configured to successively convert voltages output from the buffer circuit into numeric voltage values corresponding to the voltages generated across the first and second diode-connected transistors and to calculate a numeric value corresponding to a difference between the numeric values, wherein the numeric value is proportional to absolute temperature and independent of offset voltages of the analog-to-digital converter and the buffer circuit (para. # 0040).
The Jenkner reference does not disclose that the two diode connected transistors (22,24) are of different sizes. However it was a common configuration to manufacture a bandgap sensor comprising of two different diode connected transistors, where the two transistors are of different sizes, as shown by the example of the Sakano reference (Para. # 0005-0007), to have two different sensor outputs in order to optimize the overall sensor’s performance by allowing for better sensitivity to temperature changes caused by different current densities in the different sized diode-connected transistors, and it would have been an obvious modification to make to the temperature sensor of Jenkner for the same reason.
With respect to claim 2, the Jenkner reference discloses a processing unit (14) for determining a temperature value (para. # 0023).
With respect to claim 3, the Jenkner reference discloses the use of a “lookup table” to calculate temperature (para. # 0023).
With respect to claim 4, the use of operational amplifiers to amplify and combine weak sensor signals as shown by the Sakano reference (Fig. 1B) and it would have been obvious to use the same configuration in the circuit of Jenkner motivated by its art recognized suitability for its intended purpose.
With respect to claim 5, see paragraph # 0045 of Jenkner.
With respect to claim 6, see paragraphs # 0069-0070 of Jenkner.
Claims 7-12 simply repeat the limitations already listed above.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. The other references cited but not applied show the general state of the art.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANDY W GIBSON whose telephone number is (571)272-2103. The examiner can normally be reached Tue-Friday 10AM-6PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Peter Macchiarolo can be reached at 571-272-2375. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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RANDY W. GIBSON
Primary Examiner
Art Unit 2856
/RANDY W GIBSON/Primary Examiner, Art Unit 2855
1 Although the Jenkner reference does not expressly state so, the context implies that the circuits (30, 40) disclosed in this reference are intended to be a single integrated circuit with the temperature sensor built-in (para. # 0048, 0050, 0053 & 0081). It is well-known in the art that bandgap temperature sensors are usually included on the same integrated chip as the integrated circuit that is being monitored by the temperature sensor, as this makes the temperature sensing of the integrated circuit more accurate since the temp. sensor is physically part of the same chip; see para. # 0021 of US PG Pub # 2016/0363487 (Sakano), or para. # 0001 of US PG Pub # 2008/0069176 (Pertijs et al), for examples.