DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Information Disclosure Statement
The information disclosure statement filed 19 March 2026 fails to comply with 37 CFR 1.98(a)(3)(i) because it does not include a concise explanation of the relevance, as it is presently understood by the individual designated in 37 CFR 1.56(c) most knowledgeable about the content of the information, of each reference listed that is not in the English language. It has been placed in the application file, but the references crossed out have not been considered.
Response to Arguments
Applicant's arguments filed 14 May 2026 have been fully considered but they are not persuasive. Applicant argues that the Jenkner reference does not disclose a “buffer circuit” located between the switching circuits (70,72) and the A/D Converter (76) shown in Figure 6. Even though this might be technically accurate, it was a well-known and common practice to place some type of amplifier or buffer between the analog sensing elements and an A/D converter as shown in Figure 2 of the Lee et al reference (US PGPb # 2022/0120620) which clearly shows a “buffer circuit” (element 240) between the analog switches S1 & S2 and the A/D converter (250). Since applicant himself submitted the Lee reference on the latest IDS filed 19 March 2026, it is obvious that the applicant knew this prior to filing his amendment on 14 May. This is NOT a new issue, as the applicant actually knew that this circuit arrangement was old and known prior to his filing his latest response, and applicant did not say anything about this new reference in his response, although it seem clearly relevant to the very argument that the applicant was trying to make. Applicant has essentially admitted by slience that the element that he alleges was missing from the circuit shown in the Jenkner reference was a known element, and that the sensor configuration shown in the Lee reference was apparently an art recognized alternative configuration.
Applicant made no separate arguments for any other claim besides claim 1, so they are presumed to stand or fall with claim 1.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1-6 are rejected under 35 U.S.C. 103 as being unpatentable over Jenkner et al (US PG Pub # 2018/0252594) in view of Lee et al (US PGPb # 2022/0120620), and Sakano (US PG Pub # 2016/0363487).
The Jenkner reference discloses an integrated circuit1, comprising
a temperature sensor (para. # 0053) that includes:
first and second diode-connected transistors (para. # 0045);
a switching circuit (70, 72; Fig. 6);
a control unit (26; Fig. 2) configured to control the switching circuit to successively apply a voltage generated across the first diode-connected transistor (22) and a voltage generated across the second diode-connected transistor (24) to an input of the buffer circuit (para. # 0041 & 0045);
an analog-to-digital converter (para. # 0044) having an input connected to an output of the buffer cicuit, the analog-to-digital converter configured to successively convert voltages output from the buffer circuit into numeric voltage values corresponding to the voltages generated across the first and second diode-connected transistors and to calculate a numeric value corresponding to a difference between the numeric values, wherein the numeric value is proportional to absolute temperature and independent of offset voltages of the analog-to-digital converter and the buffer circuit (para. # 0040).
The Jenkner reference does not appear to disclose a “buffer circuit” located between the switching circuits (70,72) and the A/D Converter (76) shown in Figure 6. However, it was a well-known and common practice to place some type of amplifier or buffer between the analog sensing elements and an A/D converter as shown in Figure 2 of the Lee et al reference (US PGPb # 2022/0120620) which clearly shows a “buffer circuit” (element 240) between the analog switches S1 & S2 and the A/D converter (250). He purpose of a buffer circuit was usually to amplify the weak analog sensor signal to place it withing the detection range of the A/D convertor, and to electrically isolate the noisy A/D convertor from interfering with the operation of the sensors, and would have been an obvious alternative configuration for the circuit shown in Figure 6 of Jenkner for the same reasons.
The Jenkner reference does not disclose that the two diode connected transistors (22,24) are of different sizes. However it was a common configuration to manufacture a bandgap sensor comprising of two different diode connected transistors, where the two transistors are of different sizes, as shown by the example of the Sakano reference (Para. # 0005-0007), to have two different sensor outputs in order to optimize the overall sensor's performance by allowing for better sensitivity to temperature changes caused by different current densities in the different sized diode-connected transistors, and it would have been an obvious modification to make to the temperature sensor of Jenkner for the same reason.
With respect to claim 2, the Jenkner reference discloses a processing unit (14) for determining a temperature value (para. # 0023).
With respect to claim 3, the Jenkner reference discloses the use of a "lookup table" to calculate temperature (para. # 0023).
With respect to claim 4, the use of operational amplifiers to amplify and combine weak sensor signals as shown by the Sakano reference (Fig. 1B) and it would have been obvious to use the same configuration in the circuit of Jenkner motivated by its art recognized suitability for its intended purpose.
With respect to claim 5, see paragraph # 0045 of Jenkner.
With respect to claim 6, see paragraphs # 0069-0070 of Jenkner.
Conclusion
Claims 7-12 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The prior art of record does not show, among other things, “an operational amplifier having an inverting input connected to an emitter of the first diode- connected bipolar transistor and a non-inverting input connected to an emitter of the second diode- connected bipolar transistor via a resistor; a first PMOS-type transistor having a gate connected to an output of the operational amplifier and a drain connected to the inverting input of the operational amplifier and to the emitter of the first diode-connected bipolar transistor; and a second PMOS-type transistor having a gate connected to an output of the operational amplifier and a drain connected to the non-inverting input of the operational amplifier and to the emitter of the second diode-connected bipolar transistor via the resistor.”
Claims 13-18 are allowable over the art of record for the same reason.
THIS ACTION IS MADE FINAL. Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to RANDY W GIBSON whose telephone number is (571)272-2103. The examiner can normally be reached Tue-Friday 10AM-6PM.
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RANDY W. GIBSON
Primary Examiner
Art Unit 2856
/RANDY W GIBSON/ Primary Examiner, Art Unit 2855
1 Although the Jenkner reference does not expressly state so, the context implies that the circuits (30, 40) disclosed in this reference are intended to be a single integrated circuit with the temperature sensor built-in (para. # 0048, 0050, 0053 & 0081). It is well-known in the art that bandgap temperature sensors are usually included on the same integrated chip as the integrated circuit that is being monitored by the temperature sensor, as this makes the temperature sensing of the integrated circuit more accurate since the temp. sensor is physically part of the same chip; see para. # 0021 of US PG Pub # 2016/0363487 (Sakano), or para. # 0001 of US PG Pub # 2008/0069176 (Pertijs et al), for examples.
Prosecution Insights