DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Continued Examination Under 37 CFR 1.114
A request for continued examination under 37 CFR 1.114, including the fee set forth in 37 CFR 1.17(e), was filed in this application after final rejection. Since this application is eligible for continued examination under 37 CFR 1.114, and the fee set forth in 37 CFR 1.17(e) has been timely paid, the finality of the previous Office action has been withdrawn pursuant to 37 CFR 1.114. Applicant's submission filed on 02/10/2026 has been entered.
Response to Remarks/Arguments
With respect to the rejection of claims 1 and 22 under 35 USC 103, Applicant’s arguments filed 02/03/2026 have been fully considered but are moot in view of new ground rejection set forth herein.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1, 2, 7, 8, 12, 20-23 are rejected under 35 U.S.C. 103 as being unpatentable over Abshishek (US 2016/0169966A1) in view of Rao (US 20220109445 A1).
Regarding claim 1, Abshishek teaches an apparatus, comprising:
a first multiplexer (Fig. 2, [0032], [0033], 230) including inputs configured to receive an input data signal (D) and a scan signal (SI), and a select input configured to receive shift control signal (SE);
a first latch (220) including an input coupled to an output of the first multiplexer, and a complementary clock input configured to receive a clock signal (CLK);
a second latch (210) including an input coupled to the output of the first multiplexer, and a non- complementary clock input configured to receive the clock signal; and
a second multiplexer (240) including inputs coupled to outputs of the first and second latches (Q0, Q1), respectively, a select input configured to receive the clock signal, and an output configured to generate an output data or scan signal.
Abshishek does not explicitly teach the apparatus, wherein the first latch is configured to generate a signal at an output of the first latch in response to a reset signal;
wherein the first latch comprises:
a first inverter;
a first tristate inverter cross-coupled with the first inverter, wherein the first tristate inverter is configured to receive the clock signal and the reset signal; and
a second tristate inverter coupled to the first inverter, wherein the second tristate inverter is configured to receive the clock signal and the reset signal;
wherein the second tristate inverter comprises:
first, second, third, fourth, and fifth field effect transistors (FETs) coupled in series between an upper voltage rail and a lower voltage rail, wherein the first FET includes a gate configured to receive the reset signal, the second FET is configured to receive the clock signal, the third and fourth FETs include gates coupled to the output of the first multiplexer, the fifth FET includes a gate configured to receive a complementary clock signal, and a node between the third and fourth FETs is coupled to an input of the first inverter; and
a sixth FET coupled between the node and the lower voltage rail, wherein the sixth FET includes a gate configured to receive the reset signal, and a node between a source of the fifth FET and the lower voltage rail is coupled to a source of the sixth FET.
Rao teaches an apparatus, wherein a first latch (Fig. 6, 600, [0092]) is configured to generate a signal at an output (OUT) of the first latch in response to a reset signal (RST);
wherein the first latch comprises:
a first inverter (622);
a first tristate inverter (624) cross-coupled (pn1, pn2) with the first inverter, wherein the first tristate inverter is configured to receive a clock signal (CLK) and the reset signal (RST); and
a second tristate inverter (610) coupled to the first inverter, wherein the second tristate inverter is configured to receive the clock signal (CLK) and the reset signal (RST);
wherein the second tristate inverter comprises:
first, second, third, fourth, and fifth field effect transistors (FETs) (M10, M11, M12, M13, M14) coupled in series between an upper voltage rail (Vdd) and a lower voltage rail (Vss), wherein the first FET (M10) includes a gate configured to receive the reset signal (RST), the second FET (M12) is configured to receive the clock signal (RST), the third and fourth FETs (M11, M14) include gates coupled to the output of a multiplexer (Fig. 4, output of 410-0, for example), the fifth FET (M13) includes a gate configured to receive a complementary clock signal (~CLK), and a node (pn1) between the third and fourth FETs is coupled to an input of the first inverter (622); and
a sixth FET (M22) coupled between the node (pn1) and the lower voltage rail (Vss), wherein the sixth FET includes a gate configured to receive the reset signal (RST), and a node between a source of the fifth FET and the lower voltage rail is coupled to a source of the sixth FET (Vss).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply the latch of Rao to the latch of Abshishek in order to provide additional control function of resetting the latches which is well-known in the art (Rao, [0094]).
Regarding claim 2, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Rao further teaches an apparatus, wherein a first multiplexer (Fig. 5) comprises:
first, second, third, and fourth field effect transistors (FETs) coupled in series between an upper voltage rail (Vdd) and a lower voltage rail (Vss), wherein the first FET (M2) includes a gate configured to receive the shift control signal (SFT), the second (M1) and third (M4) FETs include gates configured to receive the input data signal (D), and the fourth FET (M3) includes a gate configured to receive a complementary shift control signal (SFT bar); and
fifth, sixth, seventh, and eighth FETs coupled in series between the upper voltage rail and the lower voltage rail, wherein the fifth (M5) and eighth (M8) FETs include gates configured to receive the scan signal (S), the sixth FET (M6) includes a gate configured to receive the complementary shift control signal, and the seventh FET (M7) includes a gate configured to receive the shift control signal.
Regarding claim 7, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Rao further teaches the apparatus, wherein the first tristate inverter comprises first, second, third, and fourth FETs (Fig. 6, M16~M19) coupled in series between an upper voltage rail (Vdd) and a lower voltage rail (Vss), wherein the first and fourth FETs (M16, M19) include gates coupled to an output of the first inverter (622), the second FET (M17) includes a gate configured to receive a complementary clock signal, the third FET (M18) includes a gate configured to receive the clock signal, and a node between the second and third FETs is coupled to an input of the first inverter (pn1).
Regarding claim 8, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Rao further teaches an apparatus, wherein the second latch (Fig. 6) comprises:
a second gating circuit (610) configured to receive the clock signal (CLK to M12/M13);
a second inverter (622) coupled to the first gating circuit; and
a second tristate inverter (624) cross-coupled with the first inverter, wherein the first tristate inverter is configured to receive the clock signal (CLK to M17/M18).
Regarding claim 12, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Rao further teaches an apparatus, wherein the second latch is configured to generate the signal at an output of the second latch in response to a reset signal (Fig. 6, RST, [0093] a reset signal (RST)).
Regarding claim 20, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Rao further teaches the apparatus, wherein the second tristate inverter (Fig. 6, 624) comprises:
first, second, third, fourth, and fifth FETs (Fig. 6, M15~M19) coupled in series between an upper voltage rail (Vdd) and a lower voltage rail (Vss), wherein the first FET includes a gate configured to receive the reset signal (RST), the second FET is configured to receive the clock signal (CLK), the third and fourth FETs include gates coupled to the output of the first multiplexer (pn2), the fifth FET includes a gate configured to receive a complementary clock signal (CLK bar), and a node between the third and fourth FETs is coupled to an input of the first inverter (pn1); and
a sixth FET (M22) coupled between the node and the lower voltage rail (VSS), wherein the sixth FET includes a gate configured to receive the reset signal (RST).
Regarding claim 21, all the limitations of claim 20 are taught by Abshishek in view of Rao.
Rao further teaches the apparatus, wherein the second latch comprises:
a second gating circuit configured to receive the clock signal (Fig. 6, 610, M12, M13);
a second inverter (622) coupled to the first gating circuit; and
a second tristate inverter cross-coupled with the first inverter (624), wherein the first tristate inverter is configured to receive the clock signal (CLK) and the reset signal (RST).
Regarding claim 22, this claim has substantially the same subject matter as that in claim 1. Therefore, claim 22 is rejected under the same rationale as claim 1 above.
Regarding claim 23, this claim has substantially the same subject matter as that in claim 12. Therefore, claim 23 is rejected under the same rationale as claim 12 above.
Claims 9-11 are rejected under 35 U.S.C. 103 as being unpatentable over Abshishek (US 2016/0169966A1) in view of Rao (US 20220109445 A1) as applied to claim 1 above, and further in view of Morris (US 2016/0373108 A1).
Regarding claim 9, all the limitations of claim 1 are taught by Abshishek in view of Rao.
Abshishek in view of Rao does not explicitly teach the apparatus, wherein the second multiplexer comprises: a first gating circuit coupled between the output of the first latch and the output of the second multiplexer; and a second gating circuit coupled between the output of the second latch and the output of the second multiplexer.
Morris teaches an apparatus, wherein a multiplexer comprises pass gate circuits or tri-state circuits ([0003], Figs. 2, 4A, 5).
Therefore, it would have been obvious to one having ordinary skill in the art before the effective filing date of claimed invention to apply gating circuits such as pass gates and tri-state gates to the multiplexer implementation of Abshishek in view of Morris as doing so is well-known and conventional (Morris, [0003]).
Regarding claim 10, all the limitations of claim 9 are taught by Abshishek in view of Rao and Morris.
Morris further teaches the apparatus, wherein at least one of the first gating circuit or the second gating circuit comprises a transmission gate (Figs. 2, 4A).
Regarding claim 11, all the limitations of claim 9 are taught by Abshishek in view of Rao and Morris.
Morris further teaches the apparatus, wherein at least one of the first gating circuit or the second gating circuit comprises a tristate inverter (Figs. 2, 5).
Conclusion
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/SEOKJIN KIM/Primary Examiner, Art Unit 2844
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