Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Non-Final Office Action
DETAILED ACTION
Examiner’s Notes
(a) Claim date: 12/12/2023.
(b) Priority date: 01/16/2023.
Claim Rejections - 35 USC 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:A person shall be entitled to a patent unless:(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.Claims 1-5, 8-19, are rejected under 35 U.S.C. 102(a)(1) as being anticipated by the prior art of record “Roy” <US 2023/0139623>.
(As to claim 1, 11 and 18, Roy discloses)
1.(Original) A method of designing an integrated circuit, the method comprising [Fig. 2]:
generating a layout based on data defining a circuit [¶0075, “synthesis tool 505... computes the area, delay, and/or power of a physical data path circuit given a prefix graph," i.e., generating a predicted physical circuit implementation from data (the prefix graph) defining the circuit, which corresponds in function to generating a layout based on data defining a circuit.];
receiving at least one state variable of reinforcement learning [¶0042, "Reinforcement learning (RL) is a class of algorithms applicable to sequential decision making tasks. RL makes use of the Markov Decision Process (MDP) formalism wherein an agent 202 attempts to optimize a function in its environment 204”];and
updating the layout based on the at least one state variable, wherein the updating of the layout comprises modifying the circuit based on the at least one state variable [¶0051, “upon receiving the design state 206, the agent 202 (or agents) can modify the design state 206 via an action 210," and that "modifying the prefix graph may include adding a node, removing a node, or moving a node in the prefix graph," where each node "represents or is associated with one or more components of data path circuit that perform one or more operations," disclosing modifying the circuit based on the state variable.],
synchronizing the circuit with the layout [¶0076, "the environment 204 can use the synthesis tool 505 to generate a predicted physical data path circuit from the prefix graph"). Note: physical data path circuit is functionally equivalent to circuit layout],
performing a post-layout simulation based on a result of the synchronization [¶0074, Roy discloses that the environment "can calculate the delay, area, and power for the initial state (or current design state 206) and the delay, area, and power for the next design state 212," using either the synthesis tool or a "metrics predictor model," which corresponds functionally to performing a simulation/estimation based on the result of generating the physical circuit implementation.];
calculating a result value of the post-layout simulation [¶0077, Roy discloses that "the environment 204 can calculate a next reward 214" that "predicts the net change in area, power consumption and/or delay of the data path circuit 108 as a result of the action 210," by "determin[ing] a difference between the two [states]," disclosing calculating a result value (reward) based on the simulation/estimation of the modified circuit's parameters.],
PNG
media_image1.png
418
426
media_image1.png
Greyscale
and determining whether to modify the at least one state variable through the reinforcement learning according to the result value [Fig. 2, agent 202; Para 0041, “FIG. 2 illustrates an example system 200 for performing reinforcement learning to generate an improved design of a data path circuit, according to at least one embodiment. In some embodiments”].
(As to claim 2, 12, Roy disclose)
2. The method of claim 1, further comprising performing data pre-processing to perform the synchronizing before the updating of the layout [¶0195, “In at least one embodiment, data may undergo pre-processing as part of data processing pipeline to prepare data for processing by one or more applications”].
(As to claim 3, 13, 19, Roy disclose)
3. The method of claim 1, wherein the synchronizing of the circuit with the layout comprises
PNG
media_image2.png
484
460
media_image2.png
Greyscale
directly modifying data defining the layout without a conversion process based on the modification in the circuit according to the at least one state variable [Fig. 4, data defined layout blocks 405, 410 is extracted in accordance the state variables (305, 310) ].
(As to claim 4, Roy disclose)
4. The method of claim 3, wherein the synchronizing of the circuit with the layout comprises extracting a parasitic component based on the modified circuit and the layout to generate input data of the post-layout simulation [¶0028, “physical synthesis—e.g., when the analytical model is put through a simulation and converted to a predicted physical model”].
(As to claim 5, Roy discloses)
5. (Original) The method of claim 1, wherein:
PNG
media_image3.png
610
408
media_image3.png
Greyscale
the determining whether to modify the at least one state variable comprises comparing the result value with a reference value to determine whether to modify the at least one state variable [FIG. 9B, operation 938: Roy discloses determining "whether one or more stopping criteria have been met," where "[a] stopping criterion may be met, for example,... after one or more target goals (e.g., for area, power and/or delay) are met," disclosing comparing the result value (the area, power, and/or delay reflected in the reward) with a reference value (the target goal) to determine whether to modify the state variable.]
(As to claim 8, Roy discloses)
8. (Original) The method of claim 1, wherein:
the reinforcement learning is based on a Q-learning reinforcement learning technique “[0043] A Q-network may be trained via a process referred to as Q-learning. Q learning is a reinforcement learning process”]
(As to claim 9, 17, Roy disclose)
9. The method of claim 1, wherein the at least one state variable is a variable representing at least one of a width or length of a transistor included in the circuit [¶0087, “maximum circuit width”].
(As to claim 10, Roy disclose)
10. The method of claim 1, wherein the result value of the simulation comprises a value for at least one of a skew occurring in the circuit or a duty cycle of an output signal [0132, “timing and/or order, in which weight and/or other parameter information is to be loaded to configure, logic,”].
(As to claim 14, Roy disclose)
PNG
media_image4.png
356
420
media_image4.png
Greyscale
14. The system of claim 11, wherein the at least one processor extracts a parasitic component using the layout synchronized with the modified circuit [Fig. 6, area vs delay, caused, wherein, the delay is a function of parasitic component].
(As to claim 15, Roy discloses)
15. (Original) The system of claim 11, wherein:
the at least one processor modifies the at least one state variable based on reinforcement learning when it is determined to modify the at least one state variable according to the result value [FIG. 9B, operation 940 and return to operation 925, Roy discloses that when the stopping criterion is not met, the next design state is processed using the (reinforcement-learning-trained) machine learning model, disclosing modifying the state variable based on reinforcement learning when it is determined to do so according to the reward.]
(As to claim 16, Roy discloses)
16. (Original) The system of claim 11, wherein:
the at least one processor outputs the layout when it is determined not to modify the at least one state variable according to the result value [FIG. 9B, operations 938, 945: Roy discloses that when the stopping criterion is met, a final design state is selected/output without further modification.].
Allowable Subject Matter
The following claims would be allowable if all rejections/objections cited in this office action (if any) are overcome and rewritten to include all of the limitations of the base claim and any intervening claims.The reason for this allowance is: the claimed subject matter could not have been anticipated or obviated using any prior arts.Allowable claims are: 6-7, 20.
Conclusion
The prior art made of record in the form PTO-892 are not relied upon is considered pertinent to applicant's disclosure.Information regarding the status of an application may be obtained from the Patent Application Information Retrieval (PAIR) system. Status information for published applications may be obtained from either Private PAIR or Public PAIR. Status information for unpublished applications is available through Private PAIR only. For more information about the PAIR system, see http://pair-direct.uspto.gov. Should you have questions on access to the Private PAIR system, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative or access to the automated information system, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.Contact information:Any inquiry concerning this communication or earlier communications from the examiner should be directed to MOHAMMED ALAM whose telephone number is (571) 270-1507, email address: [mohammed.alam@uspto.gov] and fax number (571) 270-2507. The examiner can normally be reached on 10AM to 4PM (EST), Monday to Friday. If attempts to reach the examiner by telephone are unsuccessful, the Examiner's Supervisor, JACK CHIANG can be reached on (571) 272-7483. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300./Mohammed Alam/Primary Examiner, Art Unit 2851
Prosecution Insights