DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Tsuchida et al., US2021/0111743 A1, and further in view of Jin et al., US2016/0028351 A1.
Regarding claim 1, Tsuchida teaches A radio frequency module (Fig. 1, par. 0027; radio frequency module 1) comprising: a module substrate having a first main surface and a second main surface that are opposite to each other (par. 0075; a layout of circuit elements when principal surface 91a out of principal surfaces 91a and 91b on opposite sides of module board 91 (i.e., module substrate) is viewed from the positive z-axis.); a plurality of external connection terminals that are disposed on the second main surface (par. 0078; Note that on module board 91, antenna connection terminal 100, transmission input terminals 111 and 112, reception output terminals 121 and 122, input terminals 115 and 125, and output terminals 116 and 126 may be formed on principal surface 91b (a second principal surface).); a first power amplifier circuit and a second power amplifier circuit that are disposed on the first main surface (Fig. 6, par. 0153; Note that amplification elements 11A, 11B, 12A, and 12B may be disposed on principal surface 91b.); a first transformer that is connected to the first power amplifier circuit and disposed on the first main surface (Fig. 6, par. 0154; amplification elements 11A and 11B and interstage transformer 33 may be included in one semiconductor IC 76 located on the principal surface 91.); and a second transformer that is connected to the second power amplifier circuit and disposed on the second main surface (Fig. 6, par. 0154; amplification elements 12A and 12B and interstage transformer 38 may be included in one semiconductor IC 77 located on the principal surface 91.), and wherein the second power amplifier circuit is a differential-amplifier-type power amplifier circuit (par. 0036; Transmission power amplifier 12 is a differential amplifier that amplifies radio frequency signals.).
Tsuchida fails to teach the following recited limitation. However, Jin teaches wherein the first power amplifier circuit is a Doherty-type power amplifier circuit (par. 0013; The PA system includes a Doherty PA with a carrier amplification path having an output that includes a carrier transformer and a peaking amplification path having an output that includes a peaking transformer.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Tsuchida’s teachings and Jin’s teachings in order to result in efficient power amplification in many wireless applications (Jin, par. 0006).
Regarding claim 2, Tsuchida teaches A radio frequency module (Fig. 1, par. 0027; radio frequency module 1) comprising: a module substrate having a first main surface and a second main surface that are opposite to each other (par. 0075; a layout of circuit elements when principal surface 91a out of principal surfaces 91a and 91b on opposite sides of module board 91 (i.e., module substrate) is viewed from the positive z-axis.); a plurality of external connection terminals that are disposed on the second main surface (par. 0078; Note that on module board 91, antenna connection terminal 100, transmission input terminals 111 and 112, reception output terminals 121 and 122, input terminals 115 and 125, and output terminals 116 and 126 may be formed on principal surface 91b (a second principal surface).); a first power amplifier circuit and a second power amplifier circuit that are disposed on the first main surface (Fig. 6, par. 0153; Note that amplification elements 11A, 11B, 12A, and 12B may be disposed on principal surface 91b.); a first filter circuit that is connected to the first power amplifier circuit and has a pass band including a transmission band of a first band capable of concurrent transmission of at least two channels (Fig. 6A items 61 76; clearly shows filter 61 connected to power amplifier 76.); a second filter circuit that is connected to the second power amplifier circuit and has a pass band including the transmission band of the first band (Fig. 6A items 61 76; clearly shows filter 62 connected to power amplifier 77.); a first transformer that is connected between the first power amplifier circuit and the first filter circuit and disposed on the first main surface (Fig. 6, par. 0154; amplification elements 11A and 11B and interstage transformer 33 may be included in one semiconductor IC 76 located on the principal surface 91.); and a second transformer that is connected between the second power amplifier circuit and the second filter circuit and disposed on the second main surface (Fig. 6, par. 0154; amplification elements 12A and 12B and interstage transformer 38 may be included in one semiconductor IC 77 located on the principal surface 91.), the first power amplifier circuit amplifies the signal of the first channel (par. 0036; Power amplifier 11 is a differential amplifier that amplifies radio frequency signals, input through transmission input terminal 111, of communication band A (a first communication band) and communication band B (a second communication band) that belong to a first frequency band group.), and the second power amplifier circuit amplifies the signal of the second channel (par. 0036; Transmission power amplifier 12 is a differential amplifier that amplifies radio frequency signals, input through transmission input terminal 112, of communication band C that belongs to a second frequency band group having different frequency bands from the first frequency band group.).
Tsuchida fails to teach the following recited limitation. However, Jin teaches wherein in a case where signals of a first channel and a second channel lower than the first channel within the first band are transmitted at the same time (par. 0007; a Doherty power amplifier (PA) that includes a carrier amplification path having an output that includes a carrier transformer, and a peaking amplification path having an output that includes a peaking transformer. The Doherty PA further includes a combiner configured to combine the outputs of the carrier and peaking amplification paths into an output node.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Tsuchida’s teachings and Jin’s teachings in order to result in efficient power amplification in many wireless applications (Jin, par. 0006).
Regarding claim 3, Tsuchida and Jin teach all the limitations in claim 2. Tsuchida further teaches wherein the module substrate further includes a via conductor that is disposed between the first transformer and the second transformer (par. 0125; line conductor disposed along primary coil 31a and disposed along secondary coil 31b.).
Regarding claim 4, Tsuchida teaches A radio frequency module (Fig. 1, par. 0027; radio frequency module 1) comprising: a module substrate having a first main surface and a second main surface that are opposite to each other (par. 0075; a layout of circuit elements when principal surface 91a out of principal surfaces 91a and 91b on opposite sides of module board 91 (i.e., module substrate) is viewed from the positive z-axis.); a plurality of external connection terminals that are disposed on the second main surface (par. 0078; Note that on module board 91, antenna connection terminal 100, transmission input terminals 111 and 112, reception output terminals 121 and 122, input terminals 115 and 125, and output terminals 116 and 126 may be formed on principal surface 91b (a second principal surface).); a first power amplifier circuit that is disposed on the first main surface and supports a first power class (Fig. 6, par. 0153; Note that amplification elements 11A, 11B, 12A, and 12B may be disposed on principal surface 91b.); a second power amplifier circuit that is disposed on the first main surface and supports a second power class that is the same as the first power class (Fig. 6, par. 0153; Note that amplification elements 11A, 11B, 12A, and 12B may be disposed on principal surface 91b.); a first transformer that is connected to the first power amplifier circuit and disposed on the first main surface (Fig. 6, par. 0154; amplification elements 11A and 11B and interstage transformer 33 may be included in one semiconductor IC 76 located on the principal surface 91.); and a second transformer that is connected to the second power amplifier circuit and disposed on the second main surface (Fig. 6, par. 0154; amplification elements 12A and 12B and interstage transformer 38 may be included in one semiconductor IC 77 located on the principal surface 91.), and wherein, in a case where the first power class is applied, a radio frequency signal is amplified by the first power amplifier circuit but is not amplified by the second power amplifier circuit (par. 0036; Power amplifier 11 is a differential amplifier that amplifies radio frequency signals, input through transmission input terminal 111, of communication band A (a first communication band) and communication band B (a second communication band) that belong to a first frequency band group.).
Tsuchida fails to teach the following recited limitation. However, Jin teaches wherein, in a case where a third power class that is defined by a maximum output power higher than the first power class and the second power class is applied, radio frequency signals are amplified at the same time by the first power amplifier circuit and the second power amplifier circuit (par. 0007; a Doherty power amplifier (PA) that includes a carrier amplification path having an output that includes a carrier transformer, and a peaking amplification path having an output that includes a peaking transformer. The Doherty PA further includes a combiner configured to combine the outputs of the carrier and peaking amplification paths into an output node.). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to combine Tsuchida’s teachings and Jin’s teachings in order to result in efficient power amplification in many wireless applications (Jin, par. 0006).
Regarding claim 5, Tsuchida and Jin teach all the limitations in claim 4. Tsuchida further teaches further comprising: a metal member that is disposed on the first main surface and disposed between the first transformer and the second power amplifier circuit in plan view of the module substrate (par. 0104; The planar line pattern is formed of a thin metal film, and thus has high heat resistance.).
Regarding claim 6, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches further comprising: a low noise amplifier circuit (par. 0157; low noise amplifiers 21 and 22.); and an inductor that is connected to the low now amplifier circuit and disposed on the first main surface, wherein a distance between the first transformer and the inductor is greater than a distance between the second transformer and the inductor (par. 0160; inductors or capacitors included in matching circuits 41 and 42 may be desirably integrated passive devices (IPDs) mounted on the surface or inside of a Si substrate.).
Regarding claim 7, Tsuchida and Jin teach all the limitations in claim 6. Tsuchida further teaches further comprising: a metal member that is disposed on the first main surface and disposed between the first transformer and the inductor in plan view of the module substrate (par. 0104).
Regarding claim 8, Tsuchida and Jin teach all the limitations in claim 7. Tsuchida further teaches further comprising: a resin member that covers at least part of the first power amplifier circuit and the second power amplifier circuit that are disposed on the first main surface (par. 0079); and a shield layer that covers at least part of a surface of the resin member, wherein a tip of the metal member is connected to the shield layer (par. 0079).
Regarding claim 9, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches further comprising: a matching circuit that is connected to the second transformer and disposed on the first main surface, wherein the matching circuit and the second transformer overlap at least partially in plan view of the module substrate (par. 0051; matching circuit 71 is disposed on a path that connects switch 54 and duplexer 61, and matches the impedance between (i) duplexer 61 and (ii) antenna 2 and switch 54. Matching circuit 72 is disposed on a path that connects switch 54 and duplexer 62, and matches the impedance between (i) duplexer 62 and (ii) antenna 2 and switch 54.).
Regarding claim 10, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches wherein the first transformer is formed at a plurality of first layers including the first main surface of the module substrate, wherein the second transformer is formed at a plurality of second layers including the second main surface of the module substrate, and wherein the plurality of first layers and the plurality of second layers do not overlap (par. 0096; he first circuit components disposed on principal surface 91b and output transformers 31 and 36 do not overlap in a plan view of module board 91.).
Regarding claim 11, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches wherein the first transformer is formed at a plurality of first layers including the first main surface of the module substrate, wherein the second transformer is formed at a plurality of second layers including the second main surface of the module substrate, and wherein the plurality of first layers and the plurality of second layers overlap at least partially (par. 0110).
Regarding claim 12, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches wherein the second transformer and the first transformer do not overlap in plan view of the module substrate (par. 0096; the first circuit components disposed on principal surface 91b and output transformers 31 and 36 do not overlap in a plan view of module board 91.).
Regarding claim 13, Tsuchida and Jin teach all the limitations in claim 1. Tsuchida further teaches wherein the second transformer and the first transformer overlap at least partially in plan view of the module substrate (par. 0108).
Regarding claim 14, Tsuchida and Jin teach all the limitations in claim 13. Tsuchida further teaches wherein the first transformer and the second transformer are disposed between the first power amplifier circuit and the second power amplifier circuit in plan view of the module substrate (Fig. 5; clearly shows the transformers between power amplifiers 11a 11b 12a 12b.).
Regarding claim 15, Tsuchida and Jin teach all the limitations in claim 2. Tsuchida further teaches further comprising: a low noise amplifier circuit (par. 0157; low noise amplifiers 21 and 22.); and an inductor that is connected to the low now amplifier circuit and disposed on the first main surface, wherein a distance between the first transformer and the inductor is greater than a distance between the second transformer and the inductor (par. 0160; inductors or capacitors included in matching circuits 41 and 42 may be desirably integrated passive devices (IPDs) mounted on the surface or inside of a Si substrate.).
Regarding claim 16, Tsuchida and Jin teach all the limitations in claim 15. Tsuchida further teaches further comprising: a metal member that is disposed on the first main surface and disposed between the first transformer and the inductor in plan view of the module substrate (par. 0104); a resin member that covers at least part of the first power amplifier circuit and the second power amplifier circuit that are disposed on the first main surface (par. 0079); and a shield layer that covers at least part of a surface of the resin member, wherein a tip of the metal member is connected to the shield layer (par. 0079).
Regarding claim 17, Tsuchida and Jin teach all the limitations in claim 4. Tsuchida further teaches further comprising: a low noise amplifier circuit (par. 0034; low noise amplifiers (LNAs) 21 and 22); and an inductor that is connected to the low now amplifier circuit and disposed on the first main surface, wherein a distance between the first transformer and the inductor is greater than a distance between the second transformer and the inductor (par. 0034; reception input matching circuit 40 which is an inductor that is connected to LNAs 21 22.).
Regarding claim 18, Tsuchida and Jin teach all the limitations in claim 17. Tsuchida further teaches further comprising: a metal member that is disposed on the first main surface and disposed between the first transformer and the inductor in plan view of the module substrate (par. 0104); a resin member that covers at least part of the first power amplifier circuit and the second power amplifier circuit that are disposed on the first main surface (par. 0079); and a shield layer that covers at least part of a surface of the resin member, wherein a tip of the metal member is connected to the shield layer (par. 0079).
Regarding claim 19, Tsuchida and Jin teach all the limitations in claim 2. Tsuchida further teaches further comprising: a matching circuit that is connected to the second transformer and disposed on the first main surface, wherein the matching circuit and the second transformer overlap at least partially in plan view of the module substrate, wherein the first transformer is formed at a plurality of first layers including the first main surface of the module substrate, wherein the second transformer is formed at a plurality of second layers including the second main surface of the module substrate, and wherein the plurality of first layers and the plurality of second layers do not overlap, or the plurality of first layers and the plurality of second layers overlap at least partially (par. 0096).
Regarding claim 19, Tsuchida and Jin teach all the limitations in claim 4. Tsuchida further teaches further comprising: a matching circuit that is connected to the second transformer and disposed on the first main surface, wherein the matching circuit and the second transformer overlap at least partially in plan view of the module substrate, wherein the first transformer is formed at a plurality of first layers including the first main surface of the module substrate, wherein the second transformer is formed at a plurality of second layers including the second main surface of the module substrate, and wherein the plurality of first layers and the plurality of second layers do not overlap, or the plurality of first layers and the plurality of second layers overlap at least partially (par. 0096).
Conclusion
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/AYODEJI O AYOTUNDE/Primary Examiner, Art Unit 2649