DETAILED ACTION
This action is in response to the Application filed on 12/13/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 1 – 2, 4, 11 – 12 and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over US Pub. No. 2006/0239046; (hereinafter Zane) in view of US Patent No. 10,381,918; (hereinafter Stoichita).
Regarding claim 1, Zane [e.g. Figs. 2 and 6] discloses a conversion control circuit for controlling a stackable sub-converter, wherein a plurality of the stackable sub-converters [e.g. 32, 34] are configured as a stackable multi-phase power converter [e.g. 30], wherein each of the plurality of the stackable sub-converters includes a power stage circuit [e.g. Fig. 6; 202] and a corresponding conversion control circuit [e.g. Fig. 6; 200], wherein a plurality of the power stage circuits corresponding to the plurality of the stackable sub-converters are coupled in parallel to generate an output power to a load [e.g. Fig. 2; Load], the output power including an output current [e.g. Fig. 2; IL], wherein the conversion control circuit is configured to control at least one switch [e.g. Fig. 6; high-side switch] of the power stage circuit to switch a corresponding inductor [e.g. Fig. 6; L], thereby generating the output power, wherein the conversion control circuit is configured as a master control circuit [e.g. master control for the phase converter] or a slave control circuit, wherein the plurality of the stackable sub-converters have a total phase number and an activated phase number [e.g. phases operate in an interleaved manner; paragraph 029], wherein the activated phase number is determined according to a level of the output current [e.g. Fig. 6; IL], wherein the conversion control circuit comprises: a current sharing terminal [e.g. digital bus], wherein a current sharing signal [e.g. Iave; paragraph 031 recites “The current-sharing information is a function of the current level being provided by at least one individual interleaved phase of the DC-DC converter. The current-sharing information placed on and/or received from the digital data bus, for example, may comprise collective current-sharing information of a plurality of individual interleaved phases (e.g., an average output current level of at least two interleaved phases or a function of the average output current level) or individual current-sharing information for a particular individual interleaved phase (e.g., an individual output current level of a single interleaved phase or a function of the individual output current level)”] is coupled to the current sharing terminals of the plural conversion control circuits that are coupled in parallel; a current sharing circuit [e.g. Fig.6; 210 and error calculating element], configured to generate and/or receive the current sharing signal, and to generate an adjustment signal [e.g. Fig. 6; ierror] according to a difference between the current sharing signal and a corresponding sub-current sensing signal [e.g. Isensed] to adjust at least one parameter of the conversion control circuit for current sharing between the plurality of the stackable sub-converters [e.g. Abstract recites “The controller is also configured to: (1) determine a current level being provided by said power stage, (2) update the current-sharing information based upon the determined current level, (3) determine a current error based upon the determined current level and the updated current-sharing information, (4) control an operation of said power stage based upon the current error, and (5) provide the updated current-sharing information to the data bus”], wherein the sub-current sensing signal is related to an inductor current [e.g. Fig. 6; IL] corresponding to the inductor; wherein the current sharing circuit includes the following configurations: (A): wherein the current sharing signal is generated only according to the corresponding inductor current of one of the plural inductors of the plurality of the stackable sub-converters [e.g. the multiphase operates in an interleaved manner, therefore the current sharing signal is generated according to only a corresponding inductor current of one of the plural phases as shown in Fig. 6]; or (B): wherein the current sharing signal is generated according to the plural inductor currents corresponding to the plural inductors of plural activated phases of the plurality of the stackable sub-converters, wherein a ratio of a portion of the current sharing signal generated by a master control circuit to a portion generated by each activated one of the slave control circuit or the slave control circuits is k which relates to a difference between a total phase number and the activated phase number.
Zane fails to disclose wherein the sub-converters are stackable.
Stoichita [e.g. Fig. 3] teaches wherein the sub-converters are stackable [e.g. Single-Output Stacked Configuration (Fig. 3)].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zane by wherein the sub-converters are stackable as taught by Stoichita in order of being able to accommodate a desired layout.
Regarding claim 2, Zane [e.g. Figs. 2 and 6] discloses wherein in configuration (A), the current sharing signal is generated only according to the inductor current corresponding to the master control circuit [e.g. Fig. 6; 200].
Regarding claim 4, Zane fails to disclose wherein in the configuration (B), the current-sharing circuit of each of the master control circuit and the slave control circuit generates the corresponding adjustment signal to correspondingly adjust at least one parameter, for current sharing between the plurality of the stackable sub-converters. However, the configuration (B) is not required according to claim 1.
Regarding claim 11, Zane [e.g. Figs. 2 and 6] discloses a control method, for controlling a stackable sub-converter, wherein a plurality of the stackable sub-converters [e.g. 32, 34] are configured as a stackable multi-phase power converter [e.g. 30], wherein each of the plurality of the stackable sub-converters includes a power stage circuit [e.g. Fig. 6; 202], wherein a plurality of the power stage circuits corresponding to the plurality of the stackable sub-converters are coupled in parallel to generate an output power to a load [e.g. Fig. 2; Load], wherein the power stage circuit includes at least one switch [e.g. Fig. 6; high-side switch] for switching a corresponding inductor [e.g. Fig. 6; L], thereby generating the output power, wherein the plurality of the stackable sub-converters have a total phase number and an activated phase number [e.g. phases operate in an interleaved manner; paragraph 029], wherein the control method comprises: controlling the at least one switch [e.g. high side switch (Fig. 6)] of the power stage circuit for switching the corresponding inductor; generating or receiving a current sharing signal [e.g. digital bus] by each of the plurality of the stackable sub-converters [e.g. Iave; paragraph 031 recites “The current-sharing information is a function of the current level being provided by at least one individual interleaved phase of the DC-DC converter. The current-sharing information placed on and/or received from the digital data bus, for example, may comprise collective current-sharing information of a plurality of individual interleaved phases (e.g., an average output current level of at least two interleaved phases or a function of the average output current level) or individual current-sharing information for a particular individual interleaved phase (e.g., an individual output current level of a single interleaved phase or a function of the individual output current level)”]; and performing current sharing between the plurality of the stackable sub-converters according to the current sharing signal [e.g. Abstract recites “The controller is also configured to: (1) determine a current level being provided by said power stage, (2) update the current-sharing information based upon the determined current level, (3) determine a current error based upon the determined current level and the updated current-sharing information, (4) control an operation of said power stage based upon the current error, and (5) provide the updated current-sharing information to the data bus”]; wherein the step of generating the current sharing signal includes the following configurations: (A): generating the current sharing signal only according to the corresponding inductor current of one of the plural inductors of the plurality of the stackable sub-converters [e.g. the multiphase operates in an interleaved manner, therefore the current sharing signal is generated according to only a corresponding inductor current of one of the plural phases as shown in Fig. 6]; or (B): generating the current sharing signal according to the plural inductor currents corresponding to the plural inductors of plural activated phases of the plurality of the stackable sub-converters, wherein a ratio of a portion of the current sharing signal generated by a master control circuit to a portion generated by each activated one of the slave control circuit or the slave control circuits is k which relates to a difference between a total phase number and the activated phase number.
Zane fails to disclose wherein the sub-converters are stackable; wherein one of the plurality of the stackable sub-converters is configured as a master stackable sub-converter, and each other of the plurality of the stackable sub-converters is configured as a slave stackable sub-converter.
Stoichita [e.g. Fig. 3] teaches wherein the sub-converters are stackable [e.g. Single-Output Stacked Configuration (Fig. 3)]; wherein one of the plurality of the stackable sub-converters is configured as a master stackable sub-converter [e,g. Master (Fig. 3)], and each other of the plurality of the stackable sub-converters is configured as a slave stackable sub-converter [e.g. Slave (Fig. 3)].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zane by wherein the sub-converters are stackable; wherein one of the plurality of the stackable sub-converters is configured as a master stackable sub-converter, and each other of the plurality of the stackable sub-converters is configured as a slave stackable sub-converter as taught by Stoichita in order of being able to accommodate a desired layout.
Regarding claim 12, Zane [e.g. Figs. 2 and 6] discloses wherein in the configuration (A), the current sharing signal is generated only according to the inductor current corresponding to the sub-converter [e.g. Fig. 6; 200].
Zane fails to disclose wherein the sub-converter is a master stackable sub-converter.
Stoichita [e.g. Fig. 3] teaches wherein the sub-converter is a master stackable sub-converter [e.g. Master of Single-Output Stacked Configuration (Fig. 3)].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Zane by wherein the sub-converter is a master stackable sub-converter as taught by Stoichita in order of being able to accommodate a desired layout.
Regarding claim 14, Zane fails to disclose wherein in the configuration (B), generating a corresponding adjustment signal for each of the master stackable sub-converter and the slave stackable sub-converter to correspondingly adjust at least one parameter, for current sharing between the plurality of the stackable sub-converters. However, the configuration (B) is not required according to claim 1.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claim(s) 3, 5 – 10, 13 and 15 – 19 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 3 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the current sharing circuit of the master control circuit does not generate the adjustment signal and does not adjust the at least one parameter of the conversion control circuit, wherein the current sharing circuit of each slave control circuit generates the adjustment signal to adjust the corresponding at least one parameter for current sharing between the plurality of the stackable sub-converters”.
The primary reason for the indication of the allowability of claim 5 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the conversion control circuit controls at least one switch of one of the plurality of the stackable sub-converters using a constant time, wherein the constant time is determined according to a threshold voltage, an integral capacitance value, or an integral current; wherein the adjustment signal is configured to adjust the at least one parameter to modify the constant time for current sharing between the plurality of the stackable sub-converters, wherein the at least one parameter includes at least one of the threshold voltage, the integral capacitance value, and the integral current”.
The primary reason for the indication of the allowability of claim 7 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the conversion control circuit further comprises: a sync terminal, wherein a sync signal is coupled to the sync terminals of the plural conversion control circuits that are coupled in parallel; wherein the sync signal includes plural pulses, the plural pulses are continuously counted as a counting value, wherein the sync signal includes a reset signal for resetting and initiating the counting value; wherein when the counting value is related to a phase sequence number corresponding to the conversion control circuit, the conversion control circuit enables the corresponding power stage circuit to generate the output power; wherein the master control circuit is configured to generate the sync signal via the sync terminal, and the slave control circuit is configured to receive the sync signal via the sync terminal”.
The primary reason for the indication of the allowability of claim 10 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the conversion control circuit is configured as an integrated circuit, wherein the sync terminal corresponds to a sync pin of the integrated circuit, and the current sharing terminal corresponds to a current sharing pin of the integrated circuit.
The primary reason for the indication of the allowability of claim 13 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the power stage circuit of the master stackable sub-converter is not adjusted, wherein the corresponding power stage circuit of each slave stackable sub-converter is adjusted to adjust the corresponding at least one parameter for current sharing between the plurality of the stackable sub-converters.
The primary reason for the indication of the allowability of claim 15 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: controlling at least one switch of one of the plurality of the stackable sub-converters using a constant time, wherein the constant time is determined according to a threshold voltage, an integral capacitance value, or an integral current; and adjusting at least one parameter to modify the constant time for current sharing between the plurality of the stackable sub-converters, wherein the at least one parameter includes at least one of the threshold voltage, the integral capacitance value, and the integral current.
The primary reason for the indication of the allowability of claim 17 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “further comprising: generating a sync signal by the master stackable sub-converter; receiving the sync signal by the slave stackable sub-converter, wherein the sync signal includes plural pulses, the plural pulses are continuously counted as a counting value, wherein the sync signal includes a reset signal for resetting and initiating the counting value; and enabling a corresponding power stage circuit to generate the output power when the counting value is related to a corresponding phase sequence number.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Alex Torres-Rivera whose telephone number is (571)272-5261. The examiner can normally be reached M-F 9:00-5:30 ET.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, MONICA LEWIS can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838