DETAILED ACTION
The present application, filed on or after March 16, 2013, is being examined under the
first inventor to file provisions of the AIA .
This action is responsive to the application filed 12/13/2023.
Claims 1-20 are presented for examination. Claims 1, 9, and 16 are independent Claims.
Priority
2. Receipt is acknowledged of papers submitted under 35 U.S.C. 119(a)-(d), and based on application # 202310146042.5 filed in CHINA on 02/21/2023, which papers have been placed of record in the file.
Drawings
3. The drawings filed 12/13/2023 are acceptable for examination purposes.
Allowable Subject Matter
4. Claims 8 and 15 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims, subject to the results of a final search by the Examiner.
Claim Rejections - 35 USC § 102
5. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-7, 9-14, and 16-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by ZHANG et al. (US 20220121903).
As to Claim 1:
ZHANG teaches a processing circuit (Abstract and Fig.2) for an artificial intelligence (AI) model, the processing circuit being coupled to an external memory and comprising: a memory; a memory management circuit configured to read a tensor from the external memory and store the tensor in the memory; and an operation circuit configured to:
perform an operation of a first type on a first sub-tensor of the tensor to generate a first intermediate data ([0005-0006], [0056-0058], and [0123]);
perform the operation of the first type on a second sub-tensor of the tensor to generate a second intermediate data ([0007-0012], [0056-0058], and [0123]);
perform an operation of a second type on the first intermediate data and the second intermediate data to generate a third intermediate data ([0021], [0056-0058], and [0123]);
perform the operation of the first type on a third sub-tensor of the tensor to generate a fourth intermediate data ([0056-0058, and [0072-0074], and [0123]); and
perform the operation of the second type on the first intermediate data, the second intermediate data, and the fourth intermediate data to generate a fifth intermediate data ([0056-0058], [0072-0074], and [0123]).
As to Claim 2:
ZHANG teaches memory management circuit stores the first intermediate data and the second intermediate data in the memory and deletes the first intermediate data from the memory after the fifth intermediate data is generated ([0153-0155]).
As to Claim 3:
ZHANG teaches the operation of the first type is one of an addition operation and a subtraction operation, and the operation of the second type is a convolution operation ([0058], [0081], and [0089]).
As to Claim 4:
ZHANG teaches the first intermediate data, the second intermediate data, and the fourth intermediate data correspond to a same dimension of the tensor ([0074] and [0093-0094]).As to Claim 5:
ZHANG teaches the fourth intermediate data is generated after the third intermediate data is generated ([0165] and [0192-0194]).
As to Claim 6:
ZHANG teaches a buffer circuit; wherein when the operation circuit performs the operation of the first type, the memory management circuit reads at least one subset of kernel parameters from the memory to the buffer circuit, and the operation circuit refers to only the at least one subset of the kernel parameters to perform the operation of the first type; wherein the operation of the first type is one of a subtraction operation and an addition operation ([0074] and [0132]).As to Claim 7:
ZHANG teaches the first intermediate data, the second intermediate data, and the fourth intermediate data are of a same size ([0089-0090]).
As to Claim 9:
ZHANG teaches a processing circuit for an artificial intelligence (AI) model (Abstract and Fig.2), the processing circuit being coupled to an external memory, comprising a memory, and performing following operations:
reading a tensor and a plurality of kernel parameters from the external memory and storing the tensor and the kernel parameters in the memory, wherein the tensor includes a first sub-tensor and a second sub-tensor, and the kernel parameters include vector kernel parameters ([0042-0046] and [0072-0074]);
performing a first vector operation on the first sub-tensor with reference to a first subset of the vector kernel parameters to generate a first intermediate data ([0005-0006], [0056-0058], and [0123]); and
performing a second vector operation on the second sub-tensor with reference to a second subset of the vector kernel parameters to generate a second intermediate data ([0007-0012], [0056-0058], and [0123]);
wherein the first subset of the vector kernel parameters is different from the second subset of the vector kernel parameter ([0064] and [0074]).
As to Claim 10:
ZHANG teaches the tensor further comprises a third sub-tensor ([0056-0057]), and the kernel parameters further comprise convolution kernel parameters for a convolution operation, the processing circuit further performing following operations: performing the convolution operation on the first intermediate data and the second intermediate data with reference to the convolution kernel parameters to generate a third intermediate data ([0021], [0056-0058], and [0123]); and performing a third vector operation on the third sub-tensor with reference to a third subset of the vector kernel parameters to generate a fourth intermediate data after the convolution operation ([0165] and [0192-0194]).
As to Claim 11:
ZHANG teaches the convolution operation is a first convolution operation, the processing circuit further performing following operations: performing a second convolution operation on the first intermediate data, the second intermediate data, and the fourth intermediate data with reference to the convolution kernel parameters ([0056-0058], [0072-0074], and [0123]).
As to Claim 12:
ZHANG teaches the first intermediate data is stored in the memory, the processing circuit further performing following operations: deleting the first intermediate data from the memory after the second convolution operation is performed ([0153-0155]).
As to Claim 13:
ZHANG teaches the first sub-tensor and the second sub-tensor correspond to a same dimension of the tensor ([0074] and [0093-0094]).As to Claim 14:
ZHANG teaches the first vector operation and the second vector operation are one of an addition operation and a subtraction operation ([0058], [0081], and [0089]).As to Claim 16:
ZHANG teaches a computation scheduling method for an artificial intelligence (AI) model (Abstract, [0021], and [0057]) that comprises a first operator and a second operator, the computation scheduling method comprising:
splitting a tensor into H sub-tensors, wherein H is an integer greater than one ([0056-0058] and [0143]);
splitting the first operator into H first sub-operators ([0005-0006], [0056-0058], and [0123]);
splitting the second operator into H second sub-operators ([0007-0012], [0056-0058], and [0123]);
determining a dependency relationship among the H first sub-operators and the H second sub-operators ([0074] and [0123]);
sorting the H first sub-operators and the H second sub-operators according to the dependency relationship to obtain an operation order ([0123-0128]); and
determining, according to the operation order, when a processing circuit executing the AI model deletes a target data from a memory included in the processing circuit, the target data being an output data of one of the H first sub-operators and the H second sub-operators ([0123-0124]).
As to Claim 17:
ZHANG teaches the step of determining the dependency relationship among the H first sub-operators and the H second sub-operators comprises: determining a target sub-operator; determining a source sub-operator of the target sub-operator, wherein an output of the source sub-operator is an input of the target sub-operator; and determining that the target sub-operator depends on the source sub-operator ([0074] and [0123-0128]);
As to Claim 18:
ZHANG teaches the step of sorting the H first sub-operators and the H second sub-operators according to the dependency relationship to obtain the operation order comprises: (A) determining a target sub-operator; (B) determining a source sub-operator on which the target sub-operator depends; (C) adding the source sub-operator to a queue when the source sub-operator does not depend on any sub-operator; (D) repeating step (B) to step (C) until all of the source sub-operators on which the target sub-operator depends have been added to the queue; and (E) adding the target sub-operator to the queue ([0063] and [0123-0128]).
As to Claim 19:
ZHANG teaches the step of sorting the H first sub-operators and the H second sub-operators according to the dependency relationship to obtain the operation order further comprises: (F) determining an upper-level sub-operator that depends on the target sub-operator; (G) using the upper-level sub-operator as the target sub-operator and repeating step (B) to step (E); and (H) repeating step (F) and step (G) until the target sub-operator is a top-level sub-operator ([0123-0128]).
As to Claim 20:
ZHANG teaches the step of determining when to delete the target data from the memory according to the operation order comprises: determining, according to the queue, a sub-operator that is the last to use the target data, the sub-operator being one of the H first sub-operators and the H second sub-operators; wherein the target data is deleted after an operation of the sub-operator is completed ([0153-0155]).
Conclusion
6. The prior art made of record, listed on PTO 892 provided to Applicant is considered to have relevancy to the claimed invention. Applicant should review each identified reference carefully before responding to this office action to properly advance the case in light of the prior art.
Contact information
7. Any inquiry concerning this communication or earlier communications from the
examiner should be directed to MAIKHANH NGUYEN whose telephone number is (571) 272-4093. The examiner can normally be reached on Monday-Friday (8:00 am – 5:30 pm). If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, TAMARA KYLE can be reached at (571)272-4241.
The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/MAIKHANH NGUYEN/Primary Examiner, Art Unit 2144
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