DETAILED ACTION
Response to Arguments
Applicant’s arguments, filed 06/24/2026, with respect to the rejection of claims 1 and 8 under 35 USC 103 have been fully considered and a new ground of rejection is made in view of Chen et al. (US 2022/0157956 A1; hereinafter “Chen956”). Further due to the contents of the amendment a 35 USC 112(a) rejection has been made due to new matter.
Applicant’s arguments, filed 06/24/2026, with respect to the rejection of claim 15 under 35 USC 102 have been fully considered and due to the contents of the amendment a 35 USC 112(a) rejection has been made due to new matter.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the portions of the backside contact structures must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claims contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention. The following limitations were are not described in the specification:
Claim 1: a first portion below a second portion, wherein a width of the first portion increases relative to a height of the backside contact structure, and wherein a width of the second portion decreases relative to the height of the backside contact structure (lns. 2-5).
Claim 8: wherein a width of a first portion of the backside contact structure increases relative to a height of the backside contact structure, wherein a width of a second portion of the backside contact structure decreases relative to the height of the backside contact structure . . . wherein a bottommost surface of the placeholder is entirely above the first portion of the backside contact structure (lns. 3-6 and 8-9).
Claim 11: wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region (lns.3-4).
Claim 14: wherein a topmost surface of the backside contact structure is above a topmost surface of the placeholder and directly contacts a sidewall of an inner spacer.
Claim 15: a first portion directly on top of a second portion and a third portion directly on top of the second portion, wherein a first width of the first portion increases relative to a height of the backside contact structure, wherein a second width of the second portion decreases relative to the height of the backside contact structure, and wherein a third width of the third portion is substantially equal to a width of the first source drain region… wherein a width of a top portion of the placeholder is greater than a width of a bottom portion of the placeholder, and wherein the top portion of the placeholder is above a topmost surface of a backside dielectric layer and the bottom portion is below the topmost surface of a backside dielectric layer (lns.3-6 and lns.9-12).
The aforementioned amendments solely rely on the drawings with no written description. While generally information contained in any one of the specification, claims or drawings of the application as filed may be added to any other part of the application without introducing new matter (see MPEP 2163.06). The specification explicitly states “the drawings are not necessarily to scale. The drawings are merely schematic representations, not intended to portray specific parameters of the invention. For clarity and ease of illustration, scale of elements may be exaggerated. The drawings are intended to depict only typical embodiments of the invention. In the drawings, like numbering represents like elements” (see paragraph 17 of the instant application). Therefore, the drawings are not reliable source of information regarding the dimensions of the device without a supporting written description. Therefore claims 1, 8, 15 and all claims depending therefrom are rejected under 35 U.S.C 112(a).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1 and 3 are rejected under 35 U.S.C. 103 as being unpatentable over Yun et al. (US 2024/0395900 A1; hereinafter “Yun”), in view of Chen et al. (US 2022/0157956 A1; hereinafter “Chen956”).
In regard to claim 1, Yun teaches a nanosheet semiconductor structure (a semiconductor device 20 containing a plurality of nanosheet channel layers 110) (Fig. 2 and paragraphs 6 and 37), comprising:
a backside contact structure (backside source/drain contact structures BC1-BC3),
wherein the backside contact structure comprises a first portion below a second portion (a first portion of the backside source/drain contact structures BC1-BC3 is annotated as FP in Fig. 2 below, and is shown below a second portion annotated as SP) (annotated Fig. 2 below), wherein a width of the first portion increases relative to a height of the backside contact structure (the width of the first portion FP of the backside source/drain contact structures BC1-BC3 is shown increasing in relative to the height of the backside source/drain contact structures BC1-BC3 as shown in Fig. 2),
a placeholder (placeholder structures P1 and P4) adjacent to the backside contact structure and directly beneath a source drain region (the placeholder structures P1 and P4 are formed under source/drain regions SD1 and SD4) (Fig. 2 and paragraph 42); and
a dielectric liner (a contact spacer 103) surrounding a bottom portion of the placeholder (a bottom spacer 103B surrounds each of the backside source/drain contact structures BC1-BC3) (Fig. 2 and paragraphs 44).
However, Yun doesn’t explicitly teach and wherein a width of the second portion decreases relative to the height of the backside contact structure.
Chen956 teaches a nanosheet semiconductor structure (an integrated chip comprising a nanosheet field effect transistor (NSFET)) (Fig. 1A and paragraph 19), wherein a width of a second portion (a portion of the backside contact 122 above the widest portion as shown in Fig. 22B) decreases relative to the height of the backside contact structure (as shown Fig. 22B the dummy source/drain material 1604 which is removed to form the backside contact 122, may have an exposed surface 1604s that is not a maximum width of the dummy source/drain material 1604. In such embodiments, the exposed surface 1604s of the dummy source/drain material 1604 has a second width w2 that is between a maximum width and a minimum width of the dummy source/drain material 1604i. Therefore, the portion of the backside contact 122 has a width that decreases from the widest portion wo the smallest first width w1 as shown in Fig. 24) (Fig. 24 and paragraphs 88-92).
It would’ve been obvious to one skilled in the art to combine the teachings of Yun with the teachings of Chen956 to have a width of the second portion decreases relative to the height of the backside contact structure since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
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In regard to claim 3, Yun teaches stack spacers (side spacer 103A) between and physically separating the backside contact structure from the one or more gates (the side spacers 103A are shown between the backside source/drain contact structures BC1-BC3 and gate structures G1-G6 in Fig. 2) (Fig. 2 and paragraph 45).
Claims 2, 4, and 7 are rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 as applied to claims 1, and further in view of Lee et al. (US 2024/0421154 A1; hereinafter “Lee”)
In regard to claim 2, Yun in view of Chen956 don’t explicitly teach a buffer layer between and physically separating the placeholder from the source drain region and wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region.
Lee teaches a semiconductor structure (an integrated circuit device 100) (Fig. 2A and paragraph 16), further comprising: a buffer layer (a conductive layer 222) between and physically separating a placeholder from source drain region (the conductive layer 222 may be in the first interlayer 210 between each of the placeholders 216 and a respective one of the second, third, and fourth source/drain regions 102b, 102c, and 102d) (Fig. 2A and paragraph 42).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen with the teachings of Lee to have a buffer layer between and physically separating the placeholder from the source drain region since this layer can facilitate connections of power networks to the source and drain regions as taught by Lee (paragraph 6).
In regard to claim 4, Yun in view of Chen956 don’t explicitly teach wherein a bottommost surface of the backside contact structure is substantially flat and directly contacts a backside power rail, and wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region, and wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region.
Lee teaches wherein a bottommost surface of a backside contact structure (a backside contact 218 including a conductive plug 220 may be collectively referred to as a backside contact structure) is substantially flat and directly contacts a backside power rail (the backside contact structure is shown to be flat and contacting a power 226) (Fig. 2A and paragraphs 36-37), and wherein a dielectric liner (a lower portion 217 of the substrate 212) directly contacts both a topmost surface of backside power rail (a backside power rail 226) and a bottommost surface of a shallow trench isolation region (the lower portion 217 of the substrate 212 is shown contacting the top surface of the backside power rail 226 and bottom surface of a trench isolation layer 232 in Fig. 2B) (Fig. 2A, Fig. 2B and paragraphs 18, 28 and 35).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 with the teachings of Lee to have bottommost surface of the backside contact structure is substantially flat and directly contacts a backside power rail since this layout is well known to allow connections to the a backside power distribution network structure (BSPDNS) within the device while maintaining protection against unwanted shorts as taught by Lee (paragraph 6).
In regard to claim 7, Yun in view of Chen956 don’t explicitly teach wherein the backside contact structure is made from a metal, and wherein a topmost surface of the metal of the backside contact structure is above a topmost surface of the placeholder.
Lee teaches wherein the backside contact structure is made from a metal (a conductive layer 222, a backside contact 218, and a conductive plug 220 and may be collectively referred to as a backside contact structure and the conductive layer 222 may include a metal silicide layer or a metallic nitride layer) (paragraph 34), wherein a topmost surface of the metal of a backside contact structure is above a topmost surface of a placeholder (the backside contact structure is shown to have upper most surface above than the placeholder 216 due to the backside contact structure containing the conductive layer 222) (Fig. 2A and paragraphs 36 and 41).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 with the teachings of Lee to have a topmost surface of the backside contact structure above a topmost surface of the placeholder since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. Indeed, it has been held that mere dimensional limitations are prima facie obvious absent a disclosure that the limitations are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 as applied to claim 1 above, and further in view of Chen et al. (US 2022/0131004 A1; hereinafter “Chen”).
In regard to claim 5, Yun in view of Chen956 don’t explicitly teach wherein the backside contact structure is self-aligned to adjacent shallow trench isolation regions.
Chen teaches a semiconductor structure (a workpiece 200) (Fig. 4A and paragraph 13), wherein a backside contact structure (backside contacts 270) is self-aligned to adjacent shallow trench isolation regions (the backside contact is shown aligned with an isolation feature 204 in Fig. 4A) (Fig. 4A and paragraphs 15 and 24). Furthermore the examiner notes the limitation “the backside contact structure is self-aligned to adjacent shallow trench isolation regions” is a process limitation as the term self-alignment refers to aspects of the backside contact 270 during the manufacture of the device. The presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). Therefore, a device with a backside contact aligned with adjacent shallow trench isolation regions meets the claim limitation.
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 with the teachings of Chen to have the backside contact structure is self-aligned to adjacent shallow trench isolation regions as this layout allows for proper separation of elements within the device and avoids unwanted shorts.
Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 as applied to claim 1 above, and further in view of Lee et al. (US 2020/0357703 A1; hereinafter “Lee703”).
In regard to claim 6, Yun teaches wherein the dielectric liner comprises a substantially conformal and uniform thickness (the side spacer 103A is shown to be conformal and have a uniform thickness TH1 in Fig. 2) (Fig. 2 and paragraph 48).
However, Yun in view of Chen956 doesn’t explicitly teach the dielectric liner is further disposed along sidewalls and bottoms of shallow trench isolation regions.
Lee703 teaches a nanosheet semiconductor structure (a semiconductor structure 100) (Fig. 1 and paragraph 28), further disposed along sidewalls and bottoms of shallow trench isolation regions (a first liner 302, second liner 304, and third liner 306 together form a tri-layer STI liner) (Fig. 4 and paragraph 45).
It would’ve been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 and Lee 703 to have the dielectric liner further disposed along sidewalls and bottoms of shallow trench isolation regions, since this allows for protection of the nanosheets during device formation as taught by Lee703 (paragraph 24).
Claims 8-11 are rejected under 35 U.S.C. 103 as being unpatentable over Yun, in view of Chen956 and Lee.
In regard to claim 8, Yun teaches a nanosheet semiconductor structure (a semiconductor device 20 containing a plurality of nanosheet channel layers 110) (Fig. 2 and paragraphs 6 and 37), comprising:
a backside contact structure (backside source/drain contact structures BC1-BC3) extending laterally in a direction perpendicular to one or more gates (the width of the first portion FP of the backside source/drain contact structures BC1-BC3 are shown to be extending laterally due to their shape as shown in annotated Fig. 2 above) (annotated Fig. 2 and paragraph 38),
wherein a width of a first portion of the backside contact structure increases relative to a height of a backside contact structure (the width of the first portion FP of the backside source/drain contact structures BC1-BC3 is shown increasing in relative to the height of the backside source/drain contact structures BC1-BC3 as shown in annotated Fig. 2 above),
a placeholder (placeholder structures P1 and P4) adjacent to a backside contact structure and directly beneath a source drain region (the placeholder structures P1 and P4 are formed under source/drain regions SD1 and SD4) (Fig. 2 and paragraph 42); and
a dielectric liner surrounding a bottom portion of the placeholder (a contact spacer 103 may include a side spacer 103A and a bottom spacer 103B which a bottom spacer 103B surrounds each of the backside source/drain contact structures BC1-BC3) (Fig. 2 and paragraphs 44).
Yun doesn’t explicitly teach wherein a width of a second portion of the backside contact structure decreases relative to the height of the backside contact structure; wherein a bottommost surface of the placeholder is entirely above the first portion of the backside contact structure.
Chen956 teaches a nanosheet semiconductor structure (an integrated chip comprising a nanosheet field effect transistor (NSFET)) (Fig. 1A and paragraph 19), wherein a width of a second portion (a portion of the backside contact 122 above the widest portion as shown in Fig. 22B) decreases relative to the height of the backside contact structure (as shown Fig. 22B the dummy source/drain material 1604 which is removed to form the backside contact 122, may have an exposed surface 1604s that is not a maximum width of the dummy source/drain material 1604. In such embodiments, the exposed surface 1604s of the dummy source/drain material 1604 has a second width w2 that is between a maximum width and a minimum width of the dummy source/drain material 1604i. Therefore, the portion of the backside contact 122 has a width that decreases from the widest portion wo the smallest first width w1 as shown in Fig. 24) (Fig. 24 and paragraphs 88-92).
It would’ve been obvious to one skilled in the art to combine the teachings of Yun with the teachings of Chen956 to have a width of the second portion decreases relative to the height of the backside contact structure since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Lee teaches a nanosheet semiconductor structure (an integrated circuit device 100) (Fig. 2A and paragraph 16), wherein a bottommost surface of a placeholder (placeholders 216) is entirely above a first portion of the backside contact structure (a conductive plug 220. Functions as the first portion of the backside contact structure and is shown below the placeholders 216 in Fig. 2A) (Fig. 2A and paragraphs 36 and 44).
It would’ve been obvious to one skilled in the art to combine the teachings of Yun with the teachings of Lee to have a bottommost surface of the placeholder is entirely above the first portion of the backside contact structure since the further the separation of the backside contact and the placeholder, the more the parasitic capacitance between components is reduced or eliminated as taught by Lee (paragraph 50).
In regard to claim 9, Yun in view of Chen956 don’t explicitly teach a buffer layer between and physically separating the placeholder from the source drain region.
Lee teaches a semiconductor structure (an integrated circuit device 100) (Fig. 2A and paragraph 16), further comprising: a buffer layer (a conductive layer 222) between and physically separating a placeholder from source drain region (the conductive layer 222 may be in the first interlayer 210 between each of the placeholders 216 and a respective one of the second, third, and fourth source/drain regions 102b, 102c, and 102d) (Fig. 2A and paragraph 42).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 with the teachings of Lee to have a buffer layer between and physically separating the placeholder from the source drain region since this layer can facilitate connections of power networks to the source and drain regions as taught by Lee (paragraph 6).
In regard to claim 10, Yun teaches stack spacers (bottom isolation layer 102) between and physically separating the backside contact structure from the one or more gates (the bottom isolation layer 102 are shown between the backside source/drain contact structures BC1-BC3 and gate structures G1-G6 in Fig. 2) (Fig. 2 and paragraph 9).
In regard to claim 11, Yun in view of Chen956 don’t explicitly teach wherein a bottommost surface of the backside contact structure is substantially flat and directly contacts a backside power rail, and wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region, and wherein the dielectric liner directly contacts both a topmost surface of the backside power rail and a bottommost surface of a shallow trench isolation region.
Lee teaches wherein a bottommost surface of a backside contact structure (a backside contact 218 including a conductive plug 220 may be collectively referred to as a backside contact structure) is substantially flat and directly contacts a backside power rail (the backside contact structure is shown to be flat and contacting a power 226) (Fig. 2A and paragraphs 36-37), and wherein a dielectric liner (a lower portion 217 of the substrate 212) directly contacts both a topmost surface of backside power rail (a backside power rail 226) and a bottommost surface of a shallow trench isolation region (the lower portion 217 of the substrate 212 is shown contacting the top surface of the backside power rail 226 and bottom surface of a trench isolation layer 232 in Fig. 2B) (Fig. 2A, Fig. 2B and paragraphs 18, 28 and 35).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 with the teachings of Lee to have bottommost surface of the backside contact structure is substantially flat and directly contacts a backside power rail since this layout is well known to allow connections to the a backside power distribution network structure (BSPDNS) within the device while maintaining protection against unwanted shorts as taught by Lee (paragraph 6).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 and Lee as applied to claim 8 above, and further in view of Chen et al. (US 2022/0131004 A1; hereinafter “Chen”).
In regard to claim 12, Yun in view of Chen956 and Lee don’t explicitly teach wherein the backside contact structure is self-aligned to adjacent shallow trench isolation regions.
Chen teaches a semiconductor structure (a workpiece 200) (Fig. 4A and paragraph 13), wherein a backside contact structure (backside contacts 270) is self-aligned to adjacent shallow trench isolation regions (the backside contact is shown aligned with an isolation feature 204 in Fig. 4A) (Fig. 4A and paragraphs 15 and 24). Furthermore the examiner notes the limitation “the backside contact structure is self-aligned to adjacent shallow trench isolation regions” is a process limitation as the term self-alignment refers to aspects of the backside contact 270 during the manufacture of the device. The presence of process limitations on product claims, which product does not otherwise patentably distinguish over prior art, cannot impart patentability to the product. In re Stephens 145 USPQ 656 (CCPA 1965). Therefore, a device with a backside contact aligned with adjacent shallow trench isolation regions meets the claim limitation.
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 and Lee with the teachings of Chen to have the backside contact structure is self-aligned to adjacent shallow trench isolation regions as this layout allows for proper separation of elements within the device and avoids unwanted shorts.
Claim 13 is rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 and Lee as applied to claim 8 above, and further in view of Lee et al. (US 2020/0357703 A1; hereinafter “Lee703”).
In regard to claim 13, Yun teaches wherein the dielectric liner comprises a substantially conformal and uniform thickness (the side spacer 103A is shown to be conformal and have a uniform thickness TH1 in Fig. 2) (Fig. 2 and paragraph 48).
However, Yun in view of Chen956 and Lee doesn’t explicitly teach the dielectric liner is further disposed along sidewalls and bottoms of shallow trench isolation regions.
Lee703 teaches a nanosheet semiconductor structure (a semiconductor structure 100) (Fig. 1 and paragraph 28), further disposed along sidewalls and bottoms of shallow trench isolation regions (a first liner 302, second liner 304, and third liner 306 together form a tri-layer STI liner) (Fig. 4 and paragraph 45).
It would’ve been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 and Lee with the teachings of Lee703 to have the dielectric liner further disposed along sidewalls and bottoms of shallow trench isolation regions, since this allows for protection of the nanosheets during device formation as taught by Lee703 (paragraph 24).
Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Yun in view of Chen956 and Lee as applied to claim 8 above, and further in view of Park et al. (US 2024/0413213 A1; hereinafter “Park”).
In regard to claim 14, Yun in view of Chen956 and Lee doesn’t explicitly teach wherein a topmost surface of the backside contact structure is above a topmost surface of the placeholder and directly contacts a sidewall of an inner spacer.
Park teaches a nanosheet semiconductor structure (a 3D-stacked semiconductor device) (Fig. 5 and paragraph 19), wherein a topmost surface of a backside contact structure (a top surface of a backside contact structure 133) is above a topmost surface of a placeholder (a backside isolation structure 131) and directly contacts a sidewall of an inner spacer (the top surface of a backside contact structure 133 is shown above the backside isolation structure 131 and contacting lower inner spacers 116 in Fig. 5) (Fig. 5 and paragraphs 39, 62, 77 and 95).
It would have been obvious to one skilled in the art to combine the teachings of Yun in view of Chen956 and Lee with the teachings of Park to have a topmost surface of the backside contact structure above a topmost surface of the placeholder and directly contacting a sidewall of an inner spacer since it would have been an obvious matter of design choice bounded by well-known manufacturing constraints and ascertainable by routine experimentation and optimization to choose these particular dimensions because applicant has not disclosed that the dimensions are for a particular unobvious purpose, produce an unexpected result, or are otherwise critical, and it appears prima facie that the process would possess utility using another dimension. See, for example, In re Rose, 220 F.2d 459, 105 USPQ 237 (CCPA 1955); In re Rinehart, 531 F.2d 1048, 189 USPQ 143 (CCPA 1976); Gardner v. TEC Systems, Inc., 725 F.2d 1338, 220 USPQ 777 (Fed. Cir. 1984), cert. denied, 469 U.S. 830, 225 USPQ 232 (1984); In re Dailey, 357 F.2d 669, 149 USPQ 47 (CCPA 1966).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
Lin et al. (US 20230369456 A1)
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/Supervisory Patent Examiner, Art Unit 2893
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