DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Acknowledgment is made of Applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d). However, should Applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Drawings
The drawing objection as previously issued has been withdrawn.
Specification
The specification objects as previously issued have been withdrawn due to Applicant’s amendments dated June 25th, 2026.
Claim Objections
The claim objection (e.g., the objection to Claim 1) as previously issued has been withdrawn due to Applicant’s amendments dated June 25th, 2026.
Claim Rejections - 35 USC § 112
The 35 U.S.C. § 112 rejection as previously issued has been withdrawn due to Applicant’s amendments dated June 25th, 2026.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. § 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 1-15 are rejected under 35 U.S.C. 103 as being unpatentable over Choi et al. (US 20220173106 A1; hereinafter referred to as Choi) and further in view of Lee, et al. (US 20240250169 A1; hereinafter referred to as Lee)
Regarding Claim 1, Choi discloses a semiconductor device (semiconductor memory device 1), comprising:
a lower structure (substrate 102, [0017], Fig. 16B; it is noted that the instant application states that the lower structure “may include a semiconductor substrate . . .”, [070]);
a plurality of horizontal layers horizontally oriented over the lower structure (monocrystalline semiconductor layers 120, [0017], Fig. 16B);
a first conductive line commonly coupled to first ends of the plurality of horizontal layers and extending in a direction perpendicular to the lower structure (bit line 194, [0072], Fig. 16B);
a plurality of second conductive lines crossing the plurality of horizontal layers, respectively (gate electrode layers 184, [0091], Fig. 18A; it is noted that the instant application states that the second conductive lines “may serve as a gate electrode . . .”, [019]);
a plurality of data storage elements coupled to second ends of the plurality of horizontal layers, respectively, and stacked in a direction perpendicular to the lower structure (cell capacitor 200, [0082], Fig. 16B); and
a plurality of capping layers disposed between the plurality of second conductive lines and the first conductive line (spacer capping layers 192, [0069], Fig. 16B).
a plurality of blocking layers (third buried insulating layers 196, [0073], Fig. 16B).
Choi fails to disclose that said blocking layers are disposed between the plurality of capping layers and the first conductive line.
However, in analogous art, Lee discloses a plurality of blocking layers (first buffer insulating layer 21a, [0031]) disposed between the plurality of capping layer layers (second buffer insulating layer 21b, [0031], Fig. 2A) and the first conductive line (conductive line 12, [0026], Fig. 2A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the blocking layers of Choi such that they are disposed between the plurality of capping layers and the first conductive line as taught by Lee. One would be motivated to do so in order to provide an additional insulating liner/layer between the first conductive line and the plurality of second conductive lines/word lines to prevent parasitic capacitance between the two elements and increase device performance.
Regarding Claim 2, Choi/Lee discloses the semiconductor device of claim 1, wherein the blocking layers include a dielectric material that is selectively grown from the capping layers (Choi: [0073]).
Regarding Claim 3, Choi/Lee discloses the semiconductor device of claim 1, wherein the blocking layers include silicon carbon oxide (Choi: [0073]; “the third buried insulating layer 196 may include a silicon oxide” - silicon carbon oxide is a silicon oxide).
Regarding Claim 4, Choi/Lee discloses the semiconductor device of claim 1, wherein the capping layers include silicon oxide, silicon nitride, or a combination thereof (Choi: [0069], “each of the plurality of spacer capping layers 192 may include a silicon nitride”).
Regarding Claim 5, Choi/Lee discloses the semiconductor device of claim 1, wherein each of the capping layers includes a first liner (Choi: gate dielectric layers 182, [0065], Fig. 17A) and a second liner that is partially surrounded by the first liner (Choi: spacer capping layers 192, [0069], Fig. 17A), and
each of the blocking layers includes a material that is selectively deposited from a surface of the second liner (Choi: [0073]).
Regarding Claim 6, Choi/Lee discloses the semiconductor device of claim 5, wherein the first liner includes silicon oxide (Choi: [0066]; “may include at least one selected from among a silicon oxide …”), and
the second liner includes silicon nitride (Choi: [0069]; “each of the plurality of spacer capping layers 192 may include a silicon nitride”), and
the blocking layers include silicon carbon oxide (Choi: [0073]).
Regarding Claim 7, Choi/Lee discloses the semiconductor device of claim 1, wherein the capping layers include silicon nitride (Choi: [0069]), and the blocking layers include silicon carbon oxide (Choi: [0073]).
Regarding Claim 8, Choi/Lee discloses the semiconductor device of claim 1, further comprising:
a first contact node surrounding an outer wall of the first conductive line (Choi: “conductive barrier layer”, [0072]);
an extension portion disposed between the first contact node and one of the plurality of horizontal layers (Choi: direct contact DC, [0125]); and
a second contact node disposed between the data storage element and the plurality of horizontal layers (Choi: buried contact BC, [0125]).
Regarding Claim 9, Choi/Lee discloses the semiconductor device of claim 8, wherein the first contact node, the second contact node, and the extension portion include polysilicon (Choi: [0072, 0125]).
Regarding Claim 10, Choi/Lee discloses the semiconductor device of claim 8, wherein each of the plurality of horizontal layers includes:
a first doped region (Choi: first source-drain regions 122, [0070], Figs. 16B, 17B) coupled to the extension portion (Choi: [0125], Fig. 16B);
a second doped region (Choi: second source-drain regions 126, [0078], Figs. 16B, 17B) coupled to the second contact node (Choi: [0125], Fig. 16B); and
a channel region disposed between the first doped region and the second doped region (monocrystalline channel layers 124, [0078], Figs. 16B, 17B).
Regarding Claim 11, Choi/Lee discloses the semiconductor device of claim 10, wherein each of the first and second contact nodes includes doped polysilicon (Choi: [0071]), and
the first doped region includes an impurity diffused from the first contact node (Choi: [0099]), and
the second doped region includes an impurity diffused from the second contact node (Choi: [0100]).
Regarding Claim 12, Choi/Lee discloses the semiconductor device of claim 1, wherein the plurality of horizontal layers include monocrystalline silicon (Choi: [0019]; “monocrystalline semiconductor material”, it is known in the art that silicon is a semiconductor material).
Regarding Claim 13, Choi/Lee discloses the semiconductor device of claim 1, wherein each of the second conductive lines includes
double second conductive lines vertically facing each other with the plurality of horizontal layers interposed therebetween (Choi: Fig. 18A; two gate electrode layers 184 face each with the monocrystalline semiconductor layers interposed between them).
Regarding Claim 14, Choi/Lee discloses the semiconductor device of claim 1, wherein the data storage elements include capacitors (Choi: cell capacitors 200, [0082], Fig. 16B).
Regarding Claim 15, Choi/Lee discloses the semiconductor device of claim 1, wherein each of the data storage elements includes
a first electrode coupled to each of the plurality of horizontal layers (Choi: lower electrode layer 210, [0080], Fig. 16B);
a dielectric layer over the first electrode (Choi: capacitor dielectric layer 220, [0082], Fig. 16B); and
a second electrode over the dielectric layer (Choi: upper electrode layer 230, [0082], Fig. 16B), and
the first electrode has a horizontally oriented cylindrical shape (Choi: [0080], “a hollow cylindrical shape”).
Response to Arguments
Applicant’s arguments, see pages 8 and 9, filed June 25th, 2026, with respect to the drawing objection made to Figure 1B have been fully considered and are persuasive. The prior drawing objection has been withdrawn.
Applicant’s arguments, see pages 11-16, filed June 25th, 2026, with respect to the rejection(s) of claim(s) Claims 1-15 under 35 U.S.C. § 102(a)(2) have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of Choi and Lee, as stated above. Applicant argues that the capping layer (capping layer 146, buried layer 144, and liner layer 142) as referenced in the Non-Final Action dated March 25th, 2026, are removed in further steps in the fabrication process and are, therefore not part of the end device. However, upon further consideration, Choi does disclose a plurality of spacer capping layers which are analogous to the capping layers as cited in the instant application. Applicant further argued the interpretation of the blocking layers of Choi and its resulting position in relation to the capping layer and vertical conductive line. While Choi does disclose a blocking layer in the end result of the device (buried insulating layer 196), it is not located between the capping layer and the first conductive line. However, Lee, as stated above, does teach such a limitation and, therefore, the combination of Choi/Lee would disclose the instant invention (See 35 USC § 103 Rejection to Claim 1 above for more detailed reasonings).
Conclusion
32. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The Examiner can normally be reached Monday-Friday 9:30 a.m. - 6:30 p.m. (Eastern Time Zone).
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34. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/Noah C. Robertson/Examiner, Art Unit 2812 /William B Partridge/ Supervisory Patent Examiner, Art Unit 2812
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