DETAILED ACTION
Notice of Pre-AIA or AIA Status
1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
2. Acknowledgment is made of Applicant’s claim for foreign priority under 35 U.S.C. 119 (a)-(d).
3. However, should Applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e).
Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
4. The information disclosure statement (IDS) filed on December 13th, 2023, is being considered by the Examiner.
Drawings
5. The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the recitation “capping layers must include a first liner and a second liner that is partially surrounded by the first liner” as claimed in Claim 5 must be shown on all claimed capping layers or the feature(s) canceled from the claim(s). Figure 1B, nor any figure, fails to show a “first liner” or a “second liner” for the capping layer, CC. No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the Examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
6. Applicant is reminded of the proper language and format for an abstract of the disclosure.
The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. See MPEP 609.01(b).
The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided.
7. The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed. The following title is suggested: "A THREE-DIMENSIONAL MEMORY CELL SEMICONDUCTOR DEVICE".
Claim Objections
8. Claim 1 is objected to because of the following informalities:
a. On lines 16-17, the recitation of “a plurality of the blocking layers disposed between the capping layers and the first conductive line” should be “a plurality of [[the]] blocking layers disposed between the capping layers and the first conductive line”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
9. The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
10. Claims 8-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
11. Regarding Claim 8, it recites the following limitation,". . . an extension portion disposed between the first contact node and the horizontal layer;" in lines 4-5 of said claim. There is insufficient antecedent basis for this limitation in the claim. This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. For example, “the horizontal layer” is unclear as “the horizontal layer” had previously been introduced as “a plurality of horizontal layers”. It is unclear to the Examiner whether the claimed limitation is intended to occur with all of the plurality of horizontal layers, or only one instance of the same. For purposes of examination, the Examiner will interpret these limitations to extend to the plurality rather than the individual.
Similarly, Claim 8 recites the following limitation, “a second contact node disposed between the data storage element and the horizontal layer”, in lines 1-3. There is insufficient antecedent basis for this limitation in the claim. This recited language used to define the invention is ambiguous and clarification and/or correction are/is required to make its meaning clear and precise whereby the metes and bounds of the claimed invention can be ascertained. More specifically, “the data storage element” and “the horizontal layer” are unclear to the Examiner as these elements had previously been introduced as a plurality rather than the individual. It is unclear to the Examiner whether the claimed limitations are intended to occur with all of the plurality of data storage elements and horizontal layers, or only one instance of the same. For purposes of examination, the Examiner will interpret these limitations to extend to the plurality rather than the individual.
12. Claims 9-11 are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as they are dependent upon a rejected claim (Claim 8).
Claim Rejections - 35 USC § 102
13. In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis (i.e., changing from AIA to pre-AIA ) for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
14. The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
15. Claims 1-15 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Choi et al. (US 11,751,378 B2) [hereinafter referred to as Choi].
16. Regarding Claim 1, Choi discloses a semiconductor device (Figs. 19A-19B), comprising:
a lower structure (substrate 102, Col. 3, lines 41-49, Fig. 1B; it is noted that the instant application states that the lower structure “may include a semiconductor substrate . . .”, [070]);
a plurality of horizontal layers (monocrystalline semiconductor layers 120, Col. 3, lines 38-40, Fig. 1B) horizontally oriented over the lower structure (Fig. 1B);
a first conductive line (bit line 194, Col. 12, lines 59-64, Figs. 19A-19B) commonly coupled to first ends of the horizontal layers (Col. 12, lines 59-64, Figs. 19A-19B,) and extending in a direction perpendicular to the lower structure (Col. 12, lines 64-67, Figs. 19A-19B; in Choi, bit line 194 is in a direction labeled D3, which is perpendicular to the direction labeled D1. The lower structure (substrate 102) moves in the direction of D1);
a plurality of second conductive lines (gate electrode layers 184, Col. 16, lines 64-67, Col. 17 line 1, Figs. 18A-18B), crossing the horizontal layers, respectively (Col. 17, lines 21-25, Figs. 18A-18B; it is noted that the instant application states that the second conductive lines “may serve as a gate electrode . . .”, [019]);
a plurality of data storage elements (cell capacitor 200, Col. 20, line 55, Figs. 19A-19B) coupled to second ends of the horizontal layers, respectively (Col. 16, lines 55-63, Figs. 16A-16B), and stacked in the direction perpendicular to the lower structure (Fig. 20);
a plurality of capping layers disposed between the second conductive lines and the first conductive line (capping layers 146, buried layer 144, and liner layer 142 Col. 7, lines 1-14, Figs. 4A-4C; together, capping layers 146, buried layer 144, and liner layer 142 form capping layers as described in the instant application); and
a plurality of the blocking layers disposed between the capping layers and the first conductive line (first (134), second (162), and third (196) buried insulating layers, respectively, Figs. 3A-3C, 11A-11B, 13A-13B, and 14A-15B; the first (134), second (162), and third (196) buried insulating layers of Choi together form the blocking layers as described in the instant application).
17. Regarding Claim 2, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein the blocking layers (first (134), second (162), and third (196) buried insulating layers) include a dielectric material that is selectively grown from the capping layers (Col. 13, lines 22-31).
18. Regarding Claim 3, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein the blocking layers (first (134), second (162), and third (196) buried insulating layers) include silicon carbon oxide (Col. 6, lines 24-29; Col. 10, lines 40-45).
19. Regarding Claim 4, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein the capping layers (capping layers 146, buried layer 144, and liner layer 142) include silicon oxide (Col. 7, lines 10-12), silicon nitride (Col. 12, lines 49-50), or a combination thereof.
20. Regarding Claim 5, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein each of the capping layers includes a first liner (buried layer 144, Col. 7, lines 5-6, Figs. 4A-4C) and a second liner that is partially surrounded by the first liner (liner layer 142, Col. 7, lines 2-6, Figs. 4A-4C), and
each of the blocking layers (first (134), second (162), and third (192) buried insulating layers) includes a material that is selectively deposited from a surface of the second liner (Col. 7, lines 44-49).
21. Regarding Claim 6, Choi discloses a semiconductor device of claim 5, wherein the first liner includes silicon oxide (buried layer 144, Col. 7, lines 10-12), and
the second liner (liner layer 142) includes silicon nitride (Col. 7, lines 9-10), and
the blocking layers (first (134), second (162), and third (192) buried insulating layers) include silicon carbon oxide (Col. 6, lines 24-29; Col. 10, lines 40-45).
22. Regarding Claim 7, Choi discloses a semiconductor device of claim 1, wherein the capping layers include silicon nitride (capping layer 146, Col. 7, lines 9-10), and the blocking layers (first (134), second (162), and third (192) buried insulating layers) include silicon carbon oxide (Col. 6, lines 24-29; Col. 10, lines 40-45).
23. Regarding Claim 8, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, further comprising:
a first contact node surrounding an outer wall of the first conductive line (“conductive barrier layer”, Col. 13, Lines 7-20);
an extension portion disposed between the first contact node and the horizontal layer (direct contact DC, Col. 22, lines 23-32, Figs. 16A-16B); and
a second contact node disposed between the data storage element and the horizontal layer (buried contact BC, Col. 22, lines 29-32, Figs. 16A-16B).
24. Regarding Claim 9, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 8, wherein the first contact node, the second contact node, and the extension portion include polysilicon (Col. 13, lines 12-21).
25. Regarding Claim 10, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 8, wherein each of the horizontal layers includes:
a first doped region (first source-drain region 122, Col. 14, lines 9-19, Figs. 17A-17B) coupled to the extension portion (Col. 22, lines 23-32, Figs. 16A-16B);
a second doped region (second source-drain region 126, Col. 14, lines 11-19, Figs. 17A-17B) coupled to the second contact node (buried contact BC, Col. 22, lines 29-32, Figs. 16A-16B); and
a channel region disposed between the first doped region and the second doped region (monocrystalline channel layers 124, Col. 14, lines 9-19, Figs. 17A-17B).
26. Regarding Claim 11, Choi discloses a semiconductor device (Figs 19A-19B) of claim 10, wherein each of the first and second contact nodes includes doped polysilicon (Col. 13, lines 15-16) and
the first doped region (first source-drain region 122) includes an impurity diffused from the first contact node (Col. 18, lines 27-36), and
the second doped region (second source-drain region 126) includes an impurity diffused from the second contact node (Col. 18, lines 37-43)
27. Regarding Claim 12, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein the horizontal layers (monocrystalline semiconductor layer 120) include monocrystalline silicon (Col. 2, lines 24-25).
28. Regarding Claim 13, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein each of the second conductive lines (gate electrode layers 184) includes
double second conductive lines vertically facing each other (gate electrode layers 184, Col. 16, lines 63-67, Col. 17, lines 1-9, Figs. 18A-18B) with the horizontal layers interposed therebetween (Col. 17, lines 3-9, Figs. 18A-18B).
29. Regarding Claim 14, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein the data storage elements (cell capacitor 200) include capacitors (Col. 14, lines 20-25).
30. Regarding Claim 15, Choi discloses a semiconductor device (Figs. 19A-19B) of claim 1, wherein each of the data storage elements (cell capacitor 200) includes
a first electrode coupled to each of the horizontal layers (first electrode layer 210, Col. 20, lines 55-56, Figs. 19A-19B);
a dielectric layer over the first electrode (capacitor dielectric layer 220, Col. 20, lines 56-58, Figs. 19A-19B); and
a second electrode over the dielectric layer (second electrode layer 230, Col. 20, line 58), and
the first electrode has a horizontally oriented cylindrical shape (Col 20, lines 65-67, Col. 21, lines 1-16).
Conclusion
31. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
a. Lee et al. (US 10,784,272 B2); discloses a semiconductor memory device having a plurality of horizontal layers oriented over a substrate (lower structure) with a bit line (first conductive line) orthogonal to the substrate, and a plurality of word lines (second conductive lines) crossing the horizontal layers. It further discloses a first impurity region (first doped region) which is coupled to an extension part (extension portion), a second impurity region (second doped region) coupled to a data storage element (data storage element), and a channel region (channel region) located between the first and second impurity regions.
b. Brewer, et al. (US 11,094,699 B1); discloses a stacked, horizontal capacitor structure, including a stacked semiconductor memory device.
c. Gomes, et al. (US 20210159229 A1); discloses a three-dimensional memory device with source and drain regions along horizontal layers.
d. Kim, et al. (US 10,468,414 B2); discloses a stackable semiconductor memory device.
32. Any inquiry concerning this communication or earlier communications from the Examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The Examiner can normally be reached Monday-Friday 9:30 a.m. - 6:30 p.m. (Eastern Time Zone).
33. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
34. If attempts to reach the Examiner by telephone are unsuccessful, the Examiner’s supervisor, William B. Partridge, can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/NOAH C. ROBERTSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812