CTNF 18/538,091 CTNF 91895 2842 DETAILED ACTION 07-03-aia AIA 15-10-aia The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 103 07-20-aia AIA The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 07-23-aia AIA The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. 07-21-aia AIA Claims 1-10 are rejected un der 35 U.S .C. 103 as being unpatentable over Wu ( US 6,930,550 B1 ). Cl aim 1 , recites a sel f-biased amplifier circuit comprising complementary PMOS/NMOS input transistors forming inverters at two differential input nodes, PMOS and NMOS bias transistors providing bias current, an output, and first and second transistor switches connecting from the output nodes to gates of the bias transistors to control active/standby mode. Element-by-element mapping against Wu (Fig. 3): Claim 1 Limitation Wu Disclosure (Fig. 3) Self-biased amplifier circuit Buffer Core 70 — self-biasing differential buffer generating VB from its own differential inputs (Abstract, Col. 1) First and second input nodes receiving differential input signals DIN input node (first) and VREF input node (second); Wu expressly states DIN and VREF can be replaced by a full differential D+/D− signal (Col. 5) First PMOS input transistor at first input node (gate = first input signal) P-channel drive transistor 50 at DIN input node, gate receives DIN (Fig. 3, Col. 3) First NMOS input transistor at first input node (gate = first input signal) N-channel drive transistor 52 at DIN input node, gate receives DIN (Fig. 3, Col. 3) Drains of first PMOS and NMOS connected to form inverter — first output node Drains of 50 and 52 connected to define QBOUT output node — forming a CMOS inverter stage (Fig. 3) Second PMOS input transistor at second input node P-channel drive transistor 150 at VREF input node, gate receives VREF (Fig. 3, Col. 3) Second NMOS input transistor at second input node N-channel drive transistor 152 at VREF input node, gate receives VREF (Fig. 3, Col. 3) Drains of second PMOS and NMOS connected to form inverter — second output node Drains of 150 and 152 connected to define QOUT output node (Fig. 3) At least one PMOS bias transistor; source of each PMOS input transistor connected to its drain P-channel current-source transistors 46 (DIN side) and 146 (VREF side); sources of 50 and 54 connect to drain of 46 via upper branching node (through reset transistor 48 ); sources of 150 and 154 connect to drain of 146 via upper branching node (through 148 ) (Fig. 3) At least one NMOS bias transistor; source of each NMOS input transistor connected to its drain N-channel current-sink transistors 66 (DIN side) and 166 (VREF side); sources of 52 and 56 connect to drain of 66 via lower branching node (through reset transistor 64 ); sources of 152 and 156 connect to drain of 166 via 164 (Fig. 3) Output connected to at least one output node QBOUT (drains of 50/52) and QOUT (drains of 150/152) — Wu's differential outputs (Fig. 3, Fig. 4) First transistor switch connected between output node and gate of PMOS bias transistor; second transistor switch connected between output node and gate of NMOS bias transistor; switches configured to control active/standby Not identically disclosed. Wu's transmission gates 60/62 and 160/162 connect from the BIAS-GENERATING nodes (drains of 54/56 and drains of 154/156) to VB (= gate of PMOS bias transistors 46/146 and NMOS bias transistors 66/166). Wu does NOT connect directly from the DRIVE output nodes (QBOUT, QOUT) to the bias transistor gates. The transmission gates do control active/standby (when RST is active, 62 and 162 turn off, 60 and 160 also turn off, VB floats → standby; when RST is inactive → active mode). [AltContent: rect] PNG media_image1.png 526 903 media_image1.png Greyscale Fig. 3 of Wu reproduced for ease of reference. Reason for Obviousness: Wu discloses every structural element of Claim 1 except the specific connection point of the transistor switches: in Wu, the switches (transmission gates 60/62, 160/162) connect from separate bias-generating inverter nodes (drains of transistors 54/56 and 154/156) rather than from the main drive output nodes (QBOUT, QOUT) to the bias transistor gates. Wu discloses at the DIN input node both (a) a drive inverter (transistors 50, 52 with output at QBOUT) and (b) a bias-generating inverter (transistors 54, 56 with output at the bias-gen node feeding the transmission gate). Both inverters receive the same DIN input and both produce a signal that reflects the input state. Wu explicitly states at Column 3 that the bias-generating branch uses smaller transistors than the drive branch precisely because it is generating the self-bias signal, while the drive branch generates the output. Wu teaches this architectural separation is done for efficiency (Col. 3: "10% of the energy may go toward self-bias generation, with 90% going toward output generation"). A person of ordinary skill in the art reading Wu would immediately appreciate that the bias-generating inverter branch could be simplified by connecting the transistor switches directly from the main drive output nodes (QBOUT, QOUT) to the bias transistor gates — eliminating the need for the separate bias-generating transistor pairs (54/56 and 154/156) entirely and reducing transistor count. This is a straightforward design simplification yielding a circuit with the same functional result: the output node's voltage (reflecting the input state) is used to control the self-bias VB via transistor switches, governing active/standby mode. The motivation to simplify the circuit by removing the redundant bias-generating branch and routing the existing output node directly through transistor switches to the bias transistor gates would have been obvious to a skilled circuit designer seeking to reduce die area and power consumption — goals consistently recognized in the art. Accordingly, claim 1 is rejected under 35 U.S.C. § 103 as unpatentable over Wu. Claim 2 additionally recites that the output is connected to both the first and the second output node to provide a differential output signal. Wu explicitly discloses this: Buffer Core 70 in Figure 3 generates two complementary differential outputs — QBOUT (from drains of drive transistors 50 and 52 at the DIN input node) and QOUT (from drains of drive transistors 150 and 152 at the VREF input node). These are true differential complementary outputs (when DIN > VREF, QBOUT is driven low and QOUT is driven high, and vice versa). Wu's abstract and Col. 3 expressly describe QOUT and QBOUT as the differential outputs of the buffer. Figure 4 further shows both outputs being buffered. Claim 3 additionally recites that the at least one PMOS bias transistor comprises a first PMOS bias transistor and a second PMOS bias transistor, and the at least one NMOS bias transistor comprises a first NMOS bias transistor and a second NMOS bias transistor. Wu explicitly and unambiguously discloses two separate PMOS bias transistors and two separate NMOS bias transistors in Figure 3: First PMOS bias transistor = transistor 46 (DIN side p-channel current-source, gate = VB, drain = upper branching node of DIN amplifier) Second PMOS bias transistor = transistor 146 (VREF side p-channel current-source, gate = VB, drain = upper branching node of VREF amplifier) First NMOS bias transistor = transistor 66 (DIN side n-channel current-sink, gate = VB, connected to lower branching node of DIN amplifier) Second NMOS bias transistor = transistor 166 (VREF side n-channel current-sink, gate = VB, connected to lower branching node of VREF amplifier) Wu's Col. 3 confirms: transistor 46 sources current to the DIN input amplifier and transistor 146 sources current to the VREF input amplifier — they are structurally and functionally separate transistors. Claim 4 further recites a third and fourth transistor switch with specific cross-connected topology: (1) first switch between second output node and gate of first PMOS bias transistor; (2) second switch between second output node and gate of first NMOS bias transistor; (3) third switch between first output node and gate of second PMOS bias transistor; (4) fourth switch between first output node and gate of second NMOS bias transistor. Wu's Figure 3 discloses two pairs of transmission gate transistors — ( 60 , 62 ) on the DIN side and ( 160 , 162 ) on the VREF side — both feeding the single VB node that connects to all four bias transistor gates (46, 66, 146, 166). Structurally: Transmission gate 60/62 : connects DIN-side bias-gen node → VB → gates of 46 (first PMOS bias), 66 (first NMOS bias), 146 (second PMOS bias), and 166 (second NMOS bias) Transmission gate 160/162 : connects VREF-side bias-gen node → VB → same four bias transistor gates Wu therefore discloses four transistors operating as switches (60, 62, 160, 162) that collectively control all four bias transistors. The fact that in Wu all four switches feed a common VB node rather than being individually routed to separate bias transistor gates per the cross-connected topology of Claim 4 represents a straightforward design choice. A person of ordinary skill in the art would recognize that individually routing separate transistor switches from each output node to each respective bias transistor gate — rather than using a shared VB node — achieves the same functional purpose of controlling active/standby mode while offering enhanced individual control. Such cross-connected topologies for differential bias control are well known in the art. Specifically, the cross-connection in Claim 4 (second output node → first bias transistors; first output node → second bias transistors) creates a balanced feedback loop analogous in purpose and concept to Wu's symmetric differential structure and would be an obvious implementation variant to a skilled analog circuit designer. Claim 5 further recites that each transistor switch comprises two complementary transistors — a p-type transistor configured to receive a first enable signal and an n-type transistor configured to receive a second enable signal — for controlling the active/standby mode. Wu expressly and identically teaches this structure in Figure 3. Each of Wu's two transmission gates is a complementary switch comprising: DIN-side transmission gate: P-channel transistor 62 (gate = RST = active-high reset signal = "first enable signal") N-channel transistor 60 (gate = RSTB = active-low reset signal = "second enable signal") VREF-side transmission gate: P-channel transistor 162 (gate = RST) N-channel transistor 160 (gate = RSTB) Wu's Col. 4 confirms: "when RSTB is low (active), n-channel reset transistors 64, 164 turn off, and n-channel transmission gate transistors 60, 160 also turn off, allowing VB to float" and "p-channel transmission gate transistors 62, 162 all turn off" during reset. This is precisely the complementary enable signal structure claimed. Inverter 58 (Fig. 3) generates RST from RSTB, providing the two complementary enable signals. The mapping is direct: Wu's RST and RSTB signals = the "first enable signal" and "second enable signal" of Claim 5. Wu's p-channel TG transistors (62, 162) receive RST = first enable signal; Wu's n-channel TG transistors (60, 160) receive RSTB = second enable signal. Claim 6 recites that drains and sources of both complementary transistors in each transistor switch are connected between two common nodes, forming a switch between those two nodes. This is precisely the transmission gate structure disclosed in Wu's Figure 3. For the DIN-side transmission gate: P-channel transistor 62 : channel connected between the DIN-side bias-gen node and VB node N-channel transistor 60 : channel (drain-to-source) also connected between the same DIN-side bias-gen node and the same VB node Both transistors 60 and 62 are connected in parallel between the identical two common nodes (bias-gen node and VB), forming a bidirectional switch between those nodes. Wu's Col. 4 explicitly describes this topology. The identical structure applies to transistors 160/162 on the VREF side. This is the classic CMOS transmission gate structure (parallel PMOS and NMOS between two nodes) and is directly anticipated by Wu's Figure 3. Claim 7 recites that the self-biased amplifier circuit is configured as a clock buffer converting a sinusoidal wave signal at the input to an amplified signal at the output. Wu expressly teaches this use case. At Column 5, Wu states: "The differential buffer could receive a clock signal , or a data or control signal as the data input DIN." Using the self-biasing differential buffer as a clock buffer to amplify a sinusoidal or periodic clock signal into a rail-to-rail digital output is explicitly contemplated by Wu. Furthermore, converting sinusoidal signals to amplified digital outputs is a standard and well-known function of differential input buffers in CMOS circuits, making this application obvious to any skilled artisan reading Wu. Claim 8 recites that an on-resistance of the first transistor switch, a gate capacitance of the at least one PMOS bias transistor, and a parasitic capacitance at a gate node of the at least one PMOS bias transistor are configured to form a low-pass filter. Wu discloses the structural elements that inherently produce this RC low-pass filter behavior. In Wu's Figure 3: On-resistance of first transistor switch: when transmission gate transistors 60 and 62 are conducting (active mode), they exhibit a finite on-resistance R_on between the bias-gen node and the VB node. Gate capacitance of PMOS bias transistor: the VB node connects to gates of p-channel current-source transistors 46 and 146 , each of which has a gate oxide capacitance C_g. Parasitic capacitance at gate node: the VB node also has parasitic interconnect capacitance C_p. The RC network formed by R_on of transmission gates 60/62 and the total capacitance (C_g + C_p) at the VB node (gate of 46/146) inherently functions as a low-pass filter. This is not a new insight — it is a fundamental and well-known property of any transistor switch driving a capacitive load. The formation of an RC low-pass filter from the on-resistance of a transistor switch in series with a gate capacitance is inherent in Wu's circuit and would be immediately recognized by a person of ordinary skill in the art as the mechanism by which VB is smoothed and stabilized (Col. 3: "Since VB tends to remain constant, the propagation delay through the differential buffer remains relatively constant"). The claim merely recites an inherent characteristic of Wu's disclosed circuit elements. Accordingly, the claimed low-pass filter is an inherent consequence of the on-resistance of Wu's transmission gate transistors (60/62, Fig. 3) acting with the gate capacitance and parasitic capacitance of the VB node (gate of bias transistors 46/146, Fig. 3), as would be immediately apparent to a person of ordinary skill in CMOS analog circuit design. Claim 9 further recites at least one first additional transistor switch connected between a supply voltage (VDD) and the gate of the at least one PMOS bias transistor, and at least one second additional transistor switch connected between ground and the gate of the at least one NMOS bias transistor. Wu does not explicitly disclose transistor switches connected directly from VDD to the gate of PMOS bias transistors (46/146) or from ground to the gate of NMOS bias transistors (66/166). Wu's standby/reset mechanism relies on (a) transmission gates 60/62/160/162 disconnecting the VB node (allowing it to float) and (b) reset transistors 48/64/148/164 cutting off current flow. Wu does not show direct forced clamping of the VB node to supply or ground during standby. However, the concept of forcing bias voltages to defined rails (VDD or GND) during power-down to ensure deterministic and fast standby behavior is well-established in CMOS analog design. A person of ordinary skill in the art reading Wu would recognize the limitation of Wu's floating-VB standby approach (floating VB during standby may lead to undefined bias transistor states and slow restart) and would find it obvious to add pull-up switches from VDD to the PMOS bias transistor gate and pull-down switches from GND to the NMOS bias transistor gate. This ensures the PMOS current source (46/146) is fully disabled (gate → VDD turns off PMOS current source) and the NMOS current sink (66/166) is fully disabled (gate → GND turns off NMOS current sink) during standby, providing faster, more deterministic power-down behavior. This is a straightforward application of known design techniques to a recognized problem in Wu's circuit. Accordingly, the additional transistor switches between supply voltage / ground and the bias transistor gates represent a predictable and well-recognized design enhancement for improving standby reliability and speed-up of Wu's circuit, well within the ordinary skill in the art. Claim 10 is an independent method claim for controlling a self-biased amplifier circuit. The method steps mirror the structural elements of apparatus Claim 1: Method Step (Claim 10) Wu Disclosure (Fig. 3) Receiving a differential input signal at first and second input nodes with PMOS/NMOS complementary transistors forming inverters DIN and VREF applied to gates of drive transistors 50/52 (DIN node, forming QBOUT inverter) and 150/152 (VREF node, forming QOUT inverter), Fig. 3 Providing first bias current to PMOS input transistors via at least one PMOS bias transistor P-channel current-source transistors 46 and 146 sourcing current to upper branching nodes feeding PMOS drive transistors 50/150 and bias-gen transistors 54/154 (Fig. 3, Col. 3) Providing second bias current to NMOS input transistors via at least one NMOS bias transistor N-channel current-sink transistors 66 and 166 sinking current from lower branching nodes (through reset transistors 64/164 ) connected to NMOS drive transistors 52/152 and bias-gen transistors 56/156 (Fig. 3, Col. 3) Providing control signals to first and second transistor switches connected between output nodes and gates of bias transistors to control active/standby mode RST and RSTB signals applied to transmission gate transistors 60/62 (DIN side) and 160/162 (VREF side) — RST active → transmission gates disable → VB floats → standby; RST inactive → transmission gates conduct → VB set → active mode (Fig. 3, Col. 4) As with apparatus Claim 1, the sole structural difference between Wu and Claim 10 is that Wu's transistor switches (transmission gates 60/62, 160/162) connect from bias-generating nodes (drains of 54/56 and 154/156) rather than from the drive output nodes (QBOUT, QOUT) to the bias transistor gates. The analysis and motivation for obviousness over Wu is identical to that presented for Claim 1 above. Accordingly, claim 10 is rejected under 35 U.S.C. § 103 over Wu for the reasons stated for Claim 1, applied mutatis mutandis to the method steps. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to HAFIZUR RAHMAN whose telephone number is (571)270-0659. The examiner can normally be reached M-F: 10-6. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on (571) 272-1769. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/Primary Examiner, Art Unit 2843. Application/Control Number: 18/538,091 Page 2 Art Unit: 2843 Application/Control Number: 18/538,091 Page 3 Art Unit: 2843 Application/Control Number: 18/538,091 Page 4 Art Unit: 2843 Application/Control Number: 18/538,091 Page 5 Art Unit: 2843 Application/Control Number: 18/538,091 Page 6 Art Unit: 2843 Application/Control Number: 18/538,091 Page 7 Art Unit: 2843 Application/Control Number: 18/538,091 Page 8 Art Unit: 2843 Application/Control Number: 18/538,091 Page 9 Art Unit: 2843 Application/Control Number: 18/538,091 Page 10 Art Unit: 2843 Application/Control Number: 18/538,091 Page 11 Art Unit: 2843 Application/Control Number: 18/538,091 Page 12 Art Unit: 2843