DETAILED ACTION
This action is in response to the Application filed on 12/13/2023.
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
Information Disclosure Statement
The information disclosure statement(s) (IDS) submitted on 06/10/2025 is/are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement(s) is/are being considered by the examiner.
Specification
The lengthy specification has not been checked to the extent necessary to determine the presence of all possible minor errors. Applicant's cooperation is requested in correcting any errors of which applicant may become aware in the specification.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the “wherein the controller is coupled to the power stage via a single wire interface” of claim 9 must be shown or the feature(s) canceled from the claim(s). No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Objections
Claim(s) 8 is/are objected to because of the following informalities:
Claim(s) 8 recite(s) “a controller as claimed in claim 1” in line 1. It appears that it should be “the controller as claimed in claim 1”.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claim(s) 9 is/are rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
Claim 9 recites “wherein the controller is coupled to the power stage via a single wire interface”. However, preceding claim recites “send the control signal to the plurality of phases via a first link; receive from each phase a feedback signal via a second link”. Claim 5 contradicts the multiple link (wires) claimed in claim 1.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1, 4 – 8, 10 and 13 – 18 is/are rejected under 35 U.S.C. 102(a)(1) and 102(a)(2) as being anticipated by US Pub. No. 2005/0012492; (hereinafter Mihalka).
Regarding claim 1, Mihalka [e.g. Figs. 1 - 6] discloses a controller for controlling a power stage having a plurality of phases [e.g. 201 - 202], the controller being configured to: generate a control signal [e.g. D0]; send the control signal to the plurality of phases via a first link [e.g. D0 output of 208]; receive from each phase a feedback signal via a second link [e.g. ISHR]; sum the plurality of feedback signals [e.g. ISHR sums the current on each phase; paragraph 040 recites “The ISHR signal represents the difference between the average current of the next phase to be turned off and the average of all phase currents”. It is well known in the art that the average is a sum of all the current divided by the number of phases]; and derive an average current per phase [e.g. as stated above in paragraph 040].
Regarding claim 4, Mihalka [e.g. Figs. 1 - 6] discloses wherein the control signal comprises one or more of a first pulse [e.g. Fig. 3; first pulse of D0] having a first pulse-width for activating a first phase [e.g. PH0; paragraph 035 recites “FIG. 3, a timing diagram with a three wire system and four phases is illustrated where there is no phase overlap between phases PH0-PH3. In this instance, only one phase is turned on at any time during steady state operation. Accordingly, the ON and OFF addresses for each of the phase drivers is the same before the particular phase turns on. The pulse width of the phases is determined by the timing difference between data bus lines D0 and D1. Logic is provided that resets the counters to 0 by producing a narrow pulse at the end of either the D0 or D1 signal. After these narrow pulses, the next instance of a D0 or D1 pulse turns ON or OFF phase PH0 accordingly”]; a second pulse having a second pulse-width for activating additional phases incrementally; a third pulse having a third pulse-width for de-activating all phases; and a fourth pulse having a fourth pulse-width for initiating each phase to read its own address.
Regarding claim 5, Mihalka [e.g. Figs. 1] discloses wherein the first link and the second link are unidirectional links [e.g. Fig. 1; see arrow of D0 and ISHR].
Regarding claim 6, Mihalka [e.g. Figs. 1] discloses wherein the sum of the feedback signals is proportional to an output current generated by the plurality of phases [e.g. paragraph 040 recites “The ISHR signal represents the difference between the average current of the next phase to be turned off and the average of all phase currents”].
Regarding claim 7, Mihalka [e.g. Figs. 1 - 6] discloses wherein the controller is further configured to generate a configuration signal [e.g. D2] for configuring one or more phases [e.g. Logic for Reset ON/OFF ALL ON ALL OFF], the configuration signal being transmittable via a third link [e.g. link of D2].
Regarding claim 8, Mihalka [e.g. Figs. 1 - 6] discloses coupled to a power stage having a plurality of phases [e.g. 201 - 202].
Regarding claim 10, Mihalka [e.g. Figs. 1 - 6] discloses wherein each phase comprises a decoder [e.g. ON Counter, OFF Counter & Logic in 201 - 202] for decoding the control signal.
Regarding claim 13, Mihalka discloses wherein each phase comprises an address reader [e.g. A0-A3] configured to read an address of the phase by sending a current through an address resistance [e.g. paragraph 032 recites “the address of each of these phase drivers can be determined by a single pin and a two-resistor divider in conjunction with comparators in the phase driver to discriminate different addresses based on voltage levels”].
Regarding claim 14, Mihalka discloses wherein the address reader comprises a logic circuit [e.g. comparator, paragraph 032 above with respect to claim 13] configured to initiate a read sequence [e.g. paragraph 032].
Regarding claim 15, Mihalka discloses wherein the address reader comprises a compensator circuit [e.g. additional comparator(s); paragraph 032] configured to compensate for an error generated by the address resistance [e.g. discriminate different address, paragraph 032].
Regarding claim 16, Mihalka [e.g. Figs. 1 - 6] discloses wherein the decoder is configured to measure the pulse-width of each pulse in the control signal [e.g. D0]; and perform an associated protocol based on the measurement.
Regarding claim 17, Mihalka [e.g. Figs. 1 - 6] discloses a method of controlling a power stage having a plurality of phases [e.g. 201 - 202], the method comprising: generating a control signal [e.g. D0] comprising a series of pulses [e.g. see D0 in Figs. 3 - 6]; sending the control signal to the plurality of phases via a first link [e.g. D0 output of 208]; for each phase decoding [e.g. ON Counter OFF Counter & Logic on phase drivers 201 and 202] the control signal and activating or de-activating the phase based on the control signal [e.g. paragraph 030 recites “a turn-ON signal from oscillator 204 is propagated on data line D0 to turn a selected phase ON”]; receiving via a second link a feedback signal from each phase [e.g. ISHR]; summing the plurality of feedback signals [e.g. ISHR sums the current on each phase; paragraph 040 recites “The ISHR signal represents the difference between the average current of the next phase to be turned off and the average of all phase currents”. It is well known in the art that the average is a sum of all the current divided by the number of phases]; and deriving an average current per phase [e.g. as stated above in paragraph 040].
Regarding claim 18, Mihalka [e.g. Figs. 1 - 6] discloses wherein the control signal comprises one or more of a first pulse [e.g. Fig. 3; first pulse of D0] having a first pulse-width for activating a first phase [e.g. PH0; paragraph 035 recites “FIG. 3, a timing diagram with a three wire system and four phases is illustrated where there is no phase overlap between phases PH0-PH3. In this instance, only one phase is turned on at any time during steady state operation. Accordingly, the ON and OFF addresses for each of the phase drivers is the same before the particular phase turns on. The pulse width of the phases is determined by the timing difference between data bus lines D0 and D1. Logic is provided that resets the counters to 0 by producing a narrow pulse at the end of either the D0 or D1 signal. After these narrow pulses, the next instance of a D0 or D1 pulse turns ON or OFF phase PH0 accordingly”]; a second pulse having a second pulse-width for activating additional phases incrementally; a third pulse having a third pulse-width for de-activating all phases; and a fourth pulse having a fourth pulse-width for initiating each phase to read its own address.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Mihalka in view of Applicant(s) Admitted Prior Art; (hereinafter AAPA).
Regarding claim 9, Mihalka fails to disclose wherein the controller is coupled to the power stage via a single wire interface.
AAPA [e.g. Fig. 2] teaches wherein the controller is coupled to the power stage via a single wire interface [e.g. paragraph 026 recites “FIG. 2 is a diagram of a known dual single-wire interface that can be used with the power management circuit of FIG. 1”].
It would have been obvious to one having ordinary skill in the art before the effective filing date to modify Mihalka by wherein the controller is coupled to the power stage via a single wire interface as taught by AAPA in order of being able to reduce the complexity of the circuit design, paragraph 039.
Examiner's Note
Examiner has cited particular columns and line numbers in the references applied to the claims above for the convenience of the applicant. Although the specified citations are representative of the teachings of the art and are applied to specific limitations within the individual claim, other passages and figures may apply as well. It is respectfully requested from the applicant in preparing responses, to fully consider the references in their entirety as potentially teaching all or part of the claimed invention, as well as the context of the passage as taught by the prior art or disclosed by the Examiner.
In the case of amending the claimed invention, Applicant is respectfully requested to indicate the portion(s) of the specification which dictate(s) the structure relied on for proper interpretation and also to verify and ascertain the metes and bounds of the claimed invention.
Allowable Subject Matter
Claim(s) 2 – 3 and 11 – 12 is/are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
The primary reason for the indication of the allowability of claim 2 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “having a first port connected to the first link and a second port connected to the second link, and a resistance circuit coupled to the second port, the resistance circuit having a plurality of resistances coupled in parallel, each resistance being connected to ground via a corresponding switch”.
The primary reason for the indication of the allowability of claim 11 is the inclusion therein, in combination as currently claimed as a whole, of the limitation of “wherein the decoder comprises a finite state machine coupled to a phase counter and a logic circuit; wherein the finite state machine is configured to execute a decoding protocol”.
Claims 3 and 12 are objected because its inherent dependency on claim 2 and 11, respectively.
Conclusion
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/ALEX TORRES-RIVERA/Primary Examiner, Art Unit 2838