DETAILED ACTION The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention. Claims 1-2 are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Pye (US 2018/0123551 , cited by the applicant ) . Regarding claim 1 , Pye discloses an amplifier system (amplifier 832, Figure 8C, § 0126–[0127) in which a coupled-line balun (200) is connected between an unbalanced input (Vin) and a differential gain stage (834) that produces differential outputs (Vout+, Vout−). The coupled-line balun 200 functions as a matching/interface circuit at the input of the amplifier. Additionally, Pye discloses use of a coupled-line balun in a receiver die (812) positioned at input and output signal paths (Figure 8B, § 0125). The coupled-line balun in Pye thus constitutes a matching circuit connected to the terminals of an amplifier, as claimed. Pye also teaches a coupled-line balun 100 (and its equivalent, balun 200) comprising a first stripline 106 and a second stripline 104 (the "first metal line" and "second metal line," respectively) fabricated as conductive structures over a substrate (Figure 1A, § 0050–[0052). Pye expressly describes the four terminals P1, P2, P3, and P4 ( § 0056): "the electrical connections of the coupled-line balun 100 are delineated by terminals or ports P1, P2, P3, and P4." The structure therefore constitutes a coupled-line circuit unit having a 4-port structure with first and second metal lines. Pye then explicitly discloses a series resistor-inductor (RL) network comprising inductor 108 and resistor 110, connected in series between port P2 and ground (Figure 1A; Figure 2; § 0063). Port P2 is the "through port" of first stripline 106, being the output end of the direct transmission path from P1 through to P2 ( § 0056– § 0057). Pye expressly teaches that this RL network "nulls common-mode signals in the frequency domain" at low frequencies ( § 0063), thereby "extending the bandwidth of operation to frequencies lower than the minimum length-dominated frequency." Pye further defines even-mode characteristic impedance (Z_oe) as "the characteristic impedance of the stripline 104 or the stripline 106 to the ground when both the striplines 104 and 106 are driven in-phase" ( § 0103) — i.e., the common-mode impedance — and teaches that the inductor 108 and resistor 110 control this even-mode (common-mode) response of the balun ( § 0037–[0042). The RL network therefore constitutes a "first impedance restriction circuit unit" connected to the through port P2 that restricts even-mode impedance in the low frequency band, as literally claimed. Regarding Claim 2 , Pye explicitly discloses that the first impedance restriction circuit unit (the series RL network) comprises a resistor 110 electrically connected between port P2 (the through port) and ground (Figure 2, § 0083): "the resistor 110 and the inductor 108 are connected in series between port P2 and ground at P4." The claim language "comprises a resistance" does not preclude the additional presence of an inductor; the claim merely requires that a resistance be present in the impedance restriction unit and connected to the through port. Both conditions are satisfied by Pye's resistor 110. Pye further teaches specific resistance values: "In one implementation, the resistor 110 has a resistance ranging from 10 ohm (Ω) to 100Ω" ( § 0054) and provides example values of 16.7 Ω ( § 0095) and 28.5 Ω ( § 0109). Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102 of this title, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. The factual inquiries set forth in Graham v. John Deere Co. , 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness. Claim s 3-6 are rejected under 35 U.S.C. 10 3 as being unpatentable over Pye. Regarding claim 3 , Pye does not explicitly claim a discrete second impedance restriction circuit positioned between the coupled lines for the specific purpose of restricting odd-mode impedance. However, regarding odd-mode impedance , Pye expressly discusses odd-mode characteristic impedance Z_oo as a central design parameter of coupled-line baluns ( § 0037, § 0103). Pye teaches that: "it is desirable to increase or maximize the ratio of even-mode impedance Z_oe to odd-mode impedance Z_oo" and that "implementing a coupled-line balun in this manner extends the overall bandwidth of the balun and improves common-mode rejection at low frequencies" ( § 0038). Pye further teaches that the even-mode and odd-mode impedances of coupled lines are controllable through the physical configuration of the striplines and associated circuitry. Further Pye's lumped circuit model (Figure 1B, § 0067) explicitly shows capacitor 105 "electrically connected between the stripline 104 and the stripline 106 to model the capacitance and/or coupling between the striplines 104 and 106." While Pye describes this capacitor as a model element, a person of ordinary skill in the art would understand that physically implementing a capacitive element between the coupled lines is a direct and well-known technique for controlling the odd-mode (differential-mode) characteristic impedance of the coupled-line structure. Motivation to combine/modify: Pye explicitly identifies the goal of controlling both even-mode and odd-mode impedances to achieve desired balun performance ( § 0037– § 0038, § 0103). It would have been well within the purview of a person of ordinary skill in the RF/microwave circuit design field — who routinely employs capacitive loading between coupled lines to tune odd-mode impedance — to add a discrete capacitive impedance restriction element between the coupled lines of Pye's balun to independently control the odd-mode impedance and further broaden bandwidth. There is no unexpected result or teaching away from this modification. Accordingly, c laim 3 is obvious over Pye, combined with the general knowledge of a person of ordinary skill in the art regarding coupled-line circuit design techniques. Regarding Claim 4 , Pye's lumped circuit model (Figure 1B, § 0067– § 0069) expressly discloses capacitor 105 between the striplines modeling inter-line coupling, and capacitors 113, 115, 116, 117 (between ports and ground) modeling the coupling structure at each port of the coupled-line device. Pye's multi-port model (Figure 1C, § 0070– § 0075) further discloses capacitors 162 and 164 "modeling the electrical coupling between the striplines 104 and 106" — capacitor 162 positioned between ports P1 and P4, and capacitor 164 positioned between ports P2 and P3 ( § 0071). A person of ordinary skill in the art, recognizing that capacitors 162 (between input port P1 and neighboring port P4) and 164 (between output/through port P2 and neighboring port P3) can be physically realized as discrete loading capacitors to restrict odd-mode impedance — as directly modeled in Pye — would find the exact claim structure of Claim 4 obvious. The first and second capacitors of Claim 4 correspond directly to the discrete implementation of Pye's modeled capacitors 162 and 164. The specific configuration (one capacitor at the input port side between neighboring ports, and one capacitor at the output port side between neighboring ports) is taught explicitly by Pye's lumped model and would be an obvious implementation choice. Regarding Claim 5, Pye explicitly discloses amplifier 832 (Figure 8C, § 0126–[0127), which includes a coupled-line balun 200 feeding a differential gain stage 834 that produces differential output signals Vout+ and Vout−. The gain stage 834 constitutes the "amplification circuit unit." The differential outputs Vout+ and Vout− constitute the "at least one output terminal." Additionally, Pye discloses in Figure 8B a receiver system (RX die 812) with a coupled-line balun 200 interfacing with both input and output paths, and in Figure 8A a receiver system 800 with the balun at the input followed by mixer 804, amplifier 806, anti-alias filter 808, and ADC 810 in a signal chain. Pye further discloses that the coupled-line balun (with series RL network, i.e., resistor 110 at through port P2) is usable for "a wide variety of applications" including at multiple points in receiver/amplifier chains ( § 0120– § 0129). Pye's Figure 8B shows the coupled-line balun 200 on the RX die 812 as one balun in a multi-die system, demonstrating use of multiple baluns. Pye explicitly teaches that "one or more of the above coupled-line baluns implemented in accordance with any of the principles and advantages discussed herein can be included in various electronic devices" ( § 0129). Each balun (matching circuit unit) includes resistor 110 (a resistance). Claim 5 additionally requires a capacitor between the coupled lines (in addition to the resistance at the through port), this limitation renders Claim 5 non-anticipatable by Pye alone. However, as analyzed under Claim 3 and Claim 4 above, it would have been obvious to a person of ordinary skill in the art to include a capacitor between the coupled lines to control odd-mode impedance, based on Pye's own lumped model teaching capacitors 162 and 164 between the ports of the coupled lines ( § 0071). To the extent the "plurality of matching circuit units connected to two input terminals and the output terminal respectively" (i.e., one balun at each terminal of the differential amplifier) is argued not to be shown in a single embodiment of Pye, it would still have been obvious: Pye teaches that multiple baluns can be deployed in a system ( § 0129, Figure 8B), and applying a matching balun to each terminal of a differential amplifier to achieve impedance matching at each port would be within the routine skill and ordinary design practice of an RF circuit designer. Claim 6 is substantively identical to the limitation analyzed under Claim 4, directed to the specific placement of capacitors within the 4-port coupled-line structure. As fully analyzed under Claim 4, Pye's multi-port lumped circuit model (Figure 1C, § 0071) explicitly discloses capacitor 162 between input port P1 and neighboring port P4, and capacitor 164 between output/through port P2 and neighboring port P3 — directly corresponding to the claimed capacitor placement. The discrete implementation of this modeled structure is an obvious design step for a person of ordinary skill in the art. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Enter examiner's name" \* MERGEFORMAT HAFIZUR RAHMAN whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)270-0659 . The examiner can normally be reached FILLIN "Work schedule?" \* MERGEFORMAT M-F: 10-6 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Andrea Lindgren Baltzell can be reached on FILLIN "SPE Phone?" \* MERGEFORMAT (571) 272-1769 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. /HAFIZUR RAHMAN/ Primary Examiner, Art Unit 2843.