Prosecution Insights
Last updated: July 17, 2026
Application No. 18/538,339

METHOD FOR MANUFACTURING A SEMICONDUCTOR DEVICE

Non-Final OA §103§112
Filed
Dec 13, 2023
Priority
Dec 13, 2022 — FR 2213224
Examiner
HAWKINS, IHSAN TAIWO
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
COMMISSARIAT À L'ÉNERGIE ATOMIQUE ET AUX ÉNERGIES ALTERNATIVES
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
10 currently pending
Career history
5
Total Applications
across all art units

Statute-Specific Performance

§103
76.0%
+36.0% vs TC avg
§102
16.0%
-24.0% vs TC avg
§112
8.0%
-32.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§103 §112
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Priority Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. Claim Objections Claims 9 and 12 are objected to because of the following informalities: Claim 8 mentions the second region comprising of several portions whereas claim 9, which is dependent on claim 8 mentions "said portion". It is unclear as to what this is referring to. Claim 11 mentions the second region comprising of several portions whereas claim 12, which is dependent on claim 12 mentions "said portion". It is unclear as to what this is referring to. Claim 12 mentions “the electrical isolation trenches”. However, there is no mention of “electrical isolation trenches” in any claims from which this claim depends. Appropriate correction is required. Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims 1-5 and 7-13 are rejected under 35 U.S.C. 103 as being unpatentable over Brunco (US 20170250183 A1) in view of Chang et al. (US 20220231158 A1) hereinafter referred to as "Chang". Regarding claim 1, Brunco teaches a method for manufacturing a semiconductor device comprising a first semiconductor zone optimized for electron conduction and a second semiconductor zone optimized for hole conduction, the method comprising: providing a multilayer structure comprising: a substrate (Fig. 2, element 200; ¶: [0021]), and a silicon-germanium layer disposed on the substrate (Fig. 5, element 500; ¶: [0043]); defining in the multilayer structure a first region for containing the first semiconductor zone and a second region for containing the second semiconductor zone (Fig. 2, element 202, 204; ¶: [0033]). Brunco does not teach subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region, said portion comprising prior to laser annealing a part of the silicon-germanium layer, said portion having, after laser annealing, a germanium concentration gradient with a germanium concentration which increases towards an upper face of said portion Chang teaches subjecting the multilayer structure to laser annealing so as to modify a portion of the multilayer structure located in the second region, said portion comprising prior to laser annealing a part of the silicon- germanium layer, said portion having, after laser annealing, a germanium concentration gradient with a germanium concentration which increases towards an upper face of said portion (Fig. 5, element 80; ¶: [0040]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a non-uniform concentration of Ge in order to enhance on-state current by higher carrier mobility and lower threshold voltage (¶: [0032]). Regarding claim 2, Brunco in view of Chang teach the method according to claim 1. Brunco does not teach the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer. Chang teaches the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer (Fig. 4, element 22; ¶: [0039]/[0072]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a non-uniform concentration of Ge in order to enhance on-state current by higher carrier mobility and lower threshold voltage (¶: [0032]). Regarding claim 3, Brunco in view of Chang teach the method according to claim 2. Brunco further teaches the multilayer structure further comprising a laser reflection layer disposed on the protective layer and configured to decrease efficiency of laser annealing, the method further comprising, prior to laser annealing, removing a portion of the laser reflection layer located in the second region of the multilayer structure (Fig. 8-9, element 400; ¶: [0049]). Regarding claim 4, Brunco in view of Chang teach the method according to claim 3 and Brunco further teaches removing the protective layer in the second region of the multilayer structure after laser annealing (¶: [0037]) as well as removing the laser reflection layer and the protective layer in the first region of the multilayer structure (Fig. 9-10, element 400 ; ¶: [0051]). Regarding claim 5, Brunco in view of Chang teach the method according to claim 3. Brunco further teaches defining of the first and second regions of the multilayer structure being performed after the providing of the multilayer structure and comprising the following sub-steps of: etching a trench in the multilayer structure, the trench extending through the laser reflection layer, the protective layer and the silicon-germanium layer to the substrate, and filling the trench with an electrically insulating material over at least an entire thickness of the silicon-germanium layer (Fig. 12, element 202, 204; ¶: [0019]). Regarding claim 7, Brunco in view of Chang teach the method according to claim 1 but Brunco does not teach the silicon-germanium layer having prior to laser annealing a germanium concentration of between 5% and 10%. Chang teaches the silicon-germanium layer having prior to laser annealing a germanium concentration of between 5% and 10% (Fig. 4, element 15; ¶: [0087]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a smaller Ge concentration because a high Ge concentration channel would suffer worse current leakage, due to less gate control at the center of the fin structure. (¶: [0031]) Regarding claim 8, Brunco in view of Chang teach the method according to claim 1 while Brunco further teaches the silicon-germanium layer comprising a plurality of fins (Fig. 6, element 600 a-b; ¶: [0044]) distributed between the first and second regions of the multilayer structure; and the multilayer structure further comprising electrical isolation trenches (Fig. 7, element 700; ¶: [0046]) separating the fins from each other; the multilayer structure being subjected to laser annealing so as to modify several portions of the multilayer structure located in the second region, each portion comprising at least one part of a fin prior to laser annealing (¶: [0037]). Brunco does not teach the silicon-germanium layer having a germanium concentration of between 5% and 10% prior to laser annealing. Chang teaches the silicon-germanium layer having a germanium concentration of between 5% and 10% prior to laser annealing (Fig. 4, element 15; ¶: [0087]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a smaller Ge concentration because a high Ge concentration channel would suffer worse current leakage, due to less gate control at the center of the fin structure. (¶: [0031]) Regarding claim 9, Brunco in view of Chang teach the method according to claim 8. Brunco further teaches the providing of the multilayer structure comprising the following substeps of: depositing the silicon-germanium layer onto the substrate (Fig. 5., element 500.; ¶: [0043]); etching the silicon-germanium layer so as to form the plurality of fins (Fig. 6.; ¶: [0044]); forming the electrical isolation trenches between the fins, and depositing the protective layer onto the silicon-germanium layer (Fig. 7.; ¶: [0047]). Brunco does not however, teach the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer. Chang teaches the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer (Fig. 4, element 22; ¶: [0039]/[0072]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a non-uniform concentration of Ge in order to enhance on-state current by higher carrier mobility and lower threshold voltage (¶: [0032]). Regarding claim 10, Brunco in view of Chang teach the method according to claim 9. Brunco does not teach the protective layer and the electrical isolation trenches being formed by a same electrically insulating material. Chang teaches the protective layer and the electrical isolation trenches being formed by a same electrically insulating material (Fig. 6, element 22, 30; ¶: [0039]/[0043]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a material that can be cured and then annealed to remove un-desired elements to form silicon oxide. (¶: [0043]) Regarding claim 11, Brunco in view of Chang teach the method according to claim 1. Brunco further teaches the silicon-germanium layer having, before laser annealing, a germanium concentration greater than or equal to 30% (¶: [0043]) as well as the silicon-germanium layer and a portion of the substrate being patterned in the form of a plurality of fins (Fig. 6, element 600 a-b; ¶: [0044]); and the multilayer structure being subjected to laser annealing so as to modify several portions of the multilayer structure located in the second region, each portion comprising prior to laser annealing at least one part of a fin (¶: [0037]); the method further comprising, after laser annealing, etching the silicon- germanium layer in the first region of the multilayer structure, etching the silicon-germanium layer being selective with respect to the substrate (¶: [0048]). Regarding claim 12, Brunco in view of Chang teach the method according to claim 1.Brunco further teaches the providing of the multilayer structure comprising the following substeps of: depositing the silicon-germanium layer onto the substrate (Fig. 5., element 500.; ¶: [0043]); etching the silicon-germanium layer so as to form the plurality of fins (Fig. 6,600 ¶: [0044]); forming the electrical isolation trenches between the fins, and depositing the protective layer onto the silicon-germanium layer (Fig. 7.; ¶: [0047]). Brunco does not teach the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer. Chang teaches the multilayer structure further comprising a protective layer disposed on the silicon-germanium layer, wherein said portion extends up to the protective layer prior to laser annealing and wherein said portion has after laser annealing a germanium concentration which increases towards an interface with the protective layer (Fig. 4, element 22; ¶: [0039]/[0072]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a non-uniform concentration of Ge in order to enhance on-state current by higher carrier mobility and lower threshold voltage (¶: [0032]). Regarding claim 13, Brunco in view of Chang teach the method according to claim 12. Brunco does not teach the protective layer and the electrical isolation trenches being formed by a same electrically insulating material. Chang however, teaches the protective layer and the electrical isolation trenches being formed by a same electrically insulating material (Fig. 6, element 22, 30; ¶: [0039]/[0043]). Before the effective filing date, it would have been obvious to one having ordinary skill in the art to have a material that can be cured and then annealed to remove un-desired elements to form silicon oxide. (¶: [0043]) Claim 6 is rejected under 35 U.S.C. 103 as being unpatentable over Brunco in view of Chang and Cheng et al. (US 20220157816 A1) hereinafter referred to as "Cheng". Regarding claim 6, Brunco in view of Chang teach the method according to claim 1. Brunco in view of Chang do not teach the silicon-germanium layer having a germanium concentration greater than or equal to 10% prior to laser annealing; the multilayer structure further comprises a silicon layer disposed on the silicon-germanium layer, and said portion further comprises prior to laser annealing a part of the silicon layer. Cheng teaches the silicon-germanium layer having a germanium concentration greater than or equal to 10% prior to laser annealing (Fig. 14, element 142; ¶: [0083-0084]); the multilayer structure further comprises a silicon layer disposed on the silicon-germanium layer, and said portion further comprises prior to laser annealing a part of the silicon layer (Fig. 5B, element 36A; ¶: [0063]). It would have been obvious to one having ordinary skill in the art before the effective filing date to have a germanium concentration of greater than or equal to 10% as it is beneficial to the pFETs (¶: [0084]). It would also be obvious to one having ordinary skill in the art before the effective filing date to include a silicon layer as the silicon germanium layer would be amenable to etching with respect to said silicon layer (¶: [0063]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Brunco in view of Chang and Zhou (US 20180337101 A1). Regarding claim 15, Brunco in view of Chang teach the method according to claim 1. Brunco in view of Chang fail to teach forming an N-channel field effect transistor, referred to as an nFET transistor, in the first region of the multilayer structure and forming a P-channel field effect transistor , referred to as a pFET transistor, in the second region of the multilayer structure. Zhou teaches forming an N-channel field effect transistor, referred to as an nFET transistor, in the first region of the multilayer structure and forming a P-channel field effect transistor , referred to as a pFET transistor, in the second region of the multilayer structure (Fig. 12, element 601, 602; ¶: [0025]). It would have been obvious to one having ordinary skill in the art before the effective filing date to form both an nFET as well as a pFET within the same structure in order to utilize turning the structure on and off from the two sides of the structure (¶: [0004]). Allowable Subject Matter The following is a statement of reasons for the indication of allowable subject matter: Claim 14 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims. The following is an examiner’s statement of reasons for allowance, which paraphrases and summarizes the claimed invention without intending to be limiting, wherein the legally defined scope of the claimed invention is defined by the allowed claims themselves in view of the written description under 35 USC 112. This statement is not intended to necessarily state all the reasons for allowance or all the details why the claims are allowed and has not been written to specifically or impliedly state that all the reasons for allowance are set forth (MPEP 1302.14). Regarding claim 14, the references of the Prior Art of record and considered pertinent to the applicant's disclosure and to the examiner’s knowledge does not teach or render obvious, at least to one skilled in the art, the instant invention regarding: “laser annealing is performed by exposing the multilayer structure to laser radiation having a wavelength of between 200 nm and 600 nm and an energy density of between 0.1 J/cm2 and 10 J/cm2 for a duration of between 10 ns and 1000 ns”, as recited in Claim 14, with the remaining features. Any comments considered necessary by applicant must be submitted no later than the payment of the issue fee and, to avoid processing delays, should preferably accompany the issue fee. Such submissions should be clearly labeled “Comments on Statement of Reasons for Allowance.” Citation of Pertinent Prior Art The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Wu (US 11373870 B2. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IHSAN HAWKINS whose telephone number is (571)272-8594. The examiner can normally be reached Mon-Thu 7:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /I.H./Examiner, Art Unit 2899 /LAWRENCE C TYNES JR./Examiner, Art Unit 2899
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Prosecution Timeline

Dec 13, 2023
Application Filed
Apr 30, 2026
Non-Final Rejection (signed) — §103, §112
Jul 01, 2026
Non-Final Rejection mailed — §103, §112 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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