The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Response to Amendment
This office action has been issued in response to the response filed 4/2/26. Claims 1-9, 15-20 are pending in this application. Applicant's arguments have been carefully considered, but are not persuasive in view of the “response to arguments” section below. The examiner appreciates Applicant's effort to distinguish over the cited prior art by presenting arguments/amendments in an attempt to distinguish or clarify the claimed invention, however, upon further consideration and/or search, the claims remain unpatentable over the cited prior art for the reasons articulated in the “response to arguments” section below. All claims pending in the instant application remain rejected and clarification and/or elaboration regarding why the claims are not in condition for allowance will hereafter be provided in order to efficiently further prosecution. Accordingly, this action is made FINAL.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Azad (US patent # 11429481) in view of Reed (US PGPUB # 20170161142) further in view of Fry et al (US PGPUB # 20110029807). With respect to independent claims 1, 15 Azad/Reed/Fry discloses: A memory device comprising:
a random-access memory circuit having a plurality of memory cells, a read port, a write port, and an output port [DRAM 105 with read port/input, write port/input and output port – Azad fig 1, col 6 L 63 – col 7 L 9] [memory cells in DRAM – Reed 0003];
a first multiplexer having a functional read input, a scrub read input, a scrub read enable input, and a read request output, the read request output coupled to the read port [read MUX 140 selects functional ADDR 120 vs scrub ADDR 160, OR gate signals DRAM read when RENABLE 110 (functional) or READ 170 (scrub enable) is high and the MUX/OR output are coupled to the DRAM read input/port - Azad fig 1];
a second multiplexer having a functional write input, a scrub write input, a scrub write enable input, and a write request output, the write request output coupled to the write port [write MUX 145 selects functional ADDR 125 vs scrub ADDR 155, OR gate signals DRAM write when WENABLE 115 (functional) or WRITE 165 (scrub enable) is high and the MUX/OR output are coupled to the DRAM write input/port - Azad fig 1]; and
a logic circuit [any combination of components facilitating scrub functionality including correction logic 150 - Azad fig 1] configured to scrub, via the scrub write input, at least one of the memory cells based on the scrub read input while the scrub read enable input and/or the scrub write enable input are asserted [idle scrub read, ECC check 175 and conditional corrected (scrub) write 155 - Azad fig 2-4],
wherein the logic circuit maintains a current scrub address [current value of address counter - Azad col 7 lines 25-32] [current memory scrub address – Fry 0055], and wherein, when a functional write operation is occurring at the current scrub address, the logic circuit permits the functional write to occur and proceeds to the next address; no scrubbing occurs during the functional write operation [suggested by Azad as address specific arbitration, method 400 for correcting errors in a memory, step 405 – Azad fig 4; where permitting functional write to occur is disclosed as discarding corrected data when an address collision occurs with a scrub operation – Azad step 235 in fig 4; Azad/Reed does not explicitly disclose “permits the functional write to occur and proceeds to the next address”. Nevertheless in the same field of endeavor Fry teaches implementing enhanced memory reliability using memory scrub operations, wherein permitting a functional write to occur and proceeds to the next address is disclosed in fig 5 as incrementing a scrub address to a next scrub address and advancing a scrub pointer even when no scrub write occurs (when data is valid)].
Azad does not explicitly disclose memory cells in the memory array.
Nevertheless, in the same field of endeavor Reed teaches DRAM comprised of memory cells (Reed 0003, 0034-0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize memory cells as part of a memory array in the invention of Azad as taught by Reed because cells of an array are a typical and well-known design choice for a memory array which are conducive to row/column access operations (Reed 0003, 0008, 0042).
Azad/Reed does not explicitly disclose “permits the functional write to occur and proceeds to the next address”.
Nevertheless in the same field of endeavor Fry teaches implementing enhanced memory reliability using memory scrub operations, wherein permitting a functional write to occur and proceeds to the next address is disclosed in fig 5 as incrementing a scrub address to a next scrub address and advancing a scrub pointer even when no scrub write occurs (when data is valid)].Nevertheless, in the same field of endeavor Reed teaches DRAM comprised of memory cells (Reed 0003, 0034-0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to permit a functional write to occur and proceed to the next address in the invention of Azad/Reed as taught by Fry because it would be advantageous for improving system data integrity overall system integrity and reliability (Fry 0040).
With respect to dependent claim 2, 18 Azad/Reed discloses wherein the read port is configured to receive a read request signal, the write port configured to receive a write request signal, and the output port configured to output data from at least one of the memory cells responsive to the read request signal, and wherein the random-access memory circuit is configured to write data to at least one of the memory cells responsive to the write request signal [Azad fig 1, col 3 L 63 – col L 14] [Reed 0040-0044].
With respect to dependent claim 3, 19 Azad/Reed discloses wherein the read request signal is output on the read request output and includes one of the functional read input and the scrub read input based on the scrub read enable input [read request is based on output when READ 170 (scrub-read-enable) or functional RENABLE 110 is active; MUX 140 selects scrub 160 over functional 120 operation as read source - Azad fig 1, col 3 L 63 – col L 14] [Reed 0012-0016, 0061-0063, fig 4-8].
With respect to dependent claim 4, 20 Azad/Reed/Fry discloses wherein the write request signal is output on the write request output and includes one of the functional write input and the scrub write input based on the scrub write enable input [write request is based on output when WRITE 165 (scrub-write-enable) or functional WENABLE 115 is active; MUX 145 selects scrub 155 over functional 125 operation as read source - Azad fig 1, col 3 L 63 – col L 14] [corrected/scrub write replaces functional writes Reed fig 3, paragraph 0054-0055, 0062].
With respect to dependent claim 5 Azad/Reed/Fry discloses wherein the logic circuit is configured to scrub at least one of the memory cells while a scrub enable signal is asserted [when READ 170 (scrub-read-enable) & WRITE 165 (scrub-write-enable) facilitates scrub operations – Azad fig 1-4].
With respect to dependent claim 6 Azad/Reed/Fry discloses wherein the logic circuit is configured to read data from at least one of the memory cells based on the scrub read input [MUX 140 can select scrub read address 160 when READ 170 is active/high such that a read is based on scrub read input – Azad fig 1].
With respect to dependent claim 7 Azad/Reed/Fry discloses wherein the logic circuit is configured to write data to the at least one of the memory cells based on the scrub write input [MUX 145 can select scrub write address 155 when WRITE 165 is active/high such that a write is based on scrub write input – Azad fig 1].
With respect to dependent claim 8 Azad/Reed/Fry discloses wherein the logic circuit is configured to permit a scrub write to occur based on the scrub write input while the scrub write enable input is asserted [scrub write 165 enables write, MUX 145 & OR 135 selects scrub write data 155 - Azad fig 1].
With respect to dependent claim 9 Azad/Reed/Fry discloses wherein the logic circuit is configured to permit a scrub read to occur based on the scrub read input while the scrub read enable input is asserted [scrub read 170 enables read, MUX 140 & OR 130 selects scrub read data 160- Azad fig 1].
With respect to dependent claim 16 Azad/Reed/Fry discloses wherein the read port is coupled to a first multiplexer having a functional read input, a scrub read input, the scrub read enable input, and a read request output, the read request output coupled to the read port [read MUX 140 selects functional ADDR 120 vs scrub ADDR 160, OR gate signals DRAM read when RENABLE 110 (functional) or READ 170 (scrub enable) is high and the MUX/OR output are coupled to the DRAM read input/port - Azad fig 1].
With respect to dependent claim 17 Azad/Reed/Fry discloses wherein the write port is coupled to a second multiplexer having a functional write input, a scrub write input, the scrub write enable input, and a write request output, the write request output coupled to the write port [write MUX 145 selects functional ADDR 125 vs scrub ADDR 155, OR gate signals DRAM write when WENABLE 115 (functional) or WRITE 165 (scrub enable) is high and the MUX/OR output are coupled to the DRAM write input/port - Azad fig 1].
Response to Arguments
Applicant's arguments have been fully considered but are not persuasive in view of the prior art. All claims pending in the instant application remain rejected. Please note that any rejections/objection not maintained from the previous Office Action have been rectified either by applicant's amendment and/or persuasive argument(s).
Regarding applicant’s arguments on page 1-3, that amended claims are not taught by the cited art [The examiner respectfully submits that amended grounds of rejection necessitated by amendments to the claims have rendered the remarks moot/unpersuasive, particularly in view of the combination of prior art including newly found Fry reference as integrated into the rationale above.]
Remaining arguments are understood to be predicated on the previous arguments being persuasive and thus are unpersuasive at least on dependency merits.
All remarks are understood to have been addressed herein. If any issues remain which may be clarified by the examiner, the applicant is invited to contact the examiner to set up a telephone interview.
When responding to the office action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any extension fee pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to MARWAN AYASH whose telephone number is (571)270-1179. The examiner can normally be reached 9a-730p M-R.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Rocio del Mar Perez-Velez can be reached on 571-270-5935. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/Marwan Ayash/ - Examiner - Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133
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