The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
DETAILED ACTION
Election/Restrictions
Applicant’s election, on 11/10/25, without traverse of Invention I is acknowledged. Claims 10-14 are withdrawn from consideration. Claims 1-9, 15-20 remain pending.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
The factual inquiries set forth in Graham v. John Deere Co., 383 U.S. 1, 148 USPQ 459 (1966), that are applied for establishing a background for determining obviousness under 35 U.S.C. 103(a) are summarized as follows:
1. Determining the scope and contents of the prior art.
2. Ascertaining the differences between the prior art and the claims at issue.
3. Resolving the level of ordinary skill in the pertinent art.
4. Considering objective evidence present in the application indicating obviousness or nonobviousness.
Claims 1-9, 15-20 are rejected under 35 U.S.C. 103 as being unpatentable over Azad (US patent # 11429481) in view of Reed (US PGPUB # 20170161142). With respect to independent claims 1, 15 Azad/Reed discloses: A memory device comprising:
a random-access memory circuit having a plurality of memory cells, a read port, a write port, and an output port [DRAM 105 with read port/input, write port/input and output port – Azad fig 1, col 6 L 63 – col 7 L 9] [memory cells in DRAM – Reed 0003];
a first multiplexer having a functional read input, a scrub read input, a scrub read enable input, and a read request output, the read request output coupled to the read port [read MUX 140 selects functional ADDR 120 vs scrub ADDR 160, OR gate signals DRAM read when RENABLE 110 (functional) or READ 170 (scrub enable) is high and the MUX/OR output are coupled to the DRAM read input/port - Azad fig 1];
a second multiplexer having a functional write input, a scrub write input, a scrub write enable input, and a write request output, the write request output coupled to the write port [write MUX 145 selects functional ADDR 125 vs scrub ADDR 155, OR gate signals DRAM write when WENABLE 115 (functional) or WRITE 165 (scrub enable) is high and the MUX/OR output are coupled to the DRAM write input/port - Azad fig 1]; and
a logic circuit [any combination of components facilitating scrub functionality including correction logic 150 - Azad fig 1] configured to scrub, via the scrub write input, at least one of the memory cells based on the scrub read input while the scrub read enable input and/or the scrub write enable input are asserted [idle scrub read, ECC check 175 and conditional corrected (scrub) write 155 - Azad fig 2-4].
Azad does not explicitly disclose memory cells in the memory array.
Nevertheless, in the same field of endeavor Reed teaches DRAM comprised of memory cells (Reed 0003, 0034-0035).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the invention to utilize memory cells as part of a memory array in the invention of Azad as taught by Reed because cells of an array are a typical and well-known design choice for a memory array which are conducive to row/column access operations (Reed 0003, 0008, 0042).
With respect to dependent claim 2, 18 Azad/Reed discloses wherein the read port is configured to receive a read request signal, the write port configured to receive a write request signal, and the output port configured to output data from at least one of the memory cells responsive to the read request signal, and wherein the random-access memory circuit is configured to write data to at least one of the memory cells responsive to the write request signal [Azad fig 1, col 3 L 63 – col L 14] [Reed 0040-0044].
With respect to dependent claim 3, 19 Azad/Reed discloses wherein the read request signal is output on the read request output and includes one of the functional read input and the scrub read input based on the scrub read enable input [read request is based on output when READ 170 (scrub-read-enable) or functional RENABLE 110 is active; MUX 140 selects scrub 160 over functional 120 operation as read source - Azad fig 1, col 3 L 63 – col L 14] [Reed 0012-0016, 0061-0063, fig 4-8].
With respect to dependent claim 4, 20 Azad/Reed discloses wherein the write request signal is output on the write request output and includes one of the functional write input and the scrub write input based on the scrub write enable input [write request is based on output when WRITE 165 (scrub-write-enable) or functional WENABLE 115 is active; MUX 145 selects scrub 155 over functional 125 operation as read source - Azad fig 1, col 3 L 63 – col L 14] [corrected/scrub write replaces functional writes Reed fig 3, paragraph 0054-0055, 0062].
With respect to dependent claim 5 Azad/Reed discloses wherein the logic circuit is configured to scrub at least one of the memory cells while a scrub enable signal is asserted [when READ 170 (scrub-read-enable) & WRITE 165 (scrub-write-enable) facilitates scrub operations – Azad fig 1-4].
With respect to dependent claim 6 Azad/Reed discloses wherein the logic circuit is configured to read data from at least one of the memory cells based on the scrub read input [MUX 140 can select scrub read address 160 when READ 170 is active/high such that a read is based on scrub read input – Azad fig 1].
With respect to dependent claim 7 Azad/Reed discloses wherein the logic circuit is configured to write data to the at least one of the memory cells based on the scrub write input [MUX 145 can select scrub write address 155 when WRITE 165 is active/high such that a write is based on scrub write input – Azad fig 1].
With respect to dependent claim 8 Azad/Reed discloses wherein the logic circuit is configured to permit a scrub write to occur based on the scrub write input while the scrub write enable input is asserted [scrub write 165 enables write, MUX 145 & OR 135 selects scrub write data 155 - Azad fig 1].
With respect to dependent claim 9 Azad/Reed discloses wherein the logic circuit is configured to permit a scrub read to occur based on the scrub read input while the scrub read enable input is asserted [scrub read 170 enables read, MUX 140 & OR 130 selects scrub read data 160- Azad fig 1].
With respect to dependent claim 16 Azad/Reed discloses wherein the read port is coupled to a first multiplexer having a functional read input, a scrub read input, the scrub read enable input, and a read request output, the read request output coupled to the read port [read MUX 140 selects functional ADDR 120 vs scrub ADDR 160, OR gate signals DRAM read when RENABLE 110 (functional) or READ 170 (scrub enable) is high and the MUX/OR output are coupled to the DRAM read input/port - Azad fig 1].
With respect to dependent claim 17 Azad/Reed discloses wherein the write port is coupled to a second multiplexer having a functional write input, a scrub write input, the scrub write enable input, and a write request output, the write request output coupled to the write port [write MUX 145 selects functional ADDR 125 vs scrub ADDR 155, OR gate signals DRAM write when WENABLE 115 (functional) or WRITE 165 (scrub enable) is high and the MUX/OR output are coupled to the DRAM write input/port - Azad fig 1].
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Kalyanasundharam US PGPUB # 20130139008 teaches: An error injection module for injecting errors into an ECC memory selects a target address associated with the ECC memory, selects an error injection pattern, and sets a redirect address of the scrubber to the target address. During an injection mode of the scrubber, the error injection module injects the error injection pattern into the target address of the ECC memory with the scrubber.
Cargnoni US PGPUB # 20040215886 teaches: A method of reducing errors in a cache memory of a computer system (e.g., an L2 cache) by periodically issuing a series of purge commands to the L2 cache, sequentially flushing cache lines from the L2 cache to an L3 cache in response to the purge commands, and correcting errors (single-bit) in the cache lines as they are flushed to the L3 cache. Purge commands are issued only when the processor cores associated with the L2 cache have an idle cycle available in a store pipe to the cache. The flush rate of the purge commands can be programmably set, and the purge mechanism can be implemented either in software running on the computer system, or in hardware integrated with the L2 cache. In the case of the software, the purge mechanism can be incorporated into the operating system. In the case of hardware, a purge engine can be provided which advantageously utilizes the store pipe that is provided between the L1 and L2 caches. The L2 cache can be forced to victimize cache lines, by setting tag bits for the cache lines to a value that misses in the L2 cache (e.g., cache-inhibited space). With the eviction mechanism of the cache placed in a direct-mapped mode, the address misses will result in eviction of the cache lines, thereby flushing them to the L3 cache.
When responding to this Office Action, any new claims and/or limitations should be accompanied by a reference as to where the new claims and/or limitations are supported in the original disclosure.
Any inquiry concerning this communication or earlier communication from the examiner should be directed to MARWAN AYASH at (571)270-1179. The examiner may be reached via email at marwan.ayash@uspto.gov – provided that applicant files form PTO/SB/439 to authorize internet communication, found online at http://www.uspto.gov/sites/default/files/documents/sb0439.pdf
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/Marwan Ayash/
Examiner, Art Unit 2133
/ROCIO DEL MAR PEREZ-VELEZ/Supervisory Patent Examiner, Art Unit 2133