Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings are objected to under 37 CFR 1.83(a). The drawings must show every feature of the invention specified in the claims. Therefore, the following must be shown or the features canceled from the claims 1-20 as applicable:
the first conductive layer including associated portions and/or sublayers
the second conductive layer including associated portions and/or sublayers
the third conductive layers including associated portions and/or sublayers
the fourth conductive layer including associated portions and/or sublayers
the fifth conductive layer including associated portions and/or sublayers
the first electrode
the second electrode
No new matter should be entered.
Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-20 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the enablement requirement. The claims contains subject matter which was not described in the specification in such a way as to enable one skilled in the art to which it pertains, or with which it is most nearly connected, to make and/or use the invention.
Claims 1-20, recite limitations regarding the following components: a first conductive layer including associated portions and/or sublayers, a second conductive layer including associated portions and/or sublayers, a third conductive layers including associated portions and/or sublayers, a fourth conductive layer including associated portions and/or sublayers, a fifth conductive layer including associated portions and/or sublayers, a first electrode, and a second electrode
The non-provisional specification does not provide a description of the invention and its associated components that would be sufficient to enable one of ordinary skill in the art to make and/or use the memory device without undue experimentation. This is due to the specification containing no disclosures which adequately describe what conductive layers functions as the first through fifth conductive layers as well as their associated portions.
Further, the specification is silent with regard to relative positioning which could lead one to assume what conductive layers could potentially function as the first through fifth conductive layers. As the memory device contains to the numerous components that could potentially qualify as conductive layers and electrodes, without proper indications the proper description of relative positioning of the components the examiner notes the device cannot be made without undue experimentation.
The Examiner respectfully suggests all the claim limitations be reviewed to ensure the limitations are properly reflected as they are described in the specification.
The following is a quotation of 35 U.S.C. 112(b):
(b) CONCLUSION.—The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the inventor or a joint inventor regards as the invention.
The following is a quotation of 35 U.S.C. 112 (pre-AIA ), second paragraph:
The specification shall conclude with one or more claims particularly pointing out and distinctly claiming the subject matter which the applicant regards as his invention.
Claims 1-20 rejected under 35 U.S.C. 112(b) or 35 U.S.C. 112 (pre-AIA ), second paragraph, as being indefinite for failing to particularly point out and distinctly claim the subject matter which the inventor or a joint inventor (or for applications subject to pre-AIA 35 U.S.C. 112, the applicant), regards as the invention.
In regard to claim 1, the limitations state “a first conductive layer; a second conductive layer arranged with the first conductive layer in a first direction in a first region; a plurality of third conductive layers arranged in the first region on a side opposite the first conductive layer in the first direction with respect to the second conductive layer in a mutually separated manner in the first direction” in lines 2-10. It is unclear what the applicant regards as the first through third conductive layer as the layers shown or described in the specification do not adequately apply to limitation.
In regard to claim 2, the limitations states the first conductive layer further includes a fifth portion in lines 2-3. It is unclear what the applicant regards as the fifth portion as the specification only describes the he first conductive layer having a first and second portion.
Further in regard to claims 1-20, where applicable it is unclear what the applicant regards as a first conductive layer including associated portions and/or sublayers, a second conductive layer including associated portions and/or sublayers, a third conductive layer including associated portions and/or sublayers, a fourth conductive layer including associated portions and/or sublayers, a fifth conductive layer including associated portions and/or sublayers, a first electrode, and a second electrode. The device contains a plurality of conductive components and multiple electrodes, however, the specification does not further serve to clearly specify to one of ordinary skill in the art which elements act as a first conductive layer including associated portions and/or sublayers, a second conductive layer including associated portions and/or sublayers, a third conductive layer including associated portions and/or sublayers, a fourth conductive layer including associated portions and/or sublayers, a fifth conductive layer including associated portions and/or sublayers, a first electrode, and a second electrode.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
As best understood, claims 1-6, 8, 17-18 and 20 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Yoshimizu (US 2021/0083001 A1).
In regard to claim 1, Yoshimizu teaches a memory device (a magnetic memory device) (Fig. 2 and paragraph 5), comprising:
a first conductive layer (a conductive layer 121b and semiconductor layers 101 and 102) (Fig. 2, Fig. 5 and paragraphs 57, 61 and 88);
a second conductive layer (a multi-layered catalyst layer 121a) arranged with the first conductive layer in a first direction (in a Z direction) in a first region (in one portion of the array area the multi-layered catalyst layer 121a is shown on the conductive layer 121b in the Z2 direction in Fig. 2) (Fig. 2 and paragraphs 89);
a plurality of third conductive layers (a plurality of interconnect layers 104) arranged in the first region on a side opposite the first conductive layer in the first direction with respect to the second conductive layer in a mutually separated manner in the first direction (in the portion of the cell area the plurality of interconnect layers 104 is separated from the conductive layer 121b) (Fig. 2 and paragraph 62);
a first conductor (a contact plugs 107) extending in the first direction and intersecting extensions of the third conductive layers in a second region different from the first region (the contact plugs 107 in the peripheral region is shown intersecting the interconnect layers 104 extending in the Y direction in Fig. 2) (Fig. 2 and paragraphs 54 and 62); and
a memory pillar (a memory pillars MP) extending in the first direction, of which portions intersecting the third conductive layers function as memory cells (the memory pillars MP is shown intersecting the interconnect layers 104 extending in the Y direction in Fig. 2) (Fig. 2 and paragraph 57),
wherein the second conductive layer includes a first portion (a bottom layer of the multi-layered catalyst layer 121a to the far left of the cell array as shown in Fig. 2) that extends in a plane (Y plane) intersecting the first direction (the Y direction intersects the Z direction) and is in contact with an end portion of the memory pillar (the multi-layered catalyst layer 121a is in electrical contact with the upper ends of the memory pillars MP) and a second portion (an upper layer of the multi-layered catalyst layer 121a) that is arranged on a first surface of the first portion on a side of the first conductive layer in the first direction and protrudes with respect to the first portion (as the top surface is not coplanar with the lower surface, the top surface of the multi-layered catalyst layer 121a protrudes with respect to the bottom surface) (Fig. 2 and paragraphs 60 and 89), and the first conductive layer includes a third portion in contact with the second portion in the first region (a portion of the conductive layer 121b is in electrical contact with the multi-layered catalyst layer 121a to the far left of the cell array as shown in Fig. 2) and a fourth portion (the semiconductor layer 101) in contact with an end portion of the first conductor in the second region (the plurality of interconnect layers 104 electrically connect the plurality of source lines SL formed of 121a and 121b and a contact plug 107 in the peripheral region, therefore the semiconductor layers 101 and 102 would also electrically contact the contact plug 107) (Fig. 2 and paragraphs 62).
In regard to claim 2, Yoshimizu teaches wherein the first conductive layer further includes a fifth portion in the first region (the semiconductor layer 102 functions as a fifth portion in the first region) (Fig. 2 and paragraph 61), the fifth portion being positioned on a side opposite the second conductive layer in the first direction with respect to the third portion (the semiconductor layer 102 would be placed opposite to a portion of the conductive layer 121b is in electrical contact with the multi-layered catalyst layer 121a to the far left of the cell array as shown in Fig. 2).
In regard to claim 3, Yoshimizu teaches wherein the fourth portion is positioned on a side of the first portion of the second conductive layer in the first direction with respect to the third portion (the semiconductor layer 101 is on the side of the bottom layer of the multi-layered catalyst layer 121a in the Z1 direction as shown in Fig. 2).
In regard to claim 4, Yoshimizu teaches wherein the second portion is arranged at a position that overlaps the memory pillar when viewed in the first direction (the bottom layer of the multi-layered catalyst layer 121a is shown over the memory pillars MP in Fig. 2).
In regard to claim 5, Yoshimizu teaches wherein a region of the second portion viewed in the first direction includes a region of the third portion viewed in the first direction (121a and 121b form the source line SL and would be include each other when viewed in the Z direction) (Fig. 2 and paragraph 88).
In regard to claim 6, Yoshimizu teaches wherein the end portion of the first conductor is positioned on a side of the third conductive layers in the first direction with respect to an extension of the first surface (the contact plug 107 is shown on the interconnect layers 104 in the Z direction in Fig. 2).
In regard to claim 8, Yoshimizu teaches a second conductor (contact plug 112) extending in the first direction and intersecting the extensions of the third conductive layers (the contact plug 112 is shown extending in the Z direction intersecting the Y direction) (Fig. 2 and paragraph 57); and
a fourth conductive layer (an electrode pads PD) arranged at a same level as the first conductive layer and separated from the first conductive layer (the electrode pad PD is shown in the same layer and separated from the conductive layer 121b in Fig. 2) (Fig. 2 and paragraph 63),
wherein the fourth conductive layer includes a seventh portion (the bottom surface of the electrode pads PD) in contact with an end portion of the second conductor and an eighth portion (a top surface of the electrode pads PD) arranged on a side opposite the second conductor in the first direction with respect to the seventh portion (the top and bottom surface of the electrode pads PD are arranged opposite to one another) (Fig. 2).
In regard to claim 17, Yoshimizu teaches wherein the first portion of the second conductive layer has the same material and film properties as the second portion of the second conductive layer (the layers the catalyst layer 121a may be the same material or different as described in Yoshimizu) (paragraph 89).
In regard to claim 18, Yoshimizu teaches wherein the first portion of the second conductive layer has different material or film properties from the second portion of the second conductive layer (the layers 121a and 121b may be the same material or different as described in Yoshimizu) (paragraph 89).
In regard to claim 20, Yoshimizu teaches a first electrode (a switching element SW) arranged on a side opposite the second conductive layer in the first direction with respect to the third conductive layers (the a switching element SW is shown on the opposite side of the catalyst layer 121a in Fig. 2) (Fig. 2 and paragraph 43); and a second electrode (contact plugs 206) in contact with the first electrode (Fig. 2 and paragraph 70), wherein a first chip (an array chip 100) including the first conductive layer, the second conductive layer, the third conductive layers, the first conductor, the memory pillar, and the first electrode is bonded to a second chip (a circuit chip 200) including the second electrode (Fig. 2 and paragraph 69), and the memory pillar is positioned between the second conductive layer and the first electrode (the memory pillar MP is shown between a conductive layer 121b and the contact plug 206 in Fig. 2).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
As best understood, claims 10 and 16 are rejected under 35 U.S.C. 103 as being unpatentable over Yoshimizu as applied to claims 1 and 8 above, in view of Yun et al. (US 2016/0225714 A1; hereinafter “Yun”).
In regard to claim 10, Yoshimizu doesn’t explicitly teach wherein the second conductor surrounds, when viewed in the first direction, the first conductive layer, the second conductive layer, the third conductive layers, and the memory pillar.
Yun teaches a memory device (a semiconductor device) (Fig. 3A and paragraph 63), wherein a second conductor (a cell guard contact structure 80c) surrounds (Fig. 2 and paragraph 97), when viewed in the first direction, a first conductive layer (a cell pad pattern 30) (Fig. 3A and paragraph 92), a second conductive layer (a bit line contact structures 86) (Fig. 3A and paragraph 107), a third conductive layers (a bit line interconnection structures 88) (Fig. 3A and paragraph 108), and a memory pillar (a first cell dielectric 27, a channel semiconductor pattern 28, a core insulating pattern 29 form the memory pillar) (Fig. 2, Fig. 3A and paragraph 92).
It would have been obvious to one skilled in the art to combine the teachings of Yoshimizu with the teachings of Yun to have the second conductor surrounds, when viewed in the first direction, the first conductive layer, the second conductive layer, the third conductive layers, and the memory pillar since this allows for a device with increased functionality as the surrounding regions allow for increased surface areas for connections and increased regions for dopants to be used as taught by Yun (paragraphs 9 and 73).
In regard to claim 16, Yoshimizu doesn’t explicitly teach wherein the first portion of the second conductive layer includes a semiconductor.
Yun teaches wherein a first portion (the top portion of a cell pad pattern 30) of a second conductive layer (the second conductive layer is comprised of the top portion of the cell pad 30 and the bit line contact structures 86) includes a semiconductor (the cell pad pattern 30 may be formed of polysilicon and have an N-type conductivity type) (Fig. 3A and paragraphs 92 and 107).
It would’ve been obvious to one skilled in the art to combine the teachings of Yoshimizu with the teachings of Yun to have the first portion of the second conductive layer include a semiconductor since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/SEYON ALI-SIMAH PUNCHBEDDELL/Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
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