Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 1-2, 4-6, 10-11, 13-14, 16, 20, 24-26, 28, 32, 34, 36-37, and 39-42 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Kanamori (US 20190164990 A1) hereinafter referred to as "Kanamori".
Regarding claim 1, Kanamori discloses a semiconductor memory device (figs. 1-3; para. [0018]-[0019]) comprising: a doped semiconductor structure including a first surface and a second surface facing opposite to each other (fig. 2, element 100; para. [0022]-[0023]); a gate stack structure formed over the first surface of the doped semiconductor structure, the gate stack structure including a plurality of conductive layers stacked spaced apart from each other in a direction intersecting the first surface (fig. 2, element 332, 334, 336; para. [0024]); a channel layer including a first portion overlapping with a sidewall of the gate stack structure, a second portion extending to the inside of the doped semiconductor structure from the first portion, and a third portion extending toward the second surface of the doped semiconductor structure from the second portion (fig. 2, element 215; para. [0036]); and a memory layer disposed between the first portion of the channel layer and the sidewall of the gate stack structure (fig. 2, element 195; para. [0036]), wherein the second portion of the channel layer includes a first corner adjacent to the gate stack structure and a second corner between the second surface of the doped semiconductor structure and the first corner (fig. 2, element 215; para. [0037], [0045]).
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Regarding claim 2, Kanamori discloses each of the first and second portions of the channel layer including a ring-shaped cross-sectional structure, and the third portion of the channel layer including a circular cross-sectional structure (fig. 15, element 215; para. [0092]).
Regarding claim 4, Kanamori discloses the plurality of conductive layers including a lowermost conductive layer adjacent to the doped semiconductor structure (fig. 2 element 332; para. [0024], [0027]), wherein the first portion in the channel layer has a first external diameter (fig. 2, element W2) at a level at which the lowermost conductive layer is disposed, the second portion in the channel layer has a second external diameter (fig. 2, element W1), and the third portion in the channel layer has a third external diameter (fig. 2, element W3), and wherein the second external diameter is greater than each of the first external diameter and the third external diameter (fig. 2, elements W2, W1, W3; para. [0045]).
Regarding claim 5, Kanamori discloses a core insulating layer extending along the first portion and the second portion of the channel layer, wherein the third portion of the channel layer extends to cover an end portion of the core insulating layer facing the first surface of the doped semiconductor structure (fig. 2, element 220; para. [0036] - [0038]).
Regarding claim 6, Kanamori discloses the memory layer covering the first corner of the second portion in the channel layer and extending between the doped semiconductor structure and the second portion of the channel layer (fig.2, element 195; para. [0036], [0042]).
Regarding claim 10, Kanamori discloses the memory layer covering the first and second corners of the second portion in the channel layer and extending between the third portion of the channel layer and the first semiconductor layer (fig.2, element 195; para. [0036]).
Regarding claim 11, Kanamori discloses a semiconductor memory device (figs. 1-3; para. [0018]- [0019]) comprising: a doped semiconductor structure including a first surface and a second surface facing in a direction opposite to a direction in which the first surface faces (fig. 2, element 100; para. [0022] - [0023]); a gate stack structure overlapping with the first surface of the doped semiconductor structure, the gate stack structure including a plurality of conductive layers stacked spaced apart from each other in a direction intersecting the first surface (fig. 2, element 332, 334, 336; para. [0024]); a channel hole passing through the gate stack structure to extend to the inside of the doped semiconductor structure (fig. 8, element 140; para. [0075], [0076]); a channel structure disposed in the channel hole, the channel structure including a channel layer (fig. 2, element 215; para. [0036]); and a memory layer between the channel layer and the gate stack structure (fig. 2, element 195; para. [0036]), wherein the channel hole includes an end portion inside the doped semiconductor structure, a gate penetration portion passing through the gate stack structure, and a middle portion disposed inside the doped semiconductor structure between the end portion and the gate penetration portion (fig. 11, element 142; para. [0083]), and wherein the middle portion in the channel hole includes a first corner adjacent to the gate stack structure and a second corner between the second surface of the doped semiconductor structure and the first corner (para. [0037], [0045]).
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Regarding claim 13, Kanamori discloses the channel structure further including a core insulating layer extending to the inside of the middle portion from the inside of the gate penetration portion in the channel hole (fig. 2, element 220; para. [0036]- [0037]).
Regarding claim 14, Kanamori discloses the channel layer including: a ring-shaped first portion disposed inside the gate penetration portion in the channel hole, the ring-shaped first portion surrounding a sidewall of the core insulating layer; a ring-shaped second portion disposed inside the middle portion in the channel hole, the ring- shaped second portion surrounding a sidewall of the core insulating layer; and a third portion disposed inside the end portion in the channel hole, the third portion overlapping with the core insulating layer (fig. 15, element 215; para. [0092]).
Regarding claim 16, Kanamori discloses the channel layer extending to the inside of the end portion from the inside of the gate penetration portion, and wherein the memory layer covers the first corner of the channel hole and extends between the channel layer and the doped semiconductor structure (fig.2, element 195; para. [0036]).
Regarding claim 20, Kanamori discloses a semiconductor memory device (figs. 1-3; para. [0018]- [0019]) comprising: a gate stack structure including a plurality of conductive layers (fig. 21, element 332, 334, 336) and a plurality of interlayer insulating layers (fig. 21, element 115), which are alternately disposed in a stacking direction (fig. 21, element 332, 334, 336, 115; para. [0024], [0032]), wherein the plurality of conductive layers includes a first conductive layer (fig. 21, element 332), a second conductive layer (fig. 21, element 334), and a third conductive layer (fig. 21, element 336), which are disposed spaced apart from each other in the stacking direction (fig. 21, element 332, 334, 336; para. [0024]); a channel hole passing through the gate stack structure, the channel hole including a first portion passing through the second conductive layer, a second portion extending to pass through the first conductive layer from the first portion, and a third portion extending to pass through the third conductive layer from the first portion (fig. 21, element 215; para. [0075], [0076]); a channel layer including a filling channel portion inside the second portion of the channel hole, a first liner channel portion inside the first portion of the channel hole, and a second liner channel portion inside the third portion of the channel hole (fig. 21, element 215; para. [0036]); and a memory layer between the channel layer and the gate stack structure (fig. 21, element 195; para. [0036]), wherein the first portion of the channel hole protrudes laterally toward the gate stack structure as compared with the second portion of the channel hole and the third portion of the channel hole (para. [0037], [0045]).
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Regarding claim 24, Kanamori discloses the filling channel portion extending toward an inner wall of the memory layer from a central axis extending along a center of the channel hole in the stacking direction (fig. 21; para. [0005], [0006]).
Regarding claim 25, Kanamori discloses the first liner channel portion and the second liner channel portion being spaced apart from a central axis extending along a center of the channel hole in the stacking direction (fig. 21; para. [0005], [0006]).
Regarding claim 26, Kanamori discloses the filling channel portion including a circular cross-sectional structure, and wherein the first liner channel portion and the second liner channel portion include a ring- shaped cross-sectional structure (fig. 15, element 215; para. [0092]).
Regarding claim 28, Kanamori discloses a core insulating layer extending to the inside of the third portion of the channel hole from the inside of the first portion of the channel hole, the core insulating layer overlapping with the filling channel portion in the stacking direction (fig. 21, element 220; para. [0036]- [0037]), wherein the first liner channel portion and the second liner channel portion are interposed between the core insulating layer and the memory layer (fig. 21, elements 195, 215, 220; para. [0090]).
Regarding claim 32, Kanamori discloses a semiconductor memory device (figs. 1-3; para. [0018]-[0019]) comprising: a gate stack structure including a plurality of conductive layers (fig. 21, element 332, 334) and a plurality of interlayer insulating layers (fig. 21, element 115), which are alternately disposed in a stacking direction, wherein the plurality of conductive layers include a first conductive layer (fig. 21, element 332) and a second conductive layer (fig. 21, element 334), which are disposed spaced apart from each other in the stacking direction, and the plurality of interlayer insulating layers include a pad interlayer insulating layer between the first conductive layer and the second conductive layer (fig. 21, element 332, 334; para. [0024], [0032]); a channel hole passing through the gate stack structure, the channel hole including a first portion inside the pad interlayer insulating layer, a second portion extending to pass through the first conductive layer from the first portion, and a third portion extending to pass through the second conductive layer from the first portion (fig. 21, element 215; para. [0075], [0076]); a filling channel pattern inside the second portion of the channel hole (fig. 21, element 215; para. [0036]- [0037]); a liner channel pattern including a connection portion inside the first portion of the channel hole and a vertical portion extending to the inside of the third portion of the channel hole from the connection portion (fig. 21, element 215; para. [0036]- [0037]); a gate insulating layer between the filling channel pattern and the first conductive layer (fig. 21, element 312; para. [0030]); and a memory layer between the liner channel pattern and the gate stack structure (fig. 2, element 195; para. [0036], [0042], [0045]), wherein the first portion of the channel hole protrudes laterally toward the gate stack structure as compared with the second portion of the channel hole and the third portion of the channel hole (para. [0037], [0045]).
Regarding claim 34, Kanamori discloses the filling channel pattern extending toward a sidewall of the second portion of the channel hole from a central axis extending along a center of the channel hole in the stacking direction (fig. 21, element 195; para. [0036]- [0037]).
Regarding claim 36, Kanamori discloses the gate insulating layer being cut by an interlayer insulating layer adjacent to the first conductive layer among the plurality of interlayer insulating layers (fig. 21, element 312; para. [0030]).
Regarding claim 37, Kanamori discloses the filling channel pattern including a circular cross-sectional structure, and the liner channel pattern including a ring-shaped cross-sectional structure (fig. 15, element 215; para. [0092]).
Regarding claim 39, Kanamori discloses a core insulating layer extending to the inside of the third portion of the channel hole from the inside of the first portion of the channel hole, the core insulating layer overlapping with the filling channel pattern in the stacking direction (fig. 21, element 220; para. [0036]- [0037]), wherein the connection portion and the vertical portion of the liner channel pattern are interposed between the core insulating layer and the memory layer (fig. 2, elements 195, 215, 220; para. [0090]).
Regarding claim 40, Kanamori discloses a core insulating layer extending to the inside of the third portion of the channel hole from the inside of the first portion of the channel hole, the core insulating layer overlapping with the filling channel pattern in the stacking direction, wherein the connection portion of the liner channel pattern extends between the core insulating layer and the filling channel pattern (fig. 21, elements 195, 215, 220; para. [0090]).
Regarding claim 41, Kanamori discloses a doped semiconductor structure overlapping with the gate stack structure, wherein the doped semiconductor structure contacts the filling channel pattern (fig. 21, element 102; para. [0035], [0036]).
Regarding claim 42, Kanamori discloses the first portion of the channel hole and the filling channel pattern extending to the inside of the doped semiconductor structure (fig. 21, elements 102, 215; claim 3).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claims 3, 15, 27, and 38 are rejected under 35 U.S.C. 103 as being unpatentable over Kanamori in view of Ninomiya (US 20220189986 A1) hereinafter referred to as "Ninomiya".
Regarding claim 3, Kanamori teaches the semiconductor device of claim 1 but does not teach each of the first and second portions of the channel layer including a crescent-moon-shaped cross-sectional structure, and the third portion of the channel layer includes an elliptical cross-sectional structure. Ninomiya teaches each of the first and second portions of the channel layer including a crescent-moon-shaped cross-sectional structure, and the third portion of the channel layer includes an elliptical cross-sectional structure (fig. 5B, element 60, 49; para. [0194]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do this so as to have two vertical semiconductor channels laterally spaced from each other (Ninomiya, para. [0159]).
Regarding claim 15, Kanamori teaches the semiconductor device of claim 13 but does not teach the channel layer including: a first pattern extending along a first sidewall of the core insulating layer; a second pattern extending along a second sidewall of the core insulating layer, the second pattern being spaced apart from the first pattern with the core insulating layer interposed therebetween; and a connection portion disposed inside the end portion in the channel hole, the connection portion connecting the first pattern and the second pattern to each other. Ninomiya teaches the channel layer including: a first pattern extending along a first sidewall of the core insulating layer; a second pattern extending along a second sidewall of the core insulating layer, the second pattern being spaced apart from the first pattern with the core insulating layer interposed therebetween; and a connection portion disposed inside the end portion in the channel hole, the connection portion connecting the first pattern and the second pattern to each other (fig. 5B, element 60, 49; para. [0194]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do this so as to have two vertical semiconductor channels laterally spaced from each other (Ninomiya, para. [0159]).
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Regarding claim 27, Kanamori teaches the semiconductor device of claim 20 but does not teach the filling channel portion including an elliptical cross-sectional structure, and wherein the first liner channel portion and the second liner channel portion include a crescent- moon-shaped cross-sectional structure having a width which becomes narrower as approaching an end portion thereof. Ninomiya teaches the filling channel portion including an elliptical cross-sectional structure, and wherein the first liner channel portion and the second liner channel portion include a crescent- moon-shaped cross-sectional structure having a width which becomes narrower as approaching an end portion thereof (fig. 5B, element 60, 49; para. [0194]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do this so as to have two vertical semiconductor channels laterally spaced from each other (Ninomiya, para. [0159]).
Regarding claim 38, Kanamori teaches the semiconductor device of claim 32 but does not teach the filling channel pattern including an elliptical cross-sectional structure, and wherein the liner channel pattern includes a crescent-moon-shaped cross-sectional structure having a width which becomes narrower as approaching an end portion thereof. Ninomiya teaches the filling channel pattern including an elliptical cross-sectional structure, and wherein the liner channel pattern includes a crescent-moon-shaped cross-sectional structure having a width which becomes narrower as approaching an end portion thereof (fig. 5B, element 60, 49; para. [0194]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to do this so as to have two vertical semiconductor channels laterally spaced from each other (Ninomiya, para. [0159]).
Claims 7-9, 17-19, and 29-31 are rejected under 35 U.S.C. 103 as being unpatentable over Kanamori in view of Choi et al. (US 20180366488 A1) hereinafter referred to as "Choi".
Regarding claim 7, Kanamori teaches the semiconductor device of claim. However, Kanamori does not teach a first semiconductor layer constituting the second surface, the first semiconductor layer including a groove into which an end of the third portion in the channel layer is inserted; a second semiconductor layer constituting the first surface, the second semiconductor layer surrounding a sidewall of the second portion in the channel layer; and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer contacting a sidewall of the third portion in the channel layer. Choi teaches a first semiconductor layer constituting the second surface, the first semiconductor layer including a groove into which an end of the third portion in the channel layer is inserted (fig. 1, element 113; para. [0021], [0024]); a second semiconductor layer constituting the first surface, the second semiconductor layer surrounding a sidewall of the second portion in the channel layer (fig. 1, element 131; para. [0021], [0025]); and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer, the third semiconductor layer contacting a sidewall of the third portion in the channel layer (fig. 1, element 181; para. [0021], [0026], [0036]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include these semiconductor layers in order to provide holes to a channel area during an erase operation of the semiconductor device (Choi, para. [0022]).
Regarding claim 8, Kanamori does not teach an interposition layer disposed between the first semiconductor layer and the third portion of the channel layer, wherein the interposition layer includes the same material layers as the memory layer. Choi teaches an interposition layer disposed between the first semiconductor layer and the third portion of the channel layer, wherein the interposition layer includes the same material layers as the memory layer (fig. 1, element ML2; para. [0038]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include this interposition layer to insulate the first semiconductor layer and the channel pillar from each other (Choi, para. [0042]).
Regarding claim 9, Kanamori teaches the semiconductor device of claim 1. However, Kanamori does not teach a first semiconductor layer surrounding a sidewall of the third portion in the channel layer; a second semiconductor layer disposed between the first semiconductor layer and the gate stack structure, the second semiconductor layer constituting the first surface, the second semiconductor layer surrounding a sidewall of the second portion in the channel layer; and a third semiconductor layer constituting the second surface, the third semiconductor layer including a groove into which an end of the third portion in the channel layer is inserted, the second semiconductor layer contacting the end. Choi teaches a first semiconductor layer surrounding a sidewall of the third portion in the channel layer (fig. 1, element 181; para. [0021], [0026], [0036]); a second semiconductor layer disposed between the first semiconductor layer and the gate stack structure, the second semiconductor layer constituting the first surface, the second semiconductor layer surrounding a sidewall of the second portion in the channel layer (fig. 1, element 131; para. [0021], [0025]); and a third semiconductor layer constituting the second surface, the third semiconductor layer including a groove into which an end of the third portion in the channel layer is inserted, the second semiconductor layer contacting the end (fig. 1, element 113; para. [0021], [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include these semiconductor layers in order to provide holes to a channel area during an erase operation of the semiconductor device (Choi, para. [0022]).
Regarding claim 17, Kanamori teaches the semiconductor device of claim 11. However, Kanamori does not teach the doped semiconductor structure including: a first semiconductor layer including a groove constituting the end portion of the channel hole, the first semiconductor layer constituting the second surface; a second semiconductor layer constituting the first surface, the second semiconductor layer with the middle portion of the channel hole; and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer, and wherein the channel layer includes an end inserted into the groove of the first semiconductor layer and includes a sidewall contacting the third semiconductor layer. Choi teaches the doped semiconductor structure including: a first semiconductor layer including a groove constituting the end portion of the channel hole, the first semiconductor layer constituting the second surface (fig. 1, element 113; para. [0021], [0024]); a second semiconductor layer constituting the first surface, the second semiconductor layer with the middle portion of the channel hole (fig. 1, element 131; para. [0021], [0025]); and a third semiconductor layer disposed between the first semiconductor layer and the second semiconductor layer, and wherein the channel layer includes an end inserted into the groove of the first semiconductor layer and includes a sidewall contacting the third semiconductor layer (fig. 1, element 181; para. [0021], [0026]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include these semiconductor layers in order to provide holes to a channel area during an erase operation of the semiconductor device (Choi, para. [0022]).
Regarding claim 18, Kanamori does not teach an interposition layer between the first semiconductor layer and the end of the channel layer, wherein the interposition layer includes the same material layers as the memory layer. Choi teaches an interposition layer between the first semiconductor layer and the end of the channel layer, wherein the interposition layer includes the same material layers as the memory layer (fig. 1, element ML2; para. [0038]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include this interposition layer to insulate the first semiconductor layer and the channel pillar from each other (Choi, para. [0042]).
Regarding claim 19, Kanamori teaches the semiconductor device of claim 11. However, Kanamori does not teach the doped semiconductor structure including: a first semiconductor layer with the end portion of the channel hole; a second semiconductor layer disposed between the first semiconductor layer and the gate stack structure, the second semiconductor layer with the middle portion of the channel hole, the second semiconductor layer constituting the first surface; and a third semiconductor layer constituting the second surface, wherein the third semiconductor layer includes a groove overlapping with the end portion of the channel hole, and wherein the channel layer includes an end inserted into the groove, the end contacting the third semiconductor layer. Choi teaches the doped semiconductor structure including: a first semiconductor layer with the end portion of the channel hole (fig. 1, element 181; para. [0021], [0026], [0036]); a second semiconductor layer disposed between the first semiconductor layer and the gate stack structure, the second semiconductor layer with the middle portion of the channel hole, the second semiconductor layer constituting the first surface (fig. 1, element 131; para. [0021], [0025]); and a third semiconductor layer constituting the second surface, wherein the third semiconductor layer includes a groove overlapping with the end portion of the channel hole, and wherein the channel layer includes an end inserted into the groove, the end contacting the third semiconductor layer (fig. 1, element 113; para. [0021], [0024]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include these semiconductor layers in order to provide holes to a channel area during an erase operation of the semiconductor device (Choi, para. [0022]).
Regarding claim 29, Kanamori teaches the semiconductor device of claim 20. However, Kanamori does not teach a doped semiconductor structure overlapping with the gate stack structure, wherein the doped semiconductor structure includes: a first semiconductor layer including a groove; a second semiconductor layer between the first semiconductor layer and the gate stack structure; and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer, wherein the filling channel portion is inserted into the groove of the first semiconductor layer while passing through the second semiconductor layer and the third semiconductor layer, and wherein the third semiconductor layer contacts a sidewall of the filling channel portion. Choi teaches a doped semiconductor structure overlapping with the gate stack structure, wherein the doped semiconductor structure includes: a first semiconductor layer including a groove (fig. 1, element 113; para. [0021], [0024]); a second semiconductor layer between the first semiconductor layer and the gate stack structure (fig. 1, element 131; para. [0021], [0025]); and a third semiconductor layer between the first semiconductor layer and the second semiconductor layer (fig. 1, element 181; para. [0021], [0026]), wherein the filling channel portion is inserted into the groove of the first semiconductor layer while passing through the second semiconductor layer and the third semiconductor layer, and wherein the third semiconductor layer contacts a sidewall of the filling channel portion (para. [0036]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include these semiconductor layers in order to provide holes to a channel area during an erase operation of the semiconductor device (Choi, para. [0022]).
Regarding claim 30, Kanamori teaches the semiconductor device of claim 20. However, Kanamori does not teach a doped semiconductor structure overlapping with the gate stack structure, wherein an end of the filling channel portion contacts the doped semiconductor structure. Choi teaches a doped semiconductor structure overlapping with the gate stack structure, wherein an end of the filling channel portion contacts the doped semiconductor structure (para. [0025], [0036]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the filling channel contact the doped semiconductor structure so that the core insulating layer may directly contact the channel pillar (Choi, para. [037]).
Regarding claim 31, Kanamori does not teach an interposition semiconductor layer between the doped semiconductor structure and the gate stack structure, wherein the filling channel layer and the memory layer extend to pass through the interposition semiconductor layer. Choi teaches an interposition semiconductor layer between the doped semiconductor structure and the gate stack structure, wherein the filling channel layer and the memory layer extend to pass through the interposition semiconductor layer (fig. 1, element ML2; para. [0038]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to include this interposition layer to insulate the first semiconductor layer and the channel pillar from each other (Choi, para. [0042]).
Claim 12 is rejected under 35 U.S.C. 103 as being unpatentable over Kanamori in view of Mitsuno et al. (US 20210028189 A1) hereinafter referred to as "Mitsuno".
Regarding claim 12, Kanamori teaches the semiconductor device of claim 11 but does not teach the middle portion in the channel hole extending to overlap with the gate stack structure and defining a convex portion at a sidewall of the channel hole. Mitsuno teaches the middle portion in the channel hole extending to overlap with the gate stack structure and defining a convex portion at a sidewall of the channel hole (fig. 10, element CN; para. [0092], [0094]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the channel structure be convex in order to more easily etch the sacrificial material rather than etch the sacrificial material formed at positions other than at the convex portion (Mitsuno, para. [0094]).
Claims 21-23 are rejected under 35 U.S.C. 103 as being unpatentable over Kanamori in view of Hosoda et al. (US 20220181283 A1) hereinafter referred to as "Hosoda".
Regarding claim 21, Kanamori teaches the semiconductor device of claim 20. However, Kanamori does not teach a select line isolation structure passing through the first conductive layer such that the first conductive layer is isolated into a select line of a first group and a select line of a second group. Hosoda teaches a select line isolation structure passing through the first conductive layer such that the first conductive layer is isolated into a select line of a first group and a select line of a second group (fig. 18, element 71; para. [0140]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to insert a line isolation structure into the claimed device so that the then modified conductive layers could comprise of source side select gate electrodes and world lines located between the drain side select gate electrode layers and the source side select gate electrodes (Hosoda, para. [0140]).
Regarding claim 22, Kanamori does not teach the select line isolation structure being formed in a first tapered shape which becomes thinner as a distance from the second conductive layer increases, and wherein the filling channel portion is formed in a second tapered shape which becomes thinner in a direction identical to the direction in which the first tapered shape of the select line isolation structure becomes thinner. Hosoda teaches the select line isolation structure being formed in a first tapered shape which becomes thinner as a distance from the second conductive layer increases, and wherein the filling channel portion is formed in a second tapered shape which becomes thinner in a direction identical to the direction in which the first tapered shape of the select line isolation structure becomes thinner (fig. 39, element 173; para. [0175]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to insert a line isolation structure into the claimed device so that the then modified conductive layers could comprise of source side select gate electrodes and world lines located between the drain side select gate electrode layers and the source side select gate electrodes (Hosoda, para. [0140]).
Regarding claim 23, Kanamori does not teach the select line isolation structure being formed in a first tapered shape which becomes thinner in a direction in which a distance to the second conductive layer decreases, and wherein the filling channel portion is formed in a second tapered shape which becomes thinner in a direction opposite to the direction in which the first tapered shape of the select line isolation structure becomes thinner. Hosoda teaches the select line isolation structure being formed in a first tapered shape which becomes thinner in a direction in which a distance to the second conductive layer decreases, and wherein the filling channel portion is formed in a second tapered shape which becomes thinner in a direction opposite to the direction in which the first tapered shape of the select line isolation structure becomes thinner (fig. 18, element 71; para. [0140]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to insert a line isolation structure into the claimed device in such a manner so that the drain select-level isolation trenches do not cut into the memory opening fill structures (Hosoda, para. [0141]).
Claim 35 is rejected under 35 U.S.C. 103 as being unpatentable over Kanamori in view of Lee (US 20210210426 A1) hereinafter referred to as "Lee".
Regarding claim 35, Kanamori teaches the semiconductor device of claim 32. However, Kanamori does not teach the connection portion of the liner channel pattern forming a contact surface with the filling channel pattern, and wherein the gate insulating layer overlaps with the contact surface. Lee teaches the connection portion of the liner channel pattern forming a contact surface with the filling channel pattern, and wherein the gate insulating layer overlaps with the contact surface (fig. 3A, elements CH, DS; para. [0036], [0037]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the liner channel to form a contact surface in order for the channel structure to come into contact with the doped semiconductor (Lee, para. [0036])
Allowable Subject Matter
The following is a statement of reasons for the indication of allowable subject matter:
Kanamori is cited as teaching some elements of the claimed invention. However, t
Conclusion
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/I.H./ Examiner, Art Unit 2899 04/03/2026
/ZANDRA V SMITH/ Supervisory Patent Examiner, Art Unit 2899
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