Prosecution Insights
Last updated: May 29, 2026
Application No. 18/538,792

HETEROGENEOUS TERMINATION STRUCTURES FOR SEMICONDUCTOR DEVICES

Non-Final OA §102§103
Filed
Dec 13, 2023
Examiner
HAWKINS, IHSAN TAIWO
Art Unit
2899
Tech Center
2800 — Semiconductors & Electrical Systems
Assignee
VIRGINIA TECH INTELLECTUAL PROPERTIES, INC.
OA Round
1 (Non-Final)
Grant Probability
Favorable
1-2
OA Rounds

Examiner Intelligence

Grants only 0% of cases
0%
Career Allowance Rate
0 granted / 0 resolved
-68.0% vs TC avg
Minimal +0% lift
Without
With
+0.0%
Interview Lift
resolved cases with interview
Typical timeline
Avg Prosecution
2 currently pending
Career history
2
Total Applications
across all art units

Statute-Specific Performance

§103
100.0%
+60.0% vs TC avg
Black line = Tech Center average estimate • Based on career data from 0 resolved cases

Office Action

§102 §103
DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA . Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims 1-3, 16-18 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Bakowsky et al. (US 5967795 A) hereinafter referred to as "Bakowsky". Regarding claim 1, Bakowsky discloses a device comprising: a first semiconductor region of a first conductivity type, the first conductivity type being one of a p-type conductivity and a n-type conductivity, the first semiconductor region having a top surface and being formed of a first material (Column 5, line 54-61; Fig 2a: [2]), a second semiconductor region of a second conductivity type and being formed of a second material different from the first material (Column 6, line 38-40)), the second conductivity type being different from the first conductivity type and being the other of the p-type conductivity and the n-type conductivity, the second semiconductor region positioned over the top surface of the first semiconductor region (Column 5, line 61-63; Fig 2a: [3]), a metal layer, at least a portion of which is disposed over the top surface of the first semiconductor region and at least a portion of which is disposed over the second semiconductor region, the metal layer forming a device terminal and having a terminal edge positioned over the second semiconductor region (Column 6, line 48-51; Fig. 2a: [7]), wherein a charge density of at least a portion of the second semiconductor region decreases with an increase in a lateral distance from the terminal edge of the metal layer (Column 6, line 3-5; Fig. 2a: [T]). Regarding claim 2, Bakowsky discloses the charge density of the second semiconductor region being defined as sheet charge density of an ionized dopant along a direction normal to the top surface of the first semiconductor region (Column 6, line 11-12; Column 2, line 52-54). Regarding claim 3, Bakowsky discloses an interface semiconductor region formed of the second material and having a doping concentration that is greater than that of the second semiconductor region positioned between the second semiconductor region and the metal layer (Column 5, line 63-65; Fig 2a: [4]). PNG media_image1.png 344 751 media_image1.png Greyscale Regarding claim 16, Bakowsky discloses a third semiconductor region positioned between the device terminal region and both the first semiconductor region and the second semiconductor region, the third semiconductor region having a second conductivity type, the third semiconductor region forming a p-n junction with the first semiconductor region, and the third semiconductor region being formed of the same material as the second semiconductor region (Column 8, line 66 – Column 9, line 12; Fig 5a: [17]). Regarding claim 17, Bakowsky discloses a concentration of ionized dopant in the second semiconductor region decreasing with an increase in the lateral distance from the terminal edge and wherein the second semiconductor region has a substantially vertical sidewall (Column 4, line 36=40). Regarding claim 18, Bakowsky discloses the second semiconductor region including a single layer and wherein charge density of the second semiconductor region decreases with an increase in distance from the terminal edge in a direction normal to the top surface of the first semiconductor region (Column 2, line 51-57; Fig. 2a: [T]). PNG media_image2.png 300 705 media_image2.png Greyscale Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention Claim 4 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky in view of Chen et al (US 20150014741 A1) hereinafter referred to as "Chen". Regarding claim 4, Bakowsky does not teach the second semiconductor region including a plurality of layers, wherein a lateral width of a first layer is less than a lateral width of a second layer that is nearer to the first semiconductor region, and the lateral width being measured as a lateral distance between the terminal edge of the metal layer and a lateral extent of the respective layer of the plurality of layers. Chen teaches the second semiconductor region including a plurality of layers (Chen, pa. [87]), wherein a lateral width of a first layer is less than a lateral width of a second layer that is nearer to the first semiconductor region (Chen, pa. [93]), and the lateral width being measured as a lateral distance between the terminal edge of the metal layer and a lateral extent of the respective layer of the plurality of layers (Chen, pa. [93]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the device such that the second semiconductor layer was split into a plurality of layers, where the lateral width increases with each layer closer to the first semiconductor region. Doing so would better distribute intense electric fields and thus, increase the maximum voltage resistance (Chen, pa. [0096]). Claim 5 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky and Chen in view of Chang et al. (US 20220029001 A1) hereinafter referred to as "Chang". Regarding claim 5, Bakowsky and Chen do not teach at least one layer of the plurality of layers having a sidewall with a substantially vertical edge. Chang teaches at least one layer of the plurality of layers having a sidewall with a substantially vertical edge (Chang pa. [0029]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try to make at least one of the plurality of layers with a vertical edge and achieve a predictable result. Claim 6-8 are rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky, Chen, and Chang in view of Tawara et al. (US 20220123112 A1) hereinafter referred to as "Tawara". Regarding claim 6, Bakowsky, Chen, and Chang do not teach at least two layers of the plurality of layers of the second semiconductor region having the same charge density. Tawara teaches at least two layers of the plurality of layers of the second semiconductor region having the same charge density (Tawara, pa. [0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try and make at least two of the plurality of layers have the same charge density and achieve a predictable result. Regarding claim 7, Bakowsky, Chen, Chang and Tawara teach the device claimed above. Chen further teaches a charge density of the first layer of the plurality of layers being greater than a charge density of the second layer of the plurality of layers positioned below the first layer (Chen, pa. [0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the charge density of the first layer be greater than the charge density of the second layer positioned below said first layer as doing so would suppress the application of high electric fields (Chen, pa. [0095]). Regarding claim 8, Bakowsky, Chen, Chang and Tawara teach the device claimed above. Chen further teaches a concentration of an ionized dopant in the first layer being greater than that in the second layer (Chen pa. [0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to decrease the concentration of ionized dopant in subsequent layers so that the depletion layer would not extend too far in longitudinal and lateral directions (Chen, pa. [0095]). Claim 9 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky, Chen, Chang, and Tawara in view of Yates et al. (US 20220165888 A1) hereinafter referred to as "Yates". Regarding claim 9, Bakowsky, Chen, Chang and Tawara teach the device of claim 7. However, they fail to teach a thickness of the first layer being greater than the thickness of the second layer. Yates teaches the thickness of the first layer being greater than the thickness of the second layer (Yates, pa. [0023]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the thickness of the first layer greater than the thickness of the second layer in order to reduce field crowding at the PN junction periphery and therefore reducing the peak electric field and avoiding premature avalanche breakdown under reverse bias (Yates pa. [0019]). Claim 10 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky and Chen in view of Dimitrijev et al. (US 20200091281 A1) hereinafter referred to as "Dimitrijev". Regarding claim 10, Bakowsky and Chen teach the device of claim 4 but fail to teach at least one of the plurality of layers having a sidewall with a substantially beveled edge. Dimitrijev teaches at least one of the plurality of layers having a sidewall with a substantially beveled edge (Dimitrijev, pa. [0023]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have at least one of the plurality of layers have a sidewall with a beveled edge as this would create a tapered charge density at the P-N junction (Dimitrijev, pa. [0023]). Claim 11-13 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky, Chen and Dimitrijev in view of Tawara (US 20220123112 A1). Regarding claim 11, Bakowsky, Chen, and Dimitrijev teach the device as claimed above. However, they do not teach at least two layers of the plurality of layers of the second semiconductor region having the same charge density. Tawara teaches at least two layers of the plurality of layers of the second semiconductor region having the same charge density (Tawara, pa. [0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to try and make at least two of the plurality of layers have the same charge density and achieve a predictable result. Regarding claim 12, Bakowsky, Chen, Dimitrijev, and Tawara teach the device of claim 10. Chen further teaches a charge density of the first layer of the plurality of layers being greater than a charge density of the second layer of the plurality of layers positioned below the first layer (Chen, pa. [0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the charge density of the first layer be greater than the charge density of the second layer positioned below said first layer as doing so would suppress the application of high electric fields (Chen, pa. [0095]). Regarding claim 13, Bakowsky, Chen, Dimitrijev, and Tawara teach the device claimed above. Chen further teaches a concentration of an ionized dopant in the first layer being greater than that in the second layer (Chen pa. [0091]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to decrease the concentration of ionized dopant in subsequent layers so that the depletion layer would not extend too far in longitudinal and lateral directions (Chen, pa. [0095]). Claim 14 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky, Chen, Dimitrijev, and Tawara in view of Yates (US 20220165888 A1). Regarding claim 14, Bakowsky, Chen, Dimitrijev, and Tawara fail to teach a thickness of the first layer being greater than the thickness of the second layer. Yates teaches the thickness of the first layer being greater than the thickness of the second layer (Yates, pa. [0023]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to make the thickness of the first layer greater than the thickness of the second layer in order to reduce field crowding at the PN junction periphery and therefore reducing the peak electric field and avoiding premature avalanche breakdown under reverse bias (Yates pa. [0019]). Claim 15 is rejected under 35 U.S.C. 103 as being unpatentable over Bakowsky in view of Dimitrijev (US 20200091281 A1). Regarding claim 15, Bakowsky fails to teach the device terminal region making a Schottky contact with the first semiconductor region. Dimitrijev teaches the device terminal region making a Schottky contact with the first semiconductor region (Dimitrijev, pa. [0047]). It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to implement a Schottky contact within the diode with the objective of create a diode with edge termination structures to reduce perimeter leakage (Dimitrijev, pa. [0015]). Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to IHSAN HAWKINS whose telephone number is (571)272-8594. The examiner can normally be reached Mon-Thu 7:00AM-5:00PM. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Zandra Smith can be reached at (571)272-2429. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /I.H./Examiner, Art Unit 2899 05/12/2026 /ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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Prosecution Timeline

Dec 13, 2023
Application Filed
May 19, 2026
Non-Final Rejection mailed — §102, §103 (current)

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Prosecution Projections

1-2
Expected OA Rounds
Grant Probability
Low
PTA Risk
Based on 0 resolved cases by this examiner. Grant probability derived from career allowance rate.

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