DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.
Information Disclosure Statement
The information disclosure statement (IDS) filed on April 20th, 2026, is being considered by the examiner.
Double Patenting
The double patenting rejection as previously issued has been withdrawn due to Applicant’s amendment dated July 6th, 2026.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL —The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 8-11 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Regarding Claim 8, it states the following limitation, “all portions of the beam are provided between the plurality of case beam portions in plan view” in lines 3-4 of said claim. However, said limitation is not sufficiently supported in the original disclosure. Applicant, on page 7 of their reply dated July 6th, 2026, states, “In addition, dependent claim 8 is amended based on, for example, Figures 15 and 16 and their corresponding description in the specification to recite that all portions of the beam are provided between the plurality of case beam portions in plan view”, and, therefore, would not introduce new features. However, upon review of Figures 15 and 16, the beam as previously introduced is divided into three separate beams, which is defined in the original specification ([0108]) as “The central beam 55 and the outer beams 55”. A broadest, reasonable interpretation of the claim as written would require that all three beams (i.e., the central beam and the outer beams) are provided between the plurality of case beam portions in plan view. Pursuant to the original disclosure, however, that is not supported, as the outer beams are not located between the plurality of case beam portions in plan view as shown in Figures 15 and 16.
Regarding Claims 9-11, said claims are rejected due to their dependence upon a previously rejected claim (i.e., Claim 8).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim(s) 1-5, 12, and 14 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura (US 20200211921 A1; hereinafter referred to as Kimura) and further in view of Sannai, et al. (US 20220278004 A1; hereinafter referred to as Sannai).
Regarding Claim 1, Kimura discloses a semiconductor device (“semiconductor module”, [002]) comprising:
a semiconductor element (semiconductor chips 5, insulating substrate 2, electrode 3 and solder 4, [0018]; the semiconductor chips, insulating substrate, electrode, and solder, as cited, together form the semiconductor element; these elements are hereinafter referred to together as semiconductor element) mounted on a base plate (base plate 1, [0018], Figs. 7-8);
a case (case 6, [0018]) that has a frame shape in plan view (Figs. 7-8), is attached to the base plate ([0018]), and houses the semiconductor element inside the frame shape (Figs. 7-8);
a beam that has a flat plate shape (plate member 17, [0030, 0031], Figs. 7-8; plate member 17 shall hereinafter be referred to as beam 17), is held by the case ([0030, 0031]), and is held over an internal space that is a space inside the frame shape of the case (Figs. 7-8); and
a sealing insulating material (sealing resin 9, [0018]; hereinafter, sealing resin 9 shall be referred to as sealing insulating material 9) that fills the internal space of the case (6, [0018]) and covers at least a part of the beam (17, [0030]), wherein
the beam (17) is provided above the semiconductor element and covers the semiconductor element in plan view (Figs. 7-8).
Kimura fails to disclose wherein the semiconductor device comprises a terminal that extends from a side of the case into the internal space and toward the base plate.
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Annotated Sannai Figure 2
However, in analogous art, Sannai discloses a terminal (Sannai: main terminals 12 and 14, [0042]) that extends from a side of the case into the internal space and toward the base plate (Sannai: see Annotated Sannai Fig. 2 above).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the terminals of Kimura such that they extend from a side of the case into the internal space and toward the base plate, as is disclosed by Sannai. One would be motivated to do so in order to improve thermal cycling tolerance of the semiconductor device (Sannai: [0005]).
Regarding Claim 2, Kimura/Sannai discloses a semiconductor device (Kimura: semiconductor module) according to claim 1, wherein the beam (Kimura: 17) is provided above a wiring (Kimura: wire 8, [0018]) passing through a space immediately above the semiconductor element, and covers the wiring in plan view (Kimura: Figs. 7-8).
Regarding Claim 3, Kimura/Sannai discloses a semiconductor device (Kimura: semiconductor module) according to claim 1, wherein the internal space includes an opening not covered by the beam (Kimura: 17) in plan view (Kimura: Fig. 7; Fig. 7 explicitly showcases two openings at either end of the beam within the internal space of a case).
Regarding Claim 4, Kimura/Sannai discloses a semiconductor device (Kimura: semiconductor module) according to claim 1, wherein
the beam (17) includes any one of a resin, glass, a ceramic material (Kimura: [0030]; “17 is an insulator”; resin, glass, and ceramic materials are known in the art to act as an insulator), and a metal and clad material covered with an insulator (Kimura: [0030]; “17 may be a conductor such as a metal material, in which case it is insulated from the [semiconductor element]”, a metal and clad material can act as either a conductor or insulator and is therefore taught by Kimura), and the beam (Kimura: 17) is formed of any one of a single material plate, a cracked plate, and a composite plate (Kimura: [0030]), and
a linear expansion coefficient of the beam (Kimura: 17) is smaller than a linear expansion coefficient of the sealing insulating material (Kimura: [0030]; “17 . . . has a linear expansion coefficient that is lower than the linear expansion coefficients of the [sealing insulating material] 9”).
Regarding Claim 5, Kimura/Sannai discloses a semiconductor device (Kimura: semiconductor module) according to claim 1, wherein the beam (Kimura: 17) is a component integrated with the case (Kimura: [0031]; by way of further explanation, under In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 34 (CCPA 1965), merely integrating an element into a structure, without providing any support in the disclosure as to the criticality of the integration, is not enough to overcome the patentability of the claimed invention. In the instant application, no support is provided as to why integrating the beam would be critical to the semiconductor device.)
Regarding Claim 12, Kimura/Sannai discloses a method of manufacturing a semiconductor device, the method comprising the steps of:
mounting a semiconductor element on a base plate (Kimura: [0018]);
attaching, to the base plate, a case that has a frame shape in plan view ([0018]) and is integrated with a beam (Kimura: [0031]; “the case 6 and the plate member 17 can be made of a single member”) that has a flat plate shape and is held over an internal space that is a space inside the frame shape of the case (Kimura: Fig. 8);
attaching, to the case, a terminal that extends from a side of the case into the internal space and toward the base plate (Sannai: main terminals 12 and 14, [0042], Annotated Sannai Fig. 2; see the motivation for obviousness combination in the rejection for Claim 1); and
filling the internal space with a sealing insulating material (Kimura: [0018]), wherein
in the step of attaching the case to the base plate, the case is attached to the base plate such that the semiconductor element is housed inside the frame shape and the beam is provided above the semiconductor element to cover the semiconductor element in plan view (Fig. 8), and
in the step of filling with the sealing insulating material, the filling is performed such that the sealing insulating material covers at least a part of the beam (Fig. 8).
Regarding Claim 14, Kimura/Sannai discloses the semiconductor device according to claim 1, wherein the semiconductor element is mounted on a substrate which is mounted on the base plate (Kimura: insulating substrate 2, [0018], Fig. 1).
Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura/Sannai as applied to claims 1-5, 12, and 14 above, and further in view of Tanimoto, et al. (JP 2015220238 A; hereinafter referred to as Tanimoto).
Regarding Claim 6, Kimura/Sannai discloses a semiconductor device (semiconductor module) according to claim 1.
Kimura/Sannai fails to disclose a recess portion on an inner side surface of a frame body constituting the frame shape and that the beam fits into the recess portion of the case.
However, Tanimoto discloses a semiconductor device (15, Fig. 8B) wherein the case (heat-resistant case 18) includes a recess portion on an inner side surface of a frame body constituting the frame shape (Fig. 8B), and
the beam (stress relaxation body 21; the beam as disclosed in the instant application is analogous to the stress relaxation body of as disclosed in Tanimoto as both serve the purpose of relieving the stress generated by the surrounding resin and/or gel) fits into the recess portion of the case (Fig. 8B).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the case of Kimura/Sannai such that there is a recess portion within the case for the beam to reside, as taught by Tanimoto. One would make this modification to further support the beam structure during its formation (Tanimoto [0088]).
Regarding Claim 13, Kimura/Sannai/Tanimoto discloses a method of manufacturing a semiconductor device, the method comprising the steps of:
mounting a semiconductor element on a base plate (Tanimoto: [0017]);
attaching, to the base plate, a case that has a frame shape in plan view (Tanimoto: [0015]) and includes a recess portion on an inner side surface of a frame body constituting the frame shape such that the semiconductor element is housed inside the frame shape (Tanimoto: [0088], Fig. 8B);
attaching, to the case, a beam that has a flat plate shape and is held over an internal space that is a space inside the frame shape of the case (Tanimoto: Fig. 8B);
attaching, to the case, a terminal that extends from a side of the case into the internal space and toward the base plate (Sannai: main terminals 12 and 14, [0042], Annotated Sannai Fig. 2; see the motivation for obviousness combination in the rejection for Claim 1); and
filling the internal space with a sealing insulating material (Tanimoto: [0022], Fig. 8B)), wherein
in the step of attaching the beam to the case, the beam is attached to the case such that the beam fits into the recess portion of the case and is provided above the semiconductor element to cover the semiconductor element in plan view (Tanimoto: [0080, 0083, 0086] Fig. 8B), and
in the step of filling with the sealing insulating material, the filling is performed such that the sealing insulating material covers at least a part of the beam (Tanimoto: Fig. 8B).
Claim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura/Sannai as applied to claims 1-5, 12, and 14 above, and further in view of Yasutomi, et al. (US 20170345729 A1; hereinafter referred to as Yasutomi).
Regarding Claim 7, Kimura/Sannai discloses a semiconductor device (Kimura: semiconductor module) according to claim 1.
Kimura/Sannai fails to disclose the semiconductor module wherein the beam has a protrusion on a lower surface of the flat plate shape.
However, Yasutomi discloses a semiconductor device (Yasutomi: semiconductor module, [0073]) wherein the beam (Yasutomi: expansion suppression plate 8, [0034]; the beam as taught in Kimura is analogous to the expansion suppression plate as taught in Yasutomi as both suppress the expansion/deformation of a sealant contained within a case (Yasutomi: [0034])) has a protrusion on a lower surface of the flat plate shape (Yasutomi: holes 2c, [0073], Fig. 12).
It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the beam of Kimura/Sannai such that protrusions exist on the lower surface of the beam. One would have been motivated to do so because Yasutomi teaches that the introduction of a protrusion (holes 2c) enables the prevention or reduction of both damage to the sealed object (the semiconductor device and the beam) and detachment of the sealing gel (sealing insulating material) (Yasutomi: [0076]).
Claim(s) 8-10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura/Sannai as applied to claims 1-5, 12, and 14 above, and further in view of Karasawa, et al. (JP 3237816 U; hereinafter referred to as Karasawa).
Regarding Claim 8, Kimura/Sannai discloses the semiconductor device of claim 1.
Kimura/Sannai fails to disclose a plurality of case beam portions provided on an upper side of the beam, wherein the beam is provided between the plurality of case beam portions in plan view.
However, in analogous art, Karasawa discloses a semiconductor device (Karasawa: semiconductor device 10), comprising a plurality of case beam portions (Karasawa: projections 13c1 and 13c2, [0021]) provided on an upper side of the beam (Karasawa: beam portion 3, [0022], Fig. 1), wherein
all portions of the beam are provided between the plurality of case beam portions in plan view (Karasawa: Figs. 1-5; said figures show the device in plan view wherein all portions of all beams are between the projections 13c1 and 13c2).
Therefore, It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the device as device as taught by Kimura/Sannai by implementing the case beam portions as taught by Karasawa. One would have been motivated to do so because, as Karasawa teaches, this structure design can prevent deformation caused by heat generation from the device (Karasawa: [0013]) and, thereby, increasing device performance.
Regarding Claim 9, Kimura/Sannai/Karasawa discloses a semiconductor device according to claim 8, further comprising a lid that covers the internal space (Karasawa: lid 13, [0018], Fig. 1), wherein
the plurality of case beam portions are provided on a lower surface of the lid (Karasawa: [0021], Fig. 1; “the lid 13 is provided with projections 13c1 and 13c2”).
Regarding Claim 10, Kimura/Sannai/Karasawa discloses a semiconductor device according to claim 8, wherein the plurality of case beam portions are components integrated with the case.
Pursuant to In re Larson, 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965), mere integration of elements is not patentably distinct. More specifically, “the use of a one piece construction instead of the structure disclosed in [the prior art] would be merely a matter of obvious engineering choice.” Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application with the teachings of Kimura/Sannai/Karasawa that the plurality of case beam portions are components integrated with the case, as the case beam portions are integrated with the lid as defined, and the lid being integrated with the case is merely a matter of obvious engineering choice.
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura/Sannai/Karasawa as applied to claims 8-10 above, and further in view of Kaji, et al. (US20210082778 A1; hereinafter referred to as Kaji).
Regarding Claim 11, Kimura/Sannai/Karasawa discloses a semiconductor device according to claim 8.
Kimura/Sannai/Karasawa fails to disclose wherein the beam includes a plurality of stepped portions, a thickness of each of the plurality of stepped portions is smaller than a thickness of the beam other than the plurality of stepped portions, and the beam is provided such that the plurality of stepped portions overlap the plurality of case beam portions in plan view.
However, in analogous art, Kaji does disclose a semiconductor device wherein,
the beam includes a plurality of stepped portions (Kaji: Figs. 14-15; while Figs. 14-15 only show one stepped portion, a mere duplication of parts has no patentable significance unless a new and unexpected result is produced {In re Harza, 274 F.2d 669, 124 USPQ 378 (CCPA 1960)} – in the instant application, no new result is disclosed in comparison to the result as defined in Kaji),
a thickness of each of the plurality of stepped portions is smaller than a thickness of the beam other than the plurality of stepped portions (Kaji: Figs. 14-15; the stepped portions are shown to have a thickness smaller than the thickness of the beam beyond the stepped portions), and
the beam is provided such that the plurality of stepped portions overlap the plurality of case beam portions in plan view (Kaji: Figs. 14-15).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the beam as disclosed by Kimura/Sannai/Karasawa such that it included stepped portions as disclosed by Kaji. One would be motivated to do so as the stepped portions being introduced to the beam can further reduce stress on the beam caused by the warping of the semiconductor device caused by heat generation, and can further prevent the beam from cracking (Kaji: [0055]).
Response to Arguments
Applicant’s arguments, see page 7, filed July 6th, 2026, with respect to the rejection(s) of Claims 1 and 12 under 35 U.S.C. § 102(a)(1) and Claim 13 under 35 U.S.C. § 103 have been fully considered and are persuasive in light of the associated claim amendments. Therefore, the prior rejection has been withdrawn. However, upon further search and consideration, a new ground(s) of rejection is made in view of the combination of Kimura and Sannai (for Claims 1 and 12) and in view of the combination of Kimura, Sannai, and Tanimoto (for Claim 13), as Sannai discloses a terminal that extends from a side of the case into the internal space and toward the base plate (See new rejection associated with Claims 1, 12, and 13 above).
Applicant’s arguments, see page 7, filed July 6th, 2026, with respect to the rejection(s) of Claim 8 under 35 U.S.C. § 103 have been fully considered and are persuasive in light of the associated claim amendment. Therefore, the prior rejection has been withdrawn. However, upon further search and consideration, a new ground(s) of rejection is made in view of the combination of Kimura and Sannai with Karasawa, as Karasawa discloses that all portions of the beam are provided between the plurality of case beam portions (See new rejection associated with Claim 8 above).
In the interest of compact prosecution, Examiner respectfully requests that Applicant please consider a telephone interview with the Examiner to discuss proposed claim amendments to overcome the rejection of Claims 1-13 before filing a written response to this Final Office Action. For example, perhaps Applicant could please consider amending Claim 1 to further limit the terminals such that said claim further defines how and where the terminal is further extending toward the base plate and define that the terminal is in direct physical contact with the insulating substrate instead of mere electric contact through an electrical wire, as is shown in at least Figures 1 and 2. The Examiner would welcome such a discussion and is available at the telephone number provided below.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is (571) 317-0595. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge can be reached at (571) 270-1402. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/NOAH C. ROBERTSON/Examiner, Art Unit 2812
/William B Partridge/Supervisory Patent Examiner, Art Unit 2812
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