DETAILED ACTION Notice of Pre-AIA or AIA Status 1. The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Priority 2. Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. 3. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application. Information Disclosure Statement 4. The information disclosure statement (IDS) filed on December 13 th , 2023, is being considered by the examiner. Double Patenting 5 . The nonstatutory double patenting rejection is based on a judicially created doctrine grounded in public policy (a policy reflected in the statute) so as to prevent the unjustified or improper timewise extension of the “right to exclude” granted by a patent and to prevent possible harassment by multiple assignees. A nonstatutory double patenting rejection is appropriate where the conflicting claims are not identical, but at least one examined application claim is not patentably distinct from the reference claim(s) because the examined application claim is either anticipated by, or would have been obvious over, the reference claim(s). See, e.g., In re Berg , 140 F.3d 1428, 46 USPQ2d 1226 (Fed. Cir. 1998); In re Goodman , 11 F.3d 1046, 29 USPQ2d 2010 (Fed. Cir. 1993); In re Longi , 759 F.2d 887, 225 USPQ 645 (Fed. Cir. 1985); In re Van Ornum , 686 F.2d 937, 214 USPQ 761 (CCPA 1982); In re Vogel , 422 F.2d 438, 164 USPQ 619 (CCPA 1970); In re Thorington , 418 F.2d 528, 163 USPQ 644 (CCPA 1969). 6 . A timely filed terminal disclaimer in compliance with 37 CFR 1.321(c) or 1.321(d) may be used to overcome an actual or provisional rejection based on nonstatutory double patenting provided the reference application or patent either is shown to be commonly owned with the examined application, or claims an invention made as a result of activities undertaken within the scope of a joint research agreement. See MPEP § 717.02 for applications subject to examination under the first inventor to file provisions of the AIA as explained in MPEP § 2159. See MPEP § 2146 et seq. for applications not subject to examination under the first inventor to file provisions of the AIA. A terminal disclaimer must be signed in compliance with 37 CFR 1.321(b). 7 . The filing of a terminal disclaimer by itself is not a complete reply to a nonstatutory double patenting (NSDP) rejection. A complete reply requires that the terminal disclaimer be accompanied by a reply requesting reconsideration of the prior Office action. Even where the NSDP rejection is provisional the reply must be complete. See MPEP § 804, subsection I.B.1. For a reply to a non-final Office action, see 37 CFR 1.111(a). For a reply to final Office action, see 37 CFR 1.113(c). A request for reconsideration while not provided for in 37 CFR 1.113(c) may be filed after final for consideration. See MPEP §§ 706.07(e) and 714.13. 8 . The USPTO Internet website contains terminal disclaimer forms which may be used. Please visit www.uspto.gov/patent/patents-forms. The actual filing date of the application in which the form is filed determines what form (e.g., PTO/SB/25, PTO/SB/26, PTO/AIA/25, or PTO/AIA/26) should be used. A web-based eTerminal Disclaimer may be filled out completely online using web-screens. An eTerminal Disclaimer that meets all requirements is auto-processed and approved immediately upon submission. For more information about eTerminal Disclaimers, refer to www.uspto.gov/patents/apply/applying-online/eterminal-disclaimer . 9. Claim 1 of the instant application is rejected on the ground of nonstatutory double patenting a s being unpatentable over Claim 6 of U.S. Patent No. 11037858 B2 (Kimura, et al.; hereinafter referred to as Kimura) . While the claims at issue are not identical, they are not patentably distinct from each other because Claim 1 is anticipated by Claims 6 of the reference patent (Kimura). Every claim limitation in the instant application is recited in the conflicting reference patent and the differences between the claims is recited in the conflicting reference patent claims, and the differences between the claims are highlighted below by bolding all limitations that differ, italicizing additional limitations, and underlining limitations that will be addressed below. Instant Application (Muto) US Patent No. 11037858 (Kimura) 1. A semiconductor device comprising: a semiconductor element mounted on a base plate a case that has a frame shame in plan view, is attached to the base plate, and houses the semiconductor element inside the frame shape; a beam that has a flat plate shape , is held by the case, and is held over an internal space that is a space inside the frame shape of the case; and a sealing insulating material that fills the internal space of the case and covers at least a part of the beam, wherein the beam is provided above the semiconductor element and covers the semiconductor in plan view. 1. A semiconductor module comprising: a base plate; a semiconductor chip on the base plate; a case surrounding the semiconductor ch ip on the base plate , and sealing resin sealing the semiconductor chip inside the case, Wherein a linear expansion coefficient of the sealing resin increases continuously from the semiconductor chip toward an upper surface of the sealing resin. 5. The semiconductor module according to claim 1, further comprising a plate member sealed with the sealing resin and having a lower linear expansion coefficient than that of the sealing resin. 6. The semiconductor module according to claim 5, wherein the plate member is a beam structure that connects inner walls of the case. 10 . As shown in the mapping above, c laim 6 of the reference patent (Kimura) includes all of the limitations of claim 1 of the instant application, while also reciting further limitations. Claim 1 of the instant application labels the “plate member” of the reference patent as “a beam”; however, the terms are analogous to one another as cited in claim 6 of the reference patent, “the plate member is a beam structure”. Further, c laim 1 of the instant applications cites, “the beam is provided above the semiconductor element and covers the semiconductor in plan view”, which maps to “the plate member is a beam structure that connects inner walls of the case”. By “connecting the inner walls of the case”, the reference patent is inherently providing the beam above the semiconductor element and covering the semiconductor in plan view. Therefore, the limitation as stated in claim 6 of the reference patent anticipates the limitation as cited in claim 1 of the instant application. Claim Rejections - 35 USC § 102 11 . The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. 12 . Claims 1- 5 and 12 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Kimura (US 20200211921 A1; hereinafter referred to as Kimura) . 13 . Regarding Claim 1 , Kimura discloses a semiconductor device ( “ semiconductor module ” , [002]) comprising: a semiconductor element ( semiconductor chips 5 , insulating substrate 2 , electrode 3 and solder 4 , [0018] ; the semiconductor chips, insulating substrate, electrode, and solder, as cited, together form the semiconductor element; these elements are hereinafter referred to together as semiconductor element ) mounted on a base plate ( base plate 1 , [0018], Figs. 7-8 ) ; a case ( case 6 , [0018] ) that has a frame shape in plan view ( Figs. 7-8 ) , is attached to the base plate ( [0018] ) , and houses the semiconductor element inside the frame shape ( Figs. 7-8 ) ; a beam that has a flat plate shape ( plate member 17 , [0030, 0031], Figs. 7-8 ; plate member 17 shall hereinafter be referred to as beam 17 ) , is held by the case ([0030, 0031] ) , and is held over an internal space that is a space inside the frame shape of the case ( Figs. 7-8 ) ; and a sealing insulating material ( sealing resin 9 , [0018] ; hereinafter, sealing resin 9 shall be referred to as sealing insulating material 9 ) that fills the internal space of the case ( 6 , [0018] ) and covers at least a part of the beam ( 17 , [0030] ) , wherein the beam ( 17 ) is provided above the semiconductor element and covers the semiconductor element in plan view ( Figs. 7-8 ) . 14 . Regarding Claim 2 , Kimura explicitly discloses a semiconductor device ( semiconductor module ) according to claim 1, wherein the beam ( 8 ) is provided above a wiring ( wire 8 , [0018] ) passing through a space immediately above the semiconductor element, and covers the wiring in plan view ( Figs. 7-8 ) . 15 . Regarding Claim 3 , Kimura explicitly discloses a semiconductor device ( semiconductor module ) according to claim 1, wherein the internal space includes an opening not covered by the beam ( 17 ) in plan view ( Fig. 7; Fig. 7 explicitly showcases two openings at either end of the beam within the internal space of a case) . 16 . Regarding Claim 4 , Kimura explicitly discloses a semiconductor device ( semiconductor module ) according to claim 1, wherein the beam ( 17 ) includes any one of a resin, glass, a ceramic material ([0030]; “ 17 is an insulator”; resin, glass, and ceramic materials are known in the art to act as an insulator) , and a metal and clad material covered with an insulator ([0030] ; “ 17 may be a conductor such as a metal material, in which case it is insulated from the [ semiconductor element ]”, a metal and clad material can act as either a conductor or insulator and is therefore taught by Kimura) , and the beam ( 17 ) is formed of any one of a single material plate, a cracked plate, and a composite plate ([0030]) , and a linear expansion coefficient of the beam ( 17 ) is smaller than a linear expansion coefficient of the sealing insulating material ([0030]; “ 17 . . . has a linear expansion coefficient that is lower than the linear expansion coefficients of the [ sealing insulating material ] 9 ”) . 17 . Regarding Claim 5 , Kimura explicitly discloses a semiconductor device ( semiconductor module ) according to claim 1, wherein the beam ( 17 ) is a component integrated with the case ([0031]; by way of further explanation, under In re Larson , 340 F.2d 965, 968, 144 USPQ 347, 34 (CCPA 1965), merely integrating an element into a structure, without providing any support in the disclosure as to the criticality of the integration, is not enough to overcome the patentability of the claimed invention. In the instant application, no support is provided as to why integrating the beam would be critical to the semiconductor device.) 18. Regarding Claim 12 , Kimura explicitly discloses a method of manufacturing a semiconductor device, the method comprising the steps of: mounting a semiconductor element on a base plate ([0018]) ; attaching, to the base plate, a case that has a frame shape in plan view ([0018]) and is integrated with a beam ([0031]; “the case 6 and the plate member 17 can be made of a single member”) that has a flat plate shape and is held over an internal space that is a space inside the frame shape of the case (Fig. 8) ; and filling the internal space with a sealing insulating material ([0018]) , wherein in the step of attaching the case to the base plate, the case is attached to the base plate such that the semiconductor element is housed inside the frame shape and the beam is provided above the semiconductor element to cover the semiconductor element in plan view (Fig. 8) , and in the step of filling with the sealing insulating material, the filling is performed such that the sealing insulating material covers at least a part of the beam (Fig. 8) . Claim Rejections - 35 USC § 103 1 9 . The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. 20 . The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows: 1. Determining the scope and contents of the prior art. 2. Ascertaining the differences between the prior art and the claims at issue. 3. Resolving the level of ordinary skill in the pertinent art. 4. Considering objective evidence present in the application indicating obviousness or nonobviousness . 21 . This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. 22 . Claim(s) 6 and 13 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claims 1-5 and 12 above, and further in view of Tanimoto , et al. (JP 2015220238 A; hereinafter referred to as Tanimoto ) . 2 3 . Regarding Claim 6 , Kimura explicitly discloses a semiconductor device ( semiconductor module ) according to claim 1 . Kimura fails to disclose a recess portion on an inner side surface of a frame body constituting the frame shape and that the beam fits into the re c e ss portion of the case. However, Tanimoto discloses a semiconductor device ( 15 , Fig. 8B ) wherein the case ( heat-resistant case 18 ) includes a recess portion on an inner side surface of a frame body constituting the frame shape (Fig. 8B ) , and the beam ( stress relaxation body 21 ; the beam as disclosed in the instant application is analogous to the stress relaxation body of as disclosed in Tanimoto as both serve the purpose of relieving the stress generated by the surrounding resin and/or gel ) fits into the recess portion of the case ( Fig. 8 B ) . It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the case of Kimura such that there is a recess portion within the case for the beam to reside , as taught by Tanimoto . One would make this modification to further support the beam structure during its formation ( Tanimoto [0088]). 2 4 . Regarding Claim 13 , Kimura/ Tanimoto discloses a method of manufacturing a semiconductor device, the method comprising the steps of: mounting a semiconductor element on a base plate ( Tanimoto [0017]) ; attaching, to the base plate, a case that has a frame shape in plan view ( Tanimoto [0015] ) and includes a recess portion on an inner side surface of a frame body constituting the frame shape such that the semiconductor element is housed inside the frame shape ( Tanimoto [ 0088 ], Fig. 8B) ; attaching, to the case, a beam that has a flat plate shape and is held over an internal space that is a space inside the frame shape of the case ( Tanimoto Fig. 8B) ; and filling the internal space with a sealing insulating material ( Tanimoto [0022], Fig. 8B)) , wherein in the step of attaching the beam to the case, the beam is attached to the case such that the beam fits into the recess portion of the case and is provided above the semiconductor element to cover the semiconductor element in plan view ( Tanimoto [0080, 0083, 0086] Fig. 8B) , and in the step of filling with the sealing insulating material, the filling is performed such that the sealing insulating material covers at least a part of the beam ( Tanimoto Fig. 8B) . 2 5 . C laim(s) 7 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claims 1-5 and 12 above, and further in view of Yasutomi , et al. (US 20170345729 A1; hereinafter referred to as Yasutomi ) . 2 6 . Regarding Claim 7 , Kimura discloses a semiconductor device ( semiconductor module ) according to claim 1 . Kimura fails to disclose the semiconductor module wherein the beam has a protrusion on a lower surface of the flat plate shape. However, Yasutomi discloses a semiconductor device ( semiconductor module, [0073] ) wherein the beam ( expansion suppression plate 8 , [0034] ; the beam as taught in Kimura is analogous to the expansion suppression plate as taught in Yasutomi as both suppress the expansion/deformation of a sealant contained within a case ( Yasutomi [0034])) has a protrusion on a lower surface of the flat plate shape ( holes 2c , [0073], Fig. 12 ). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the beam of Kimura such that protrusions exist on the lower surface of the beam. One would have been motivated to do so because Yasutomi teaches that the introduction of a protrusion (holes 2c ) enables the prevention or reduction of both damage to the sealed object (the semiconductor device and the beam) and detachment of the sealing gel (sealing insulating material) ( Yasutomi [0076]). 2 7 . C laim(s) 8-11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Kimura as applied to claims 1-5 and 12 above, and further in view of Kaji , et al. (US20210082778 A1; hereinafter referred to as Kaji ). 2 8 . Regarding Claim 8 , Kimura explicitly discloses the semiconductor device of claim 1 . Kimura fails to disclose a plurality of case beam portions provided on an upper side of the beam, wherein the beam is provided between the plurality of case beam portions in plan view. Kaji , however, discloses a semiconductor device (semiconductor module 1), comprising a plurality of case beam portions provided on an upper side of the beam ( protrusion 5 6 , [0076], Figs. 7 and 8; Kaji discloses protrusion 56 as only a single element; mere duplication of these protrusions has no patentable significance as the result of adding multiple is the same as having only one { In re Harza , 274 F.2d 669, 124 USPQ 378 (CCPA 1960) } ) , wherein the beam ( second barrier layer 60 , [0089, 0094]; second barrier layer 60 and the beam of the instant application are analogous as the second barrier layer can also be made of a resin, a ceramic or glass material [0094], similarly to the instant application ) is provided between the plurality of case beam portions in plan view (Fig s. 14-17). It would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the claimed invention by applying the protrusions as taught by Kaji to the device as disclosed in Kimura. One would have been motivated to do so because, as Kaji teaches, these protrusions create stress relation ports along the beam which reduces the stress imposed on the beam and can prevent cracking ( Kaji [0064, 0065]). 2 9 . Regarding Claim 9 , Kimura/ Kaji discloses a semiconductor device according to claim 8 , further comprising a lid that covers the internal space ( first barrier layer 50 ; [0049], Figs. 14-17; first barrier layer 50 and the lid of the instant application are analogous as the first barrier layer may is provided on the sealing resin [0049] ) , wherein the plurality of case beam portions are provided on a lower surface of the lid (Figs. 14-17) . 30 . Regarding Claim 10 , Kimura/ Kaji discloses a semiconductor device according to claim 8 , wherein the plurality of case beam portions are components integrated with the case. P ursuant to In re Larson , 340 F.2d 965, 968, 144 USPQ 347, 349 (CCPA 1965) , mere integration of elements is not patentably distinct. More specifically, “the use of a one piece construction instead of the structure disclosed in [the prior art] would be merely a matter of obvious engineering choice.” Therefore, Kimura/ Kaji indirectly teaches that the plurality of case beam portions are components integrated with the case. 31 . Regarding Claim 11 , Kimura/ Kaji discloses a semiconductor device according to claim 8, wherein the beam (second barrier layer 60 ) includes a plurality of stepped portions (Figs. 14-15; while Figs. 14-15 only show only stepped portion, a mere duplication of parts has no patentable significance unless a new and unexpected result is produced { In re Harza , 274 F.2d 669, 124 USPQ 378 (CCPA 1960) } – in the instant application, no new result is disclosed in comparison to the result as defined in Kaji ) , a thickness of each of the plurality of stepped portions is smaller than a thickness of the beam other than the plurality of stepped portions (Figs. 14-15; the stepped portions are shown to have a thickness smaller than the thickness of the beam beyond the stepped portions) , and the beam is provided such that the plurality of stepped portions overlap the plurality of case beam portions in plan view (Figs. 14-15) . Conclusion 32. The prior art made of record and not relied upon is considered pertinent to applicant's disclosure: a. Yoshioka, et al. (WO 2024185127 A1), discloses a semiconductor device, and manufacturing method for same, including a beam in suspension surrounded by a sealing resin. b. Nakahara, et al. (US 20190252289 A1), discloses a power module with the beam being placed vertically between the semiconductor elements instead of above. c. Crispell, et al. (US 20080042302 A1), discloses grooves or protrusions attached to a lid covering an integrated circuit. 33. Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571) 317-0595 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone) . 34. Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. 35. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT William B . Partridge can be reached at ( FILLIN "SPE Phone?" \* MERGEFORMAT 571 ) 270-1402 . The fax phone number for the organization where this application or proceeding is assigned is ( 571 ) 273-8300. 36. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at ( 866 ) 217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call ( 800 ) 786-9199 (IN USA OR CANADA) or ( 571 ) 272-1000. /NOAH C. ROBERTSON/ Examiner, Art Unit 2812 /William B Partridge/ Supervisory Patent Examiner, Art Unit 2812