Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant's arguments filed on 06-11-2026 have been fully considered but they are not persuasive. With regard to the §102 rejections of the original claims 1, 2, 4, and 16, the applicant has said that "Lin fails to expressly or inherently teach each and every limitation of claims 1, 2, 4 and 16 as originally filed." However, the applicant has not shown which limitations or arrangement of elements Lin fails to teach. With regard to the §103 rejections of original claims 3, 5-15, and 17-20, applicant has not given any arguments regarding the basis of these rejections.
With regard to the new amendments to the independent claims, the applicant argue that Lin does not teach the newly added features “a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact […] a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact” and that the collective teachings of Lin and Huang fail to teach the newly added feature. While Lin alone does not teach these limitations, when taken in view of Huang, the claimed limitation can be found. Specifically, the first and second encapsulation layers of Huang, 142 and 144, extend below the top surface of the electrode contact via 110 in Huang figure 16A.
Specification
The objections to the specification have been withdrawn in light of the Applicant’s amendments.
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claim(s) 1-3, 5-12, and 14-20 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lin et al. (US 20190096753 A1), hereinafter "Lin" in view of Huang et al. (US 20220310903 A1), hereinafter “Huang”.
Regarding claim 1, Lin discloses a semiconductor structure (Figure 2, “an electronic device 202”), comprising: a memory device comprising a first electrode layer (104), at least one memory element layer disposed on the first electrode layer (204, “the inter-electrode element 204 may be … a data storage element”. A data storage element is a memory element), and a second electrode layer disposed on the at least one memory element layer (206), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (110, the first electrode via is in electrical contact with the electrode and acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer (208, “a pair of spacers” which encapsulate the device and thus form an encapsulation layer); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212, “a sealing layer”, also encapsulates the device), and a metal via disposed on the top surface of the second electrode layer (214).
Lin does not teach that a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact, nor that a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact.
Huang, in the same field of memory devices, teaches a first encapsulation layer wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (142 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0041), as well as a second encapsulation layer wherein a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (144 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0042). Huang also teaches that both of these encapsulation layers help reduce moisture and hydrogen diffusion into the MTJ stacks and reduce bombardment damage during later processing steps (Huang paragraph 0010).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion and reduce bombardment damage during processing steps.
Regarding claim 2, Lin in view of Huang teaches all of the limitations of claim 1. Lin further discloses the second encapsulation layer is further disposed on sidewalls of the second electrode layer (212, is on the sidewalls of 206).
Regarding claim 3, Lin in view of Huang teaches all of the limitations of claim 1.
Lin does not teach that the first encapsulation layer is further disposed on sidewalls of the second electrode layer.
Huang, teaches a first encapsulation layer (142 in Huang figure 16A is a first passivation layer that encapsulates the MRAM structure, paragraph 0041) further disposed on the sidewalls of the second electrode layer (136 in Huang figure 16A). Huang also teaches that the passivation layers help reduce moisture and hydrogen diffusion into the MTJ stacks during later processing steps.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion during processing steps.
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Regarding claim 5, Lin in view of Huang teaches all of the limitations of claim 1, wherein the electrode contact (110) is disposed on a metal layer (228).
Lin does not explicitly teach that the metal layer the electrode contact is disposed on is a patterned metal layer.
Huang teaches the electrode contact is disposed on a patterned metal layer (Huang, L4 in figure 2, see paragraph 0018, “underlying metallization pattern, such as metal lines L4”). Lin also teaches that patterning is an example of a common semiconductor manufacturing process (Lin paragraph 0002).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the present claimed invention, to modify Lin in view of Huang to apply a known technique of metal patterning to a known device, a memory element, ready for improvement to yield predictable results of a pattern of metal lines, as is known art.
Regarding claim 6, Lin in view of Huang teaches all of the limitations of claim 1 wherein the metal via (Lin 214) connects a conductive wire to the second electrode layer (216 in Lin).
Lin does not explicitly teach that the metal via connects a bit line contact to the second electrode layer.
Huang teaches the metal via connects a bit line contact to the second electrode layer (Huang figure 16A, 174L. These are electrically coupled to the logic devices [paragraph 0053], and these logic devices are row decoders and column decoders, where the column decoders select bit lines for the MRAM cells [paragraphs 0011 and 0012]. Therefore, these are contacts for the bit lines. The contacts are connected to second electrode 136 by metal via 174V). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components (Huang paragraph 002 and 0012), useful in electronic device applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line, which would be beneficial to read the individual bits out of an array of memory elements.
Regarding claim 7, Lin in view of Huang teach all of the limitations of claim 6. The combined device shows an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (Lin, fig 2, 210).
Regarding claim 8, Lin in view of Huang teaches all of the limitations of claim 7. The combined device shows the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer (Lin, figure 2, 210 is in between the second encapsulation layer 212 and the conductive wire 216 which would be modified by Huang to be the bit line contact).
Regarding claim 9, Lin in view of Huang teaches al of the limitations of claim 6.
Lin does not explicitly teach the metal via and bit line contact being part of a dual damascene structure.
Huang teaches that the metal via and the bit line contact are part of a dual damascene structure (Huang paragraph 0016, “The interconnect structure 68 may formed by a damascene process, such as … a dual damascene process”. L6 and V6 are a part of the interconnect structure 68, where L6 and V6 are a bit line contact and a metal via). Huang discloses that this is a suitable process for making structures through an ILD layer (Huang paragraph 0015) and that it enables the metal via and bit line contact to be a continuous conductive feature (Huang paragraph 0056).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this known technique of dual damascene to improve a known device, a memory element, ready for improvement and achieve the predictable result of having a stacked via and bit line contact as a continuous conductive element above the second electrode, which would be beneficial for efficient charge flow.
Regarding claim 10, Lin discloses a semiconductor structure (Lin figure 2, “an electronic device 202”), comprising: a memory device comprising a first electrode layer (104), at least one memory element layer disposed on the first electrode layer (204), and a second electrode layer disposed on the at least one memory element layer (206), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (110, the first electrode via is in electrical contact with the electrode and acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer (208); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212).
Lin does not teach that a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact, nor that a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact.
Huang, teaches a first encapsulation layer wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (142 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0041), as well as a second encapsulation layer wherein a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (144 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0042). Huang also teaches that both of these encapsulation layers help reduce moisture and hydrogen diffusion into the MTJ stacks and reduce bombardment damage during later processing steps (Huang paragraph 0010).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion and reduce bombardment damage during processing steps.
Lin also does not teach a bit line contact disposed on the top surface of the second electrode layer and the second encapsulation layer.
Huang teaches a bit line contact disposed on the top surface of the second electrode layer and the second encapsulation layer (Huang 174L). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components (Huang paragraph 002 and 0012), useful in electronic device applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line, which would be beneficial to read the individual bits out of an array of memory elements.
Furthermore, the combined invention shows the bit line contact is separated from the first encapsulation layer by the second encapsulation layer (Lin figure 2. 212 is between 208 and the conductive wire 216 which would be modified by Huang to be the bit line contact).
Regarding claim 11, Lin in view of Huang teaches all of the limitations of claim 10. Lin further teaches the second encapsulation layer is further disposed on sidewalls of the second electrode layer (Lin 212).
Regarding claim 12, Lin in view of Huang teaches all of the limitations of claim 10.
Lin does not teach the first encapsulation layer is further disposed on sidewalls of the second electrode layer.
Huang teaches a first encapsulation layer further disposed on the sidewalls of the second electrode layer (Huang figure 16A, 142 is a first passivation layer that encapsulates the MRAM structure, paragraph 0041). Huang also teaches that the passivation layers help reduce moisture and hydrogen diffusion into the MTJ stacks during later processing steps.
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion during processing steps.
Regarding claim 14, Lin in view of Huang teaches all of the limitations of claim 10, wherein the electrode contact (110) is disposed on a metal layer (228).
Lin does not explicitly teach that the metal layer the electrode contact is disposed on is a patterned metal layer.
Huang teaches the electrode contact is disposed on a patterned metal layer (Huang, L4 in figure 2, see paragraph 0018, “underlying metallization pattern, such as metal lines L4”). Lin also teaches that patterning is an example of a common semiconductor manufacturing process (Lin paragraph 0002).
It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the present claimed invention, to modify Lin in view of Huang to apply a known technique of metal patterning to a known device, a memory element, ready for improvement to yield predictable results of a pattern of metal lines, as is known art.
Regarding claim 15, Lin in view of Huang teaches all of the limitations of claim 10. The combined invention also shows an interlevel dielectric layer disposed on the second encapsulation layer and the bit line contact (Lin 210).
Regarding claim 16, Lin discloses an integrated circuit, comprising: one or more semiconductor structures (paragraph 0004), wherein at least one of the one or more semiconductor structures comprises: a semiconductor structure (Figure 2, “an electronic device 202”), comprising: a memory device comprising a first electrode layer (104), at least one memory element layer disposed on the first electrode layer (204, “the inter-electrode element 204 may be … a data storage element”. A data storage element is a memory element), and a second electrode layer disposed on the at least one memory element layer (206), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (110, the first electrode via is in electrical contact with the electrode and acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer (208, “a pair of spacers” which encapsulate the device and thus form an encapsulation layer); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212, “a sealing layer”, also encapsulates the device), and a metal via disposed on the top surface of the second electrode layer (214).
Lin does not teach that a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact, nor that a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact.
Huang, teaches a first encapsulation layer wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (142 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0041), as well as a second encapsulation layer wherein a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (144 in Huang figure 16A. It is formed conformally in the recesses formed in Huang figure 9, see paragraph 0042). Huang also teaches that both of these encapsulation layers help reduce moisture and hydrogen diffusion into the MTJ stacks and reduce bombardment damage during later processing steps (Huang paragraph 0010).
Therefore, it would have obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion and reduce bombardment damage during processing steps.
Regarding claim 17, Lin in view of Huang teaches all of the limitations of claim 16, wherein the metal via (Lin 214) connects a conductive wire (Lin 216) to the second electrode layer.
Lin does not explicitly teach that the metal via connects a bit line contact to the second electrode layer.
Huang teaches the metal via connects a bit line contact to the second electrode layer (174L in Huang figure 16A). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components (Huang paragraph 002 and 0012), useful in electronic device applications.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line, which would be beneficial to read the individual bits out of an array of memory elements.
Regarding claim 18, Lin in view of Huang teach all of the limitations of claim 17. The combined device shows an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (Lin figure 2, 210).
Regarding claim 19, Lin in view of Huang teaches all of the limitations of claim 18. The combined device shows the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer (Lin, figure 2, 210 is in between the second encapsulation layer 212 and the conductive wire 216 which would be modified by Huang to be the bit line contact).
Regarding claim 20, Lin in view of Huang teaches al of the limitations of claim 17.
Lin does not explicitly teach the metal via and bit line contact being part of a dual damascene structure.
Huang teaches that the metal via and the bit line contact are part of a dual damascene structure (Huang paragraph 0016, “The interconnect structure 68 may formed by a damascene process, such as … a dual damascene process”. L6 and V6 are a part of the interconnect structure 68, where L6 and V6 are a bit line contact and a metal via). Huang discloses that this is a suitable process for making structures through an ILD layer (Huang paragraph 0015) and that it enables the metal via and bit line contact to be a continuous conductive feature (Huang paragraph 0056).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this known technique of dual damascene to improve a known device, a memory element, ready for improvement and achieve the predictable result of having a stacked via and bit line contact as a continuous conductive element above the second electrode, which would be beneficial for efficient charge flow.
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Brent Fairbanks can be reached at 408-918-7532. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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