DETAILED ACTION Notice of Pre-AIA or AIA Status The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA. Specification Applicant is reminded of the proper language and format for an abstract of the disclosure. The abstract should be in narrative form and generally limited to a single paragraph on a separate sheet within the range of 50 to 150 words in length. The abstract should describe the disclosure sufficiently to assist readers in deciding whether there is a need for consulting the full patent text for details. The language should be clear and concise and should not repeat information given in the title. It should avoid using phrases which can be implied, such as, “The disclosure concerns,” “The disclosure defined by this invention,” “The disclosure describes,” etc. In addition, the form and legal phraseology often used in patent claims, such as “means” and “said,” should be avoided. The disclosure is objected to because of the following informalities: • FILLIN "Enter appropriate information" \* MERGEFORMAT In paragraph 0056, "158and" should read "158 and". • In paragraph 0020, it is unclear what is meant by “ where the ILD layer thickness is higher buying opens margin. ” Consider rephrasing for clarity . Appropriate correction is required. The use of the term FILLIN "Identify the term that is a trade name or mark used in commerce." \d "[ 1 ]" NBLoK ™ , which is a trade name or a mark used in commerce, has been noted in this application. Although the use of trade names and marks used in commerce (i.e., trademarks, service marks, certification marks, and collective marks) are permissible in patent applications, the proprietary nature of the marks should be respected and every effort made to prevent their use in any manner which might adversely affect their validity as commercial marks. Claim Rejections - 35 USC § 102 The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action: A person shall be entitled to a patent unless – (a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale , or otherwise available to the public before the effective filing date of the claimed invention. (a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 1, 2, 4, and 16 are rejected under 35 U.S.C. 102 FILLIN "Insert either \“(a)(1)\” or \“(a)(2)\” or both. If paragraph (a)(2) of 35 U.S.C. 102 is applicable, use form paragraph 7.15.01.aia, 7.15.02.aia or 7.15.03.aia where applicable." \d "[ 2 ]" (a)(1) as being FILLIN "Insert either—clearly anticipated—or—anticipated—with an explanation at the end of the paragraph." \d "[ 3 ]" anticipated by FILLIN "Insert the prior art relied upon." \d "[ 4 ]" Lin et al. (US 20190096753 A1) , hereinafter referred to as “Lin”. Regarding claim 1 , Lin discloses a semiconductor structure ( Figure 2, “an electronic device 202”), comprising: a memory device comprising a first electrode layer (10 4 ) , at least one memory element layer disposed on the first electrode layer (204, “t he inter-electrode element 204 may be … a data storage element”. A data storage element is a memory element) , and a second electrode layer disposed on the at least one memory element layer (206) ; a first encapsulation layer disposed on at least sidewalls of the first electrode layer and the at least one memory element layer (208, “a pair of spacers” which encapsulate the device and thus form an encapsulation layer) ; a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212, “a sealing layer”, also encapsulates the device) ; and a metal via disposed on the top surface of the second electrode layer (214) . Regarding claim 2 , Lin discloses all of the limitations of claim 1, and further discloses the second encapsulation layer is further disposed on sidewalls of the second electrode layer (212, is on the sidewalls of 206). Regarding claim 4 , Lin discloses all of the limitations of claim 1, and further discloses a bottom surface of the first electrode layer is disposed on an electrode contact (110, the first electrode via is in electrical contact with the electrode and acts as an electrode contact). Regarding claim 16 , Lin discloses a n integrated circuit, comprising: one or more semiconductor structures (paragraph 0004), wherein at least one of the one or more semiconductor structures comprises: a memory device comprising a first electrode layer (10 4 ) , at least one memory element layer disposed on the first electrode layer (204) , and a second electrode layer disposed on the at least one memory element layer (206) ; a first encapsulation layer disposed on at least sidewalls of the first electrode layer and the at least one memory element layer (208) ; a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212) ; and a metal via disposed on the top surface of the second electrode layer (214) . Claim Rejections - 35 USC § 103 The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action: A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made. This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned as of the effective filing date of the claimed invention(s) absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned as of the effective filing date of the later invention in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention. Claims FILLIN "Insert the claim numbers which are under rejection." \d "[ 1 ]" 3, 5-15, and 17-20 are rejected under 35 U.S.C. 103 as being unpatentable over FILLIN "Insert the prior art relied upon." \d "[ 2 ]" Lin in view of Huang et al. (US 20220310903 A1), hereinafter referred to as "Huang". Regarding claim 3 , Lin teaches all of the limitations of claim 1. Lin does not teach that the first encapsulation layer is further disposed on sidewalls of the second electrode layer. Huang , in the same field of memory devices, teaches a first encapsulation layer ( 142 in Huang figure 16A is a first passivation layer that encapsulates the MRAM structure, paragraph 0041) further disposed on the sidewalls of the second electrode layer (136 in Huang figure 16A). Huang also teaches that the passivation layers help reduce moisture and hydrogen diffusion into the MTJ stacks during later processing steps. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion during processing steps. Regarding claim 5 , Lin teaches all of the limitations of claim 4 , wherein the electrode contact (110) is disposed on a metal layer (228) . Lin does not explicitly teach that the metal layer the electrode contact is disposed on is a patterned metal layer. Huang teaches the electrode contact is disposed on a patterned metal layer ( Huang, L4 in figure 2, see paragraph 0018, “underlying metallization pattern, such as metal lines L4”). Lin also teaches that patterning is an example of a common semiconductor manufacturing process ( Lin paragraph 0002). I t would have been obvious to a person of ordinary skill in the art, before the effective filing date of the present claimed invention, to modify Lin in view of Huang to apply a known technique of metal patterning to a known device, a memory element, ready for improvement to yield predictable results of a pattern of metal lines, as is known art. Regarding claim 6 , Lin teaches all of the limitations of claim 1 wherein the metal via (Lin 214) connects a conductive wire to the second electrode layer (216 in Lin). Lin does not explicitly teach that the metal via connects a bit line contact to the second electrode layer . Huang teaches the metal via connects a bit line contact to the second electrode layer ( Huang f igure 16A, 174L. These are electrically coupled to the logic devices [paragraph 0053], and these logic devices are row decoders and column decoders, where the column decoders select bit lines for the MRAM cells [paragraphs 0011 and 0012]. Therefore, these are contacts for the bit lines . The contacts are connected to second electrode 136 by metal via 174V ). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components ( Huang paragraph 002 and 0012) , useful in electronic device applications . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line , which would be beneficial to read the individual bits out of an array of memory elements. Regarding claim 7 , Lin in view of Huang teach all of the limitations of claim 6. The combined device shows an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (Lin , fig 2, 210). Regarding claim 8 , Lin in view of Huang teaches all of the limitations of claim 7. The combined device shows the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer (Lin, figure 2, 210 is in between the second encapsulation layer 212 and the conductive wire 216 which would be modified by Huang to be the bit line contact). Regarding claim 9 , Lin in view of Huang teaches al of the limitations of claim 6. Lin does not explicitly teach the metal via and bit line contact being part of a dual damascene structure. Huang teaches that the metal via and the bit line contact are part of a dual damascene structure ( Huang paragraph 0016, “ The interconnect structure 68 may formed by a damascene process, such as … a dual damascene proces s”. L6 and V6 are a part of the interconnect structure 68, where L6 and V6 are a bit line contact and a metal via). Huang discloses that this is a suitable process for making structures through an ILD layer ( Huang paragraph 0015) and that it enables the metal via and bit line contact to be a continuous conductive feature (Huang paragraph 0056) . Therefore, it would have been obvious to o ne of ordinary skill in the art before the effective filing date of the claimed invention to use this known technique of dual damascene to improve a known device , a memory element, ready for improvement and achieve the predictable result of having a stacked via and bit line contact as a continuous conductive element above the second electrode, which would be beneficial for efficient charge flow . Regarding claim 10 , Lin discloses a semiconductor structure ( Lin f igure 2, “an electronic device 202”), comprising: a memory device comprising a first electrode layer (10 4 ) , at least one memory element layer disposed on the first electrode layer (204) , and a second electrode layer disposed on the at least one memory element layer (206) ; a first encapsulation layer disposed on at least sidewalls of the first electrode layer and the at least one memory element layer (208) ; a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (212). Lin does not teach a bit line contact disposed on the top surface of the second electrode layer and the second encapsulation layer . Huang teaches a bit line contact disposed on the top surface of the second electrode layer and the second encapsulation layer ( Huang 174L). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components ( Huang paragraph 002 and 0012) , useful in electronic device applications . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line , which would be beneficial to read the individual bits out of an array of memory elements. Furthermore, the combined invention shows the bit line contact is separated from the first encapsulation layer by the second encapsulation layer (Lin figure 2. 212 is between 208 and the conductive wire 216 which would be modified by Huang to be the bit line contact). Regarding claim 11 , Lin in view of Huang teaches all of the limitations of claim 10. Lin further teaches the second encapsulation layer is further disposed on sidewalls of the second electrode layer ( Lin 212). Regarding claim 12 , Lin in view of Huang teaches all of the limitations of claim 10. Lin does not teach the first encapsulation layer is further disposed on sidewalls of the second electrode layer. Huang teaches a first encapsulation layer further disposed on the sidewalls of the second electrode layer ( Huang f igure 16A, 142 is a first passivation layer that encapsulates the MRAM structure, paragraph 0041). Huang also teaches that the passivation layers help reduce moisture and hydrogen diffusion into the MTJ stacks during later processing steps. It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to modify the invention of Lin using the teachings of Huang to reduce moisture and hydrogen diffusion during processing steps. Regarding claim 13 , Lin in view of Huang teaches all of the limitations of claim 10. Lin further teaches a bottom surface of the first electrode layer is disposed on an electrode contact ( Lin 110). Regarding claim 14 , Lin in view of Huang teaches all of the limitations of claim 13 , wherein the electrode contact (110) is disposed on a metal layer (228). Lin does not explicitly teach that the metal layer the electrode contact is disposed on is a patterned metal layer. Huang teaches the electrode contact is disposed on a patterned metal layer (Huang, L4 in figure 2, see paragraph 0018, “underlying metallization pattern, such as metal lines L4”). Lin also teaches that patterning is an example of a common semiconductor manufacturing process (Lin paragraph 0002). It would have been obvious to a person of ordinary skill in the art, before the effective filing date of the present claimed invention, to modify Lin in view of Huang to apply a known technique of metal patterning to a known device, a memory element, ready for improvement to yield predictable results of a pattern of metal lines, as is known art. Regarding claim 15 , Lin in view of Huang teaches all of the limitations of claim 10. The combined invention also shows an interlevel dielectric layer disposed on the second encapsulation layer and the bit line contact (Lin 210). Regarding claim 17 , Lin teaches all of the limitations of claim 16 , wherein the metal via (Lin 214) connects a conductive wire (Lin 216) to the second electrode layer . Lin does not explicitly teach that the metal via connects a bit line contact to the second electrode layer. Huang teaches the metal via connects a bit line contact to the second electrode layer ( 174L in Huang f igure 16A). Huang teaches that these couple with the logic devices, to access the bits stored in the memory components ( Huang paragraph 002 and 0012) , useful in electronic device applications . Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine the bit line contact of Huang with the memory device of Lin to interface with a bit line , which would be beneficial to read the individual bits out of an array of memory elements. Regarding claim 18 , Lin in view of Huang teach all of the limitations of claim 17 . The combined device shows an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (Lin fig ure 2, 210). Regarding claim 19 , Lin in view of Huang teaches all of the limitations of claim 18. The combined device shows the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer (Lin, figure 2, 210 is in between the second encapsulation layer 212 and the conductive wire 216 which would be modified by Huang to be the bit line contact). Regarding claim 20 , Lin in view of Huang teaches al of the limitations of claim 17. Lin does not explicitly teach the metal via and bit line contact being part of a dual damascene structure. Huang teaches that the metal via and the bit line contact are part of a dual damascene structure (Huang paragraph 0016, “ The interconnect structure 68 may formed by a damascene process, such as … a dual damascene proces s”. L6 and V6 are a part of the interconnect structure 68, where L6 and V6 are a bit line contact and a metal via). Huang discloses that this is a suitable process for making structures through an ILD layer (Huang paragraph 0015) and that it enables the metal via and bit line contact to be a continuous conductive feature (Huang paragraph 0056). Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to use this known technique of dual damascene to improve a known device, a memory element, ready for improvement and achieve the predictable result of having a stacked via and bit line contact as a continuous conductive element above the second electrode, which would be beneficial for efficient charge flow. Conclusion Any inquiry concerning this communication or earlier communications from the examiner should be directed to FILLIN "Examiner name" \* MERGEFORMAT DANIEL K ELLIOTT whose telephone number is FILLIN "Phone number" \* MERGEFORMAT (571)357-4606 . The examiner can normally be reached FILLIN "Work Schedule?" \* MERGEFORMAT Mon-Fri 8:00 -5:00 . Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice. If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, FILLIN "SPE Name?" \* MERGEFORMAT Brent Fairbanks can be reached at FILLIN "SPE Phone?" \* MERGEFORMAT 408-918-7532 . The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300. Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000. /DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899 /DALE E PAGE/ Supervisory Patent Examiner, Art Unit 2899