DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Response to Arguments
Applicant’s arguments with respect to claim(s) 1-3, 5-12, and 14-20 have been considered but are moot because the new ground of rejection does not rely on any reference applied in the prior rejection of record for any teaching or matter specifically challenged in the argument.
Claim Rejections - 35 USC § 102
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claim(s) 1-3, 5-7, 9-12, 14-18, and 20 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Yin et al. (US 20210376231 A1), hereinafter referred to as "Yin".
Regarding claim 1, Yin discloses a semiconductor structure, comprising: a memory device comprising a first electrode layer (electrode 126 in Yin figure 17A), at least one memory element layer disposed on the first electrode layer (memory stack 130, 140, 146, and 148 in figure 17A), and a second electrode layer disposed on the at least one memory element layer (electrode 158 in figure 17A), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (via 124 contacts the first electrode and acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer (inner dielectric spacer 162 in figure 17A) extending from a bottom surface of the first electrode layer to a top surface of the at least one memory element layer (see figure 17A), wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (See figure 17A; 162 extends into trench between the memory stacks which goes below the top of the electrode contact); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (outer dielectric spacer 164 in figure 17A), wherein a top portion of the second encapsulation layer is in contact with the second electrode layer (See figure 17A; top part of the second spacer meets with the first spacer at the corner of the second electrode layer, and it is certainly at least in thermal contact) and a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (figure 17A; 164 extends down like 162 does); and a metal via disposed on the top surface of the second electrode layer (narrow portion of 180 in figure 17A).
Regarding claim 2, Yin discloses all of the limitations of claim 1, and further discloses that the second encapsulation layer is further disposed on sidewalls of the second electrode layer (Yin figure 17A, the outer spacer 164 is on the sidewalls of the inner spacer 162, which is on the sidewalls of the second electrode layer 148, and thus 164 is on the sidewalls of 148).
Regarding claim 3, Yin discloses all of the limitations of claim 1, and further discloses that the first encapsulation layer is further disposed on sidewalls of the second electrode layer (See Yin figure 17A).
Regarding claim 5, Yin discloses all of the limitations of claim 1, and further discloses that the electrode contact is disposed on a patterned metal layer (electrode contact 124 is on metal vias and lines 622 and 628 in figure 17A, which can be formed by dual damascene, which is a patterning process; see Yin paragraph 0037).
Regarding claim 6, Yin discloses all of the limitations of claim 1, and further discloses that the metal via connects a bit line contact to the second electrode layer (the wider portion of 180 contacts the line 192, which can be a bit line – see Yin paragraph 0083 – and is therefore a bit line contact. This part is connected to the second electrode 148 by the narrow portion of 180).
Regarding claim 7, Yin discloses all of the limitations of claim 6, and further discloses an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (dielectric layer 170, 176, and 190 in figure 17A).
Regarding claim 9, Yin discloses all of the limitations of claim 6, and further discloses that the metal via and the bit line contact are part of a dual damascene structure (Figures 10-15 and 17A; the process that forms the via and bit line contact yields the same structure as that of the dual damascene process).
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Regarding claim 10, Yin discloses a semiconductor structure, comprising: a memory device (devices in memory region 100) comprising a first electrode layer (126 in Yin figure 22), at least one memory element layer disposed on the first electrode layer (130, 140, 146, and 148 in figure 22), and a second electrode layer disposed on the at least one memory element layer (158 in figure 22), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (via 124 acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer (162 in figure 22), wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (see figure 22); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (164 in figure 22), wherein a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (see figure 22); and a bit line contact in contact with the top surface of the second electrode layer and vertical sidewalls of the second encapsulation layer (180 in figure 22 contacts bit line 192, and thus is a bit line contact. It is also on the top surface of 158 and sidewalls of 164); wherein the bit line contact is separated from the first encapsulation layer by the second encapsulation layer (See figure 22; 164 is between bit line contact 180 and inner spacer 162).
Regarding claim 11, Yin discloses all of the limitations of claim 10, and further discloses that the second encapsulation layer is further disposed on sidewalls of the second electrode layer (Yin figure 17A, the outer spacer 164 is on the sidewalls of the inner spacer 162, which is on the sidewalls of the second electrode layer 148, and thus 164 is on the sidewalls of 148).
Regarding claim 12, Yin discloses all of the limitations of claim 10, and further discloses that the first encapsulation layer is further disposed on sidewalls of the second electrode layer (See Yin figure 17A).
Regarding claim 14, Yin discloses all of the limitations of claim 10, and further discloses that the electrode contact is disposed on a patterned metal layer (electrode contact 124 is on metal vias and lines 622 and 628 in figure 17A, which can be formed by dual damascene, which is a patterning process; see Yin paragraph 0037).
Regarding claim 15, Yin discloses all of the limitations of claim 10, and further discloses an interlevel dielectric layer disposed on the second encapsulation layer and the bit line contact (dielectric layer 170, 176, and 190 in figure 17A).
Regarding claim 16, Yin discloses an integrated circuit, comprising: one or more semiconductor structures (Yin figure 17A shows several devices such as transistors and memory structures integrated together into a circuit), wherein at least one of the one or more semiconductor structures comprises: a memory device comprising a first electrode layer (126 in figure 17A), at least one memory element layer disposed on the first electrode layer (130, 140, 146, and 148 in figure 17A), and a second electrode layer disposed on the at least one memory element layer (158 in figure 17A), wherein a bottom surface of the first electrode layer is disposed on an electrode contact (124 acts as an electrode contact); a first encapsulation layer disposed on at least vertical sidewalls of the first electrode layer and the at least one memory element layer extending from a bottom surface of the first electrode layer to a top surface of the at least one memory element layer (162 in figure 17A), wherein a bottom surface of the first encapsulation layer extends below the bottom surface of the first electrode layer and a top surface of the electrode contact (162 extends below top surface of 124 and bottom surface of 126); a second encapsulation layer disposed on the first encapsulation layer and above a top surface of the second electrode layer (164 in figure 17A), wherein a top surface of the second encapsulation layer is in contact with the second electrode layer (See figure 17A; top part of the second spacer meets with the first spacer at the corner of the second electrode layer, and it is certainly at least in thermal contact) and a bottom surface of the second encapsulation layer extends below the bottom surface of the first electrode layer and the top surface of the electrode contact (164 extends below the second electrode like 162); and a metal via disposed on the top surface of the second electrode layer (narrow portion of 180 in figure 17A).
Regarding claim 17, Yin discloses all of the limitations of claim 16, and further discloses that the metal via connects a bit line contact to the second electrode layer (the wider portion of 180 contacts the line 192, which can be a bit line – see Yin paragraph 0083 – and is therefore a bit line contact. This part is connected to the second electrode 148 by the narrow portion of 180).
Regarding claim 18, Yin discloses all of the limitations of claim 17, and further discloses an interlevel dielectric layer disposed on the second encapsulation layer, the metal via and the bit line contact (dielectric layer 170, 176, and 190 in figure 17A).
Regarding claim 20, Yin discloses all of the limitations of claim 17, and further discloses that the metal via and the bit line contact are part of a dual damascene structure (Figures 10-15 and 17A; the process that forms the via and bit line contact yields the same structure as that of the dual damascene process).
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
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Claims 8 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Yin in view of Lin et al. (US 20190096753 A1), hereinafter referred to as Lin.
Regarding claim 8, Yin discloses all of the limitations of claim 7. Yin does not disclose that the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer.
Lin teaches an interlevel dielectric layer that separates a second encapsulation layer from an above metal layer (Lin figure 2; dielectric 212 separates sealing layer 212 from conductive wire 216). Lin also teaches that this dielectric layer can be a low k or extremely low k dielectric (Lin paragraph 0025). It is known that low k dielectrics provide reduced capacitance due to the lower dielectric constant, and thus this dielectric layer would help reduce parasitic capacitance between components better than the higher k dielectrics used by Yin.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the bit line contact be separated from the second encapsulation layer by the interlevel dielectric layer like in Lin in order to reduce the parasitic capacitance.
Regarding claim 19, Yin discloses all of the limitations of claim 18. Yin does not disclose that the bit line contact is separated from the second encapsulation layer by the interlevel dielectric layer.
Lin teaches an interlevel dielectric layer that separates a second encapsulation layer from an above metal layer (Lin figure 2; dielectric 212 separates sealing layer 212 from conductive wire 216). Lin also teaches that this dielectric layer can be a low k or extremely low k dielectric (Lin paragraph 0025). It is known that low k dielectrics provide reduced capacitance due to the lower dielectric constant, and thus this dielectric layer would help reduce parasitic capacitance between components better than the higher k dielectrics used by Yin.
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have the bit line contact be separated from the second encapsulation layer by the interlevel dielectric layer like in Lin in order to reduce the parasitic capacitance.
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to DANIEL K ELLIOTT whose telephone number is (571)357-4606. The examiner can normally be reached Mon-Fri 8:00 -5:00.
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/DANIEL KURT ELLIOTT/ Examiner, Art Unit 2899
/Brent A. Fairbanks/ Supervisory Patent Examiner, Art Unit 2899
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