Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Objections
Claim 2 is objected to because of the following informalities: the claim ends in a semi-colon rather than a period.
Claim 9 is objected to because of the following informalities: claim 9 recites the limitation “a voltage generator to provide a voltage to one or more rows of the analog neural memory array, the voltage generator, wherein the voltage is generated. . .”. It appears that the phrase “the voltage generator” was erroneously recited into the claim limitation. Appropriate correction is required.
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claims 1-8 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al (US 20200234111 A1, herein Tran_111) in view of Bowers et al (US 5714892 A, herein Bowers).
Regarding claim 1, Tran_111 teaches a system comprising: an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns (para. [0091] recites “FIG. 8 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present embodiments”. Para. [0104]-[0105] recite “FIG. 11 depicts neuron VMM array 1100, which is particularly suited for memory cells 310 as shown in FIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 1100 comprises memory array 1101 of non-volatile memory cells and reference array 1102 (at the top of the array) of non-volatile reference memory cells. In VMM array 1100, control gate lines, such as control gate line 1103, run in a vertical direction (hence reference array 1102 in the row direction is orthogonal to control gate line 1103), and erase gate lines, such as erase gate line 1104, run in a horizontal direction” (i.e., an analog neural network array comprising non-volatile memory cells arranged in rows and columns)); and
a voltage generator to provide a voltage to one or more rows of the analog neural memory array (para. [0101] recites “FIG. 10 is a block diagram depicting the usage of numerous layers of VMM arrays 32, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31, and provided to input VMM array 32a. The converted analog inputs could be voltage or current” (i.e., a voltage generator to the analog neural network)), the voltage generator [comprising a voltage ladder] to generate a plurality of voltages according to a logarithmic formula (para. [0197] recites “FIG. 40 depicts current-to-logarithmic voltage converter 4000, which optionally can be used to convert a neuron output current into a logarithmic voltage, that for example, can be applied as an input (for example, on a WL or a CG line) of the VMM memory array” (i.e., generating voltages according to a logarithmic formula)).
However, Tran_111 does not explicitly teach wherein the voltage generator comprises a voltage ladder.
Bowers teaches wherein the voltage generator comprises a voltage ladder (col. 9 lines 21-32 recite “FIG. 6 illustrates a pinout-limited voltage output DAC which incorporates the new three state input stage to provide a logic input and a control input on the same integrated circuit pin. In this way. the controller the controller 56 controls the connections between the voltage references VrefH and VrefL and an output block 18. The output section 62 consists of an R2R ladder 70, each input node of which is conventionally connected through the switching section 58 to either VrefH and VrefL” (i.e. a voltage ladder)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine these teachings by to modify the DAC voltage generator from Tran_111 with the DAC voltage generator comprising a voltage ladder from Bowers. Tran_111 and Bowers are both directed to digital-to-analog converters; but while Tran_111 teaches a DAC voltage generator in at least paragraph [0100], Tran_111 does not specify whether this DAC comprises a voltage ladder. One or ordinary skill in the art would be motivated to substitute the known voltage ladder DAC configuration from Bowers in for the known DAC voltage generator from Tran_111 to convert digital bits to an appropriate analog level.
Regarding claim 2, the combination of Tran_111 and Bowers teaches the system of claim 1 as mentioned above, comprising: a mapping block to trim the plurality of voltages and provide one of the plurality of voltages as an output voltage in response to a control signal (Tran_111 para. [0207] recites “FIG. 49 depicts an embodiment where activation occurs before the neuron output is converted into a pulse of variable width or a pulse series”. Tran_111 para. [0208] recites “the digital output bits are mapped to a new set of digital bits using an activation mapping table or function implemented by activation mapping unit 5010. Examples of such a mapping are shown graphically in FIGS. 50 and 51” (i.e., a mapping function, or block, to edit, or trim the output voltages)).
Regarding claim 3, the combination of Tran_111 and Bowers teaches the system of claim 2 as mentioned above, comprising: an output buffer to receive the output voltage and provide a buffered voltage to the analog neural memory array (Tran_111 fig. 33 and para. [0142] recite “neuron output blocks 3302a, 3302b, 3302c, 3302d, 3302e, 3302/, 3302g, and 3302h each includes a buffer ( e.g., op amp) low impedance output type circuit that can drive a long, configurable interconnect” (i.e., an output buffer for the analog neural network)).
Regarding claim 4, the combination of Tran_111 and Bowers teaches the system of claim 1 as mentioned above, wherein the voltage generator receives a high voltage from a first voltage source and a low voltage from a second voltage source and the plurality of voltages are greater than or equal to the low voltage and less than or equal to the high voltage (Bowers col. 9 lines 21-39 recite “FIG. 6 illustrates a pinout-limited voltage output DAC which incorporates the new three state input stage to provide a logic input and a control input on the same integrated circuit pin. In this way, the controller the controller 56 controls the connections between the voltage references VrefH and VrefL and an output block 18. The output section 62 consists of an R2R ladder 70, each input node of which is conventionally connected through the switching section 58 to either VrefH and VrefL. The DAC's analog output voltage Vout is highest with all the input nodes connected to the high reference VrefH, lowest with all the input nodes connected to the low reference VrefL and takes on intermediate values corresponding to the values of the binary combinations stored within the registers 64” (i.e., receiving a high voltage from a first source and a low voltage from a second source, wherein the voltages between are between the high and low voltage values)).
Regarding claim 5, the combination of Tran_111 and Bowers teaches the system of claim 4 as mentioned above, wherein the voltage generator comprises a plurality of resistors in series, wherein a first end of the plurality of resistors is coupled to the high voltage source and a second end of the plurality of resistors is coupled to the low voltage source (Bowers col. 8 lines 66-67 recite “A voltage output DAC connects each input node of an R2R resistor ladder through analog switches to one of two voltage references”. Bowers fig. 6 and col. 9 lines 28-39 recite “the controller the controller 56 controls the connections between the voltage references VrefH and VrefL and an output block 18. The output section 62 consists of an R2R ladder 70, each input node of which is conventionally connected through the switching section 58 to either VrefH and VrefL. The DAC's analog output voltage Vout is highest with all the input nodes connected to the high reference VrefH, lowest with all the input nodes connected to the low reference VrefL and takes on intermediate values corresponding to the values of the binary combinations stored within the registers 64” (i.e., a voltage ladder comprising a series of resistors coupled to a high and low voltage source)).
Regarding claim 6, the combination of Tran_111 and Bowers teaches the system of claim 1 as mentioned above, wherein the voltage causes non-volatile memory cells in the one or more rows to operate in one or more of a sub-threshold region, a linear region, and a saturation region (Tran_111 para. [0106] recites “the non-volatile memory cells of VMM array 1100, i.e. the flash memory of VMM array 1100, are preferably configured to operate in a sub-threshold region”. Tran_111 para. [0112] recites “the flash memory cells of VMM arrays described herein can be configured to operate in the linear region”. Tran_111 para. [0115] recites “the flash memory cells of VMM arrays described herein can be configured to operate in the saturation region” (i.e., operating in one or more of a sub-threshold, linear, or saturation region)).
Regarding claim 7, the combination of Tran_111 and Bowers teaches the system of claim 1 as mentioned above, wherein the non-volatile memory cells comprise stacked- gate flash memory cells (Tran_111 para. [0085] recites “FIG. 7 depicts stacked gate memory cell 710, which is another type of flash memory cell).
Regarding claim 8, the combination of Tran_111 and Bowers teaches the system of claim 1 as mentioned above, wherein the non-volatile memory cells comprise split-gate flash memory cells (Tran_111 para. [0074] recites “Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ("the '130 patent"), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in FIG. 2”).
Claims 9-10 and 14-15 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al (US 20200234111 A1, herein Tran_111) in view of Tran et al (US 20200019848 A1, herein Tran_848).
Regarding claim 9, Tran_111 teaches a system comprising: an analog neural memory array comprising a plurality of non-volatile memory cells arranged into rows and columns (para. [0091] recites “FIG. 8 conceptually illustrates a non-limiting example of a neural network utilizing a non-volatile memory array of the present embodiments”. Para. [0104]-[0105] recite “FIG. 11 depicts neuron VMM array 1100, which is particularly suited for memory cells 310 as shown in FIG. 3, and is utilized as the synapses and parts of neurons between an input layer and the next layer. VMM array 1100 comprises memory array 1101 of non-volatile memory cells and reference array 1102 (at the top of the array) of non-volatile reference memory cells. In VMM array 1100, control gate lines, such as control gate line 1103, run in a vertical direction (hence reference array 1102 in the row direction is orthogonal to control gate line 1103), and erase gate lines, such as erase gate line 1104, run in a horizontal direction” (i.e., an analog neural network array comprising non-volatile memory cells arranged in rows and columns)); and
a voltage generator to provide a voltage to one or more rows of the analog neural memory array (para. [0101] recites “FIG. 10 is a block diagram depicting the usage of numerous layers of VMM arrays 32, here labeled as VMM arrays 32a, 32b, 32c, 32d, and 32e. As shown in FIG. 10, the input, denoted Inputx, is converted from digital to analog by a digital-to-analog converter 31, and provided to input VMM array 32a. The converted analog inputs could be voltage or current” (i.e., a voltage generator to the analog neural network)), the voltage generator.
However, Tran_111 does not explicitly teach wherein the voltage is generated based on an I-V characteristic of the plurality of non-volatile memory cells.
Tran_848 teaches wherein the voltage is generated based on an I-V characteristic of the plurality of non-volatile memory cells (para. [0076] recites “FIG. 8 is a block diagram of the various levels of VMM. As shown in FIG. 8, the input is converted from digital to analog by digital-to-analog converter 31, and provided to input VMM 32a. The converted analog inputs could be voltage or current”. Para. [0111] recites “FIG. 19 depicts an exemplary reference transistor 1900 with a configuration, which is the same configuration shown in FIG. 18A. FIG. 20 depicts another exemplary reference memory cell with another configuration (wordline coupled to bitline), and FIG. 21 depicts another exemplary reference memory cell with another configuration (floating gate FG coupled to bitline). It can be appreciated that each of these devices might have a different current-voltage characteristic curve” (i.e., generating voltages based on different I-V characteristics)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine these teachings by using the voltage generation method based on I-V characteristics from Tran_848 to modify the voltage generation method from Tran_111. Tran_111 and Tran_848 are both directed to digital-to-analog converters for analog neural networks; however, Tran_111 does not explicitly teach taking different current-voltage characteristic curves into account in its description of the digital-to-analog converter. One or ordinary skill in the art would be motivated to apply the known voltage generation method from Tran_848 to the known digital-to-analog converter from Tran_111 to account for different current-voltage characteristic curves.
Regarding, claim 10, the combination of Tran_111 and Tran_848 teaches the system of claim 9 as mentioned above, wherein the voltage causes non-volatile memory cells in the one or more rows to operate in one or more of a sub-threshold region, a linear region, and a saturation region (Tran_111 para. [0106] recites “the non-volatile memory cells of VMM array 1100, i.e. the flash memory of VMM array 1100, are preferably configured to operate in a sub-threshold region”. Tran_111 para. [0112] recites “the flash memory cells of VMM arrays described herein can be configured to operate in the linear region”. Tran_111 para. [0115] recites “the flash memory cells of VMM arrays described herein can be configured to operate in the saturation region” (i.e., operating in one or more of a sub-threshold, linear, or saturation region)).
Regarding claim 14, the combination of Tran_111 and Tran_848 teaches the system of claim 9 as mentioned above, wherein the non-volatile memory cells comprise stacked-gate flash memory cells (Tran_111 para. [0085] recites “FIG. 7 depicts stacked gate memory cell 710, which is another type of flash memory cell).
Regarding claim 15 the combination of Tran_111 and Tran_848 teaches the system of claim 9 as mentioned above, wherein the non-volatile memory cells comprise split-gate flash memory cells (Tran_111 para. [0074] recites “Digital non-volatile memories are well known. For example, U.S. Pat. No. 5,029,130 ("the '130 patent"), which is incorporated herein by reference, discloses an array of split gate non-volatile memory cells, which are a type of flash memory cells. Such a memory cell 210 is shown in FIG. 2”).
Claims 11-13 are rejected under 35 U.S.C. 103 as being unpatentable over Tran et al (US 20200234111 A1, herein Tran_111) in view of Tran et al* (US 20200019848 A1, herein Tran_848), in further view of Bowers et al (US 5714892 A, herein Bowers).
*this document was cited in the IDS dated 12/13/2023
Regarding claim 11, the combination of Tran_111 and Tran_848 teaches the system of claim 9 as mentioned above.
However, the combination of Tran_111 and Tran_848 does not explicitly teach wherein the voltage generator comprises a voltage ladder.
Bowers teaches wherein the voltage generator comprises a voltage ladder (Bowers col. 9 lines 21-32 recite “FIG. 6 illustrates a pinout-limited voltage output DAC which incorporates the new three state input stage to provide a logic input and a control input on the same integrated circuit pin. In this way, the controller the controller 56 controls the connections between the voltage references VrefH and VrefL and an output block 18. The output section 62 consists of an R2R ladder 70, each input node of which is conventionally connected through the switching section 58 to either VrefH and VrefL” (i.e. a voltage ladder)).
Therefore, it would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to combine these teachings by to modify the DAC voltage generator from Tran_111 (as modified by Tran_848) with the DAC voltage generator comprising a voltage ladder from Bowers. Tran_111 and Bowers are both directed to digital-to-analog converters; but while Tran_111 teaches a DAC voltage generator in at least paragraph [0100], Tran_111 does not specify whether this DAC comprises a voltage ladder. One or ordinary skill in the art would be motivated to substitute the known voltage ladder DAC configuration from Bowers in for the known DAC voltage generator from Tran_111 to convert digital bits to an appropriate analog level.
Regarding claim 12, the combination of Tran_111, Tran_848, and Bowers teaches the system of claim 11 as mentioned above, wherein the voltage ladder generates a plurality of voltages according to a logarithmic formula (Tran_111 para. [0197] recites “FIG. 40 depicts current-to-logarithmic voltage converter 4000, which optionally can be used to convert a neuron output current into a logarithmic voltage, that for example, can be applied as an input (for example, on a WL or a CG line) of the VMM memory array” (i.e., generating voltages according to a logarithmic formula)).
Regarding claim 13, the combination of Tran_111, Tran_848, and Bowers teaches the system of claim 11 as mentioned above, wherein the voltage ladder generates a plurality of voltages according to a linear formula (Tran_111 para. [0112] recites “the flash memory cells of VMM arrays described herein can be configured to operate in the linear region”. Tran_111 para. [0114] recites “For an I-to-V linear converter, a memory cell (such as a reference memory cell or a peripheral memory cell) or a transistor operating in the linear region or a resistor can be used to linearly convert an input/output current into an input/output voltage” (i.e., generating voltages according to a linear formula)).
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
“Modeling split-gate flash memory cell for advanced neuromorphic computing” (Tadayoni et al) teaches a SPICE model of a split-gate flash memory cell, implemented in a 180 nm CMOS technology, that allows the users to set the individual memory cell to any precise analog state.
“Modeling R−2R Segmented-Ladder DACs” (Marche et al) teaches derivations for expressions for the input and output impedances of R-2R ladders for current- and voltage-mode operations and an equivalent circuit is proposed for voltage mode designs.
“Logarithmic Analog-to-Digital Converters: A Survey” (Cantarano et al) teaches an overview of analog-to-digital converters with logarithmic law including cascade connections, digital connections, and analog connections.
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/L.M.F./ Examiner, Art Unit 2147
/MARC S SOMERS/Primary Examiner, Art Unit 2159
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