MEMORY DEVICE AND METHOD OF MANUFACTURING MEMORY DEVICE

Application No. 18/538,967

• Filed: Dec 13, 2023
• Priority: Jul 20, 2023 — RE 10-2023-0094811
• Examiner: ROBERTSON, NOAH CHRISTOPHER
• Art Unit: 2812
• Tech Center: 2800 — Semiconductors & Electrical Systems
• Assignee: SK hynix Inc.
• OA Round: 1 (Non-Final)

Office Action

DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .

Election/Restrictions
Applicant's election with traverse of Group I (Claims 1-11) in the reply filed on June 9th, 2026, is acknowledged. The traversal is on the ground(s) that, following amendment to Claim 12 in which the limitation, “a metal line” was removed, Group I and Group II now constitute common elements and that there would be no substantial increase in the search burden that would result from examining Group I and Group II together. Applicant’s arguments are persuasive in light of the amendments made to Claim 12 and, therefore, Examiner withdraws the restriction requirement between the inventions of Group I and Group II.

Examiner in the Election/Restriction Requirement further required an election of species upon election of Group I. The election requirement between Sub-Species IA and Sub-Species IB would still be required with the restriction requirement between Group I and Group II being withdrawn. Applicant’s reply failed to elect a species, with or without traverse. Therefore, Examiner held an interview with attorney of record, Susan Lukasik, Esq., on June 22nd, 2026, wherein Sub-Species IA (i.e., claim 10) was elected and Sub-Species IB (i.e., claim 11) was withdrawn pending possible rejoinder.

Examiner further notes that applicant did not traverse the restriction requirement between the claimed inventions of Groups I and II with the claimed invention of Group III in applicant’s reply filed on June 9th, 2026. Examiner acknowledges that applicant has withdrawn the claimed invention of Group III (Claims 18-21) in its reply filed on June 9th, 2026, pending the allowance of the product or apparatus claims per the process of rejoinder. As such, Claims 18-21 are hereby marked withdrawn and the Restriction/Election is FINAL.

Status of Claims
Pursuant to applicant’s reply to restriction requirement filed on June 9th, 2026, and the above response to arguments, Claims 1-21 are pending; however, Claims 11 and 18-21, for the above stated reasons, are withdrawn and are not subject to the within examination.

Priority
Receipt is acknowledged of certified copies of papers required by 37 CFR 1.55. More specifically, the foreign priority to foreign application KR10-2023-0094811 filed July 20th, 2023, is acknowledged. However, should applicant desire to obtain the benefit of foreign priority under 35 U.S.C. 119(a)-(d) prior to declaration of an interference, a certified English translation of the foreign application must be submitted in reply to this action. 37 CFR 41.154(b) and 41.202(e). Failure to provide a certified translation may result in no benefit being accorded for the non-English application.

Information Disclosure Statement
The information disclosure statement (IDS) filed on December 13th, 2023, is being considered by the Examiner.

Drawings
The drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they do not include the following reference sign(s) mentioned in the description: “TS” ([0051], top surface TS). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.

Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.

The specification is objected to for the following reasons. Pursuant to [0067] of the instant specification, “the second pad portion P2 of the first bonding pad PAD1 . . . does not overlap micro pattern lines adjacent to the corresponding micro pattern line 203”, and further states, “The first pad portion P1 of the first bonding pad PAD1, however may overlap the corresponding micro pattern line 203 and the adjacent micro pattern lines”. However, Claim 9 states, “wherein the second pad portion overlaps micro pattern lines located adjacent to the predetermined micro pattern line”. Therefore, the specification appears to contradict the claims. Further, in [0051] of the instant specification, the specification states that first pad portion is a portion exposed through a top surface of the memory chip and that the second pad portion is in mechanical and electrical contact with the bit line/micro pattern line. However, Claim 1 states the inverse, such that first pad portion is the portion in direct and electric contact with the bit line/micro pattern line and the second pad portion is exposed through a top surface of the memory chip. In short, it appears that the instant specification inverts the naming of the first and second pad portion. Therefore, for the purposes of compact prosecution, the Examiner shall interpret the first pad portion and the second pad portion as they are defined in the claims (i.e., a first pad portion electrically coupled to the predetermined micro pattern line and a second pad portion coupled to the first pad portion and exposed at a top surface of the memory chip) and not how they are defined in the specification. Appropriate correction to the specification is required.

Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –

(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.

Claim(s) 12-15 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Lee (US 20210320114 A1; hereinafter referred to as Lee).

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Regarding Claim 12, Lee discloses a memory device comprising:
a memory cell array (memory array AR, [0111], Fig. 5A);
a plurality of bit lines located on the memory cell array (bit lines BL, [0112, 0114], Figs. 5A-5B);
a plurality of first bonding pads coupled to the plurality of bit lines, respectively (second bonding pad PB2’, [0116], Fig. 5A); and
a plurality of second bonding pads (first bonding pads PB1’, [0105], Fig. 5A);
wherein the first bonding pads and the second bonding pads are bonded ([0110]); and
wherein each of the first bonding pads has a pin structure (Fig. 5A).

Regarding Claim 13, Lee discloses the memory device according to claim 12, wherein each of the first bonding pads comprises:
a first pad portion directly coupled to any one of the plurality of bit lines (see Annotated Fig. 5A); and
a second pad portion coupled to the first pad portion (see annotated Fig. 5A).

Regarding Claim 14, Lee discloses the memory device according to claim 13, wherein each of the bonding pads comprises:
a barrier metal layer located on a sidewall and a bottom surface of the first pad portion and a bottom surface of the second pad portion (barrier part BP_B, [0032], Fig. 3); and
a bonding pad material disposed on the barrier metal layer (conductive part BP_C, [0032], Fig. 3).

Regarding Claim 15, Lee discloses the memory device according to claim 14, wherein the barrier metal layer is located only on a bottom surface of each of the first bonding pads (Fig. 5A).

Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.

The factual inquiries for establishing a background for determining obviousness under 35 U.S.C. 103 are summarized as follows:
(a) Determining the scope and contents of the prior art.
(b) Ascertaining the differences between the prior art and the claims at issue.
(c) Resolving the level of ordinary skill in the pertinent art.
(d) Considering objective evidence present in the application indicating obviousness or nonobviousness.

Claim(s) 1-8 and 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu, et al. (US 20220238454 A1; hereinafter referred to as Chiu) and further in view of Chiang, et al. (US 20230008792 A1; hereinafter referred to as Chiang).

Regarding Claim 1, Chiu discloses a memory chip ([0010], “memory cell”) comprising:
a plurality of micro pattern lines (conductive lines 152, [0017], Fig. 9A);
a capping layer covering portions of the micro pattern lines (etch stop layer (ESL) 210 and first passivation layer 220 [the combination together forms a capping layer], [0019], Fig. 9A); and
a bonding pad penetrating the capping layer (barrier layer 230 and pad layer 240 [the combination together forms a bonding pad], [0022], Fig. 9A), said bonding pad being electrically coupled to a predetermined micro pattern line (Fig. 9A);
wherein the bonding pad comprises:
a first pad portion electrically coupled to the predetermined micro pattern line (see Annotated Fig. 9A); and
a second pad portion coupled to the first pad portion and exposed at a top surface of the memory chip (see Annotated Fig. 9A).

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Chiu is silent on the upper surface of the second pad portion having a convex shape.
However, in analogous art, Chiang discloses an upper surface of the second pad portion has a convex shape ([0003], Fig. 6).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the bonding pad as taught by Chiu such that the bonding pad has a convex upper surface of the second pad portion as disclosed by Chiang. One would be motivated to do so as having a convex upper surface, or even a concave upper surface, can lead to less stress at the bonding interface between two semiconductor structures/chips which improves device reliability (Chiang: [0003]).

Regarding Claim 2, Chiu/Chiang discloses the memory chip according to claim 1, wherein the bonding pad comprises:
a barrier metal layer located on a sidewall and a bottom surface of the first pad portion and a bottom surface of the second pad portion (Chiu: barrier layer 230, [0022], Fig. 9A); and
a bonding pad material disposed on the barrier metal layer (Chiu: pad layer 240, [0022], Fig. 9A).

Regarding Claim 3, Chiu/Chiang discloses the memory chip according to claim 2, wherein the bonding pad material comprises copper (Chiu: [0030], “the conductive material 240′ is a metal layer and may include aluminum (Al), although it may also be made of copper (Cu), silver (Ag), gold (Au), nickel (Ni), tungsten (W), alloys, or any combination thereof”).

Regarding Claim 4, Chiu/Chiang discloses the memory chip according to claim 2, wherein the barrier metal layer is located only on the bottom surface of the bonding pad (Chiu: Fig. 9A).

Regarding Claim 5, Chiu/Chiang discloses the memory chip according to claim 2, wherein the first pad portion penetrates the capping layer (Chiu: Fig. 9A).

Regarding Claim 6, Chiu/Chiang discloses the memory chip according to claim 5, wherein the capping layer comprises:
a first capping layer disposed on the upper portions of the plurality of micro pattern lines (Chiu: ESL 210, [0018], Fig. 9A), and including a silicon nitride layer (Chiu: [0018], “the ESL 210 may be formed of SiNx …”); and
a second capping layer disposed over the first capping layer (Chiu: first passivation layer 220, [0019], Fig. 9A), and including a silicon oxide layer (Chiu: [0019], “The first passivation layer 220 may be made of non-organic material selected from un-doped silicate glass (USG), silicon nitride, silicon oxynitride, silicon oxide, and/or multi-layers thereof”).

Regarding Claim 7, Chiu/Chiang discloses the memory chip according to claim 5, further comprising:
a buffer layer disposed over the capping layer (Chiu: second passivation layer 250, [0034], Fig. 9A),
wherein a side of the second pad portion contacts the buffer layer (Chiu: Fig. 9A).

Regarding Claim 8, Chiu/Chiang discloses the memory chip according to claim 7, wherein the buffer layer contacts the bonding pad material (Chiu: Fig. 9A).

Regarding Claim 10, Chiu/Chiang discloses the memory chip according to claim 1, wherein the bonding pad has a damascene structure (Chiu: Figs. 3A-6, the process shown in said figures is a damascene process of forming a bonding pad).

Claim(s) 9 is/are rejected under 35 U.S.C. 103 as being unpatentable over Chiu/Chang as applied to claims 1-8 and 10 above, and further in view of Lee (US 20210320114 A1; hereinafter referred to as Lee).

Regarding Claim 9, Chiu/Chiang discloses the memory chip according to claim 1.
The combination of Chiu/Chiang is silent on the second pad portion overlaps micro pattern lines located adjacent to the predetermined micro pattern line.
However, in analogous art, Lee discloses a bonding pad with a second pad portion and a first pad portion (Lee: [0118], see Annotated Lee Fig. 5A above), wherein the second pad portion overlaps micro pattern lines located adjacent to the predetermined micro pattern line (see Annotated Lee Fig. 5A; the second pad portion overlaps with adjacent micro pattern lines to the predetermined micro pattern line).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the second bonding pad portion as taught by the combination of Chiu/Chiang such that it overlaps with micro pattern lines adjacent to the predetermined micro pattern line. One would be motivated to do so as a structure in this form can lead to higher device reliability and lower power consumption as semiconductor structures (e.g., bit lines/micro pattern lines) continue to scale down in size (Lee: [0004-0005]).

Claim(s) 16-17 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lee as applied to claims 12-15 above, and further in view of Chiu, et al. (US 20220238454 A1; hereinafter referred to as Chiu).

Regarding Claim 16, Lee discloses the memory device according to claim 15.
Lee is silent on the memory device further comprising a capping layer and a buffer layer sequentially disposed on upper portions of the plurality of bit lines, wherein the first pad portion penetrates the capping layer, and the second pad portion penetrates the buffer layer.
However, in analogous art, Chiu discloses a memory device further comprising:
a capping layer (Chiu: etch stop layer (ESL) 210 and first passivation layer 220 [the combination together forms a capping layer], [0019]) and a buffer layer (Chiu: second passivation layer 250, [0034]) sequentially disposed on upper portions of the plurality of bit lines (Chiu: Fig. 9A),
wherein the first pad portion penetrates the capping layer (Chiu: Fig. 9A), and the second pad portion penetrates the buffer layer (Chiu: Fig. 9A).
Therefore, it would have been obvious to one of ordinary skill in the art prior to the effective filing date of the instant application to modify the memory device as disclosed by Lee such that there is a capping layer and a buffer layer in which the first pad portion of the first bonding pads penetrates the capping layer and the second pad portion of the first bonding pads penetrates the buffer layer. One would be motivated to make this modification as the capping layer provides a mechanism of stopping the etching process when forming the vias or contacts near the bonding pad and provides additional protection to the bit lines when etching (Chiu: [0018]). Similarly, one would be motivated to introduce a buffer layer as, both the buffer layer and the capping layer, can further decreases the risk of damage to the device during the etching process and prevent diffusion between electrical layers (Chiu: [0009]).

Regarding Claim 17, Lee/Chiu discloses the memory device according to claim 16, wherein the bonding pad material contacts the buffer layer (Chiu: Fig. 9A).

Conclusion
For the purpose of compact prosecution, Examiner notes that Lee does not appear to expressly disclose the limitations of Claim 1 and all of its dependent claims and Chiu/Chiang does not appear to expressly disclose the limitations of Claim 12 and all of its dependent claims. Assuming arguendo, were either reference/combination of references overcome, it does not expressly mean the claims are allowable, and further search and consideration would be needed.
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
(a) Futatsuyama, et al. (US 20240284673 A1); discloses a memory device with multiple bonding pads and a plurality of bit lines
(b) Lee (US 20220068885 A1); discloses a memory device.

Any inquiry concerning this communication or earlier communications from the examiner should be directed to Noah C. Robertson whose telephone number is [phone]. The examiner can normally be reached Monday-Friday 9:30 AM - 6:30 PM (Eastern Time Zone).

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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, William B Partridge, can be reached at [phone]. The fax phone number for the organization where this application or proceeding is assigned is [phone].

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/Noah C. Robertson/Examiner, Art Unit 2812

/William B Partridge/Supervisory Patent Examiner, Art Unit 2812

Prosecution Timeline

• Dec 13, 2023: Application Filed
• Jun 22, 2026: Examiner Interview (Telephonic)
• Jun 23, 2026: Examiner Interview Summary
• Jul 24, 2026: Non-Final Rejection mailed — §102, §103 (current)