DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to because in Figure 3, step 340 recites “Receiving a hold signal from the microcontroller to the first switch” and Applicant’s Figure 1 shows that the hold signal (HOLD) is applied to the second switch (130). Appropriate correction is required.
Furthermore, the drawings are objected to as failing to comply with 37 CFR 1.84(p)(5) because they include the following reference character(s) not mentioned in the description: Step 350 in Figure 3 is not mentioned in Applicant’s specification.
Corrected drawing sheets in compliance with 37 CFR 1.121(d), or amendment to the specification to add the reference character(s) in the description in compliance with 37 CFR 1.121(b) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Specification
The disclosure is objected to because of the following informalities: Figures 3 and 4 are not included in the Brief Description of the Drawings section.
Appropriate correction is required.
Claim Rejections - 35 USC § 112
The following is a quotation of the first paragraph of 35 U.S.C. 112(a):
(a) IN GENERAL.—The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor or joint inventor of carrying out the invention.
The following is a quotation of the first paragraph of pre-AIA 35 U.S.C. 112:
The specification shall contain a written description of the invention, and of the manner and process of making and using it, in such full, clear, concise, and exact terms as to enable any person skilled in the art to which it pertains, or with which it is most nearly connected, to make and use the same, and shall set forth the best mode contemplated by the inventor of carrying out his invention.
Claims 1-6 are rejected under 35 U.S.C. 112(a) or 35 U.S.C. 112 (pre-AIA ), first paragraph, as failing to comply with the written description requirement. The claim(s) contains subject matter which was not described in the specification in such a way as to reasonably convey to one skilled in the relevant art that the inventor or a joint inventor, or for applications subject to pre-AIA 35 U.S.C. 112, the inventor(s), at the time the application was filed, had possession of the claimed invention.
Claim 1 recites “a first switch configured to be controlled by a source of the first FET.” Examiner notes that in Applicant’s Figure 1, the gate of 120 is controlled by the drain of the first FET 110.
Claims 2-5 are rejected for being dependent on claim 1.
Claim 6 recites “a second FET with a gate in electrical communication with the input line and a source in in [sic] electrical communication with a pullup resistor and a sleep signal output.” Examiner notes that the second FET 150 has a drain connected to the pullup resistor 145 and SLEEP.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale, or otherwise available to the public before the effective filing date of the claimed invention.
Claim(s) 1-7 is/are rejected under 35 U.S.C. 102(a)(1) as being anticipated by Cook et al. (U.S. Patent 2019/0341803 cited in the Information Disclosure Statement filed December 9, 2024, hereafter Cook).
Claim 1: Cook teaches an apparatus (Figures 1, 2A, 2B and 4E) comprising:
an input line (VIN_MAIN) configured to receive a signal from a low voltage differential signal line ([0019] to select between main power or battery power; [0086]);
a first field effect transistor (FET) (473; Figure 4E) with a gate in electrical communication with the input line (via VBSW_EN, which is connected to VIN_MAIN through the circuitry of Figure 2C);
a first switch (471; Figure 4E) configured to be controlled by a drain of the first FET (gate of 471 is connected to the drain of 473);
a power input (Vbat) in electrical communication with a first side of the first switch (via 426);
a power output (to D1; Figure 4E) in electrical communication with a second side of the first switch (via 472);
a second switch (122; Figure 2A) with a first side in electrical communication with the source of the first FET (sources of 122 and 476 are coupled to ground) and configured to receive a hold control signal (Hibernate); and
a second FET (475; Figure 4E) with a gate in electrical communication with the input line (via 476 and the circuitry of Figure 2C) and a drain in electrical communication with a pullup resistor (R2) and a sleep signal output (via the operation of 476).
Claim 2: Cook further teaches that the first switch comprises a MOSFET (471; Figure 4E) and the second switch comprises a BJT ([0057]).
Claim 3: Cook further teaches a power source in electrical communication with the power input (Vbat is from battery 22; Figure 1).
Claim 4: Cook further teaches a microcontroller (10; Figure 1) configured to (1) receive power through the power output (via 32; Figure 1), (2) output the hold control signal (via Hibernate), and (3) receive a sleep signal from the sleep signal output (via VBSW_ENP).
Claim 5: Cook further teaches that the first FET and the second FET are selected with a gate voltage threshold in the range of 1.26 volts and 3.17 volts ([0086] where hibernate control circuits can operate at any voltage, including 1.4V).
Claim 6: Cook teaches a method of waking up a microcontroller in an apparatus (Figures 1, 2A, 2B and 4E) comprising:
an input line (VIN_MAIN) configured to receive a signal from a low voltage differential signal line ([0019] to select between main power or battery power; [0086]);
a first field effect transistor (FET) (473; Figure 4E) with a gate in electrical communication with the input line (via VBSW_EN and the circuitry of Figure 2A);
a first switch (471) configured to be controlled by a drain of the first FET (473);
a power input (Vbat) in electrical communication with a first side of the first switch (via 426);
a power source (Vbat is from battery 22; Figure 1) in electrical communication with the power input (from 22);
a power output (to D1; Figure 4E) in electrical communication with a second side of the first switch (via 472);
a second switch (122; Figure 2A) with a first side in electrical communication with the drain of the first FET (via Vbat) and configured to receive a hold control signal (via Hibernate);
a second FET (476; Figure 4E) with a gate in electrical communication with the input line (via VBSW_ENP and the circuitry of Figure 2B) and a drain in in electrical communication with a pullup resistor (R2) and a sleep signal output (output of 476 controlled by VBSW_ENP); and
a microcontroller (10; Figure 1) configured to (1) receive power through the power output (via 32; Figure 1), (2) output the hold control signal (via 476), and (3) receive a sleep signal from the sleep signal output (via VSBW_EN and 476); and
comprising the steps of:
extracting an analog signal from the low voltage differential signal line (to generate VBSW_EN and VBSW_ENP);
energizing the gate of the first FET to connect the power input to the power output through the first switch (via 473);
energizing the microcontroller using power from the power source communicated through the first switch (via Hibernate Power); and
receiving a hold signal from the microcontroller to the first switch to maintain the first switch connecting the power input to the power output (to keep 473 on and 476 off via the circuitry of Figures 2A and 2B).
Claim 7: Cook teaches a method of shutting down a microcontroller in an apparatus (Figures 1, 2A, 2B and 4E) comprising:
an input line (VIN_MAIN) configured to receive a signal from a low voltage differential signal line ([0019] to select between main power or battery power; [0086]);
a first field effect transistor (FET) (473; Figure 4E) with a gate in electrical communication with the input line (via VBSW_EN and the circuitry of Figure 2A);
a first switch (471) configured to be controlled by a drain of the first FET (473);
a power input (Vbat) in electrical communication with a first side of the first switch (via 426);
a power source (Vbat is from battery 22; Figure 1) in electrical communication with the power input (from 22);
a power output (to D1; Figure 4E) in electrical communication with a second side of the first switch (via 472);
a second switch (122; Figure 2A) with a first side in electrical communication with the drain of the first FET (via Vbat) and configured to receive a hold control signal (via Hibernate);
a second FET (476; Figure 4E) with a gate in electrical communication with the input line (via VBSW_ENP and the circuitry of Figure 2B) and a drain in in electrical communication with a pullup resistor (R2) and a sleep signal output (output of 476 controlled by VBSW_ENP); and
a microcontroller (10; Figure 1) configured to (1) receive power through the power output (via 32; Figure 1), (2) output the hold control signal (via 476), and (3) receive a sleep signal from the sleep signal output (via VSBW_EN and 476); and
comprising the steps of:
extracting an analog signal from the low voltage differential single line (to generate VBSW_EN and VBSW_ENP);
deenergizing the gate of the second FET to energize the sleep signal output (output of 476 when 476 is off);
running a power off sequence on the microcontroller (via VBSW_ENP and 10); and
initiating a signal (VBSW_ENP) to open the second switch which opens the first switch (via VBSW_EN) and terminates power to the microcontroller (from main power).
Conclusion
Any inquiry concerning this communication or earlier communications from the examiner should be directed to COLLEEN J O'TOOLE whose telephone number is (571)270-1273. The examiner can normally be reached Monday - Friday, 9:00 am - 6:00pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Menatoallah Youssef can be reached at (571)270-3684. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
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/C.J.O/Examiner, Art Unit 2849
/Menatoallah Youssef/SPE, Art Unit 2849