DETAILED ACTION
Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Priority
The present application is a divisional of U.S. Application No. 17/342,462, filed June 8, 2021, now U.S. Patent No. 11,881,707 B2, issued January 23, 2024, which claims the benefit of U.S. Provisional Application No. 63/042,963, filed June 23, 2020 and U.S. Provisional Application No. 63/036,346, filed June 8, 2020.
Election/Restrictions
Applicant’s election without traverse of Group II, claims 9-17 in the reply filed on April 9, 2026 is acknowledged. Claims 1-8 and 18-20 are withdrawn from further consideration pursuant to 37 CFR 1.142(b
Information Disclosure Statement
The information disclosure statement (IDS) submitted on December 13, 2023, November 4, 2024, June 5, 2025, September 23, 2025, and December 9, 2025 are in compliance with the provisions of 37 CFR 1.97. Accordingly, the information disclosure statement is being considered by the examiner.
Specification
The title of the invention is not descriptive. A new title is required that is clearly indicative of the invention to which the claims are directed.
Drawings
The drawings were received on December 13, 2023. These drawings are acceptable.
Examination Notice
In the event the determination of the status of the application as subject to AIA 35 U.S.C. 102 and 103 (or as subject to pre-AIA 35 U.S.C. 102 and 103) is incorrect, any correction of the statutory basis for the rejection will not be considered a new ground of rejection if the prior art relied upon, and the rationale supporting the rejection, would be the same under either status.
This application currently names joint inventors. In considering patentability of the claims the examiner presumes that the subject matter of the various claims was commonly owned at the time any inventions covered therein were effectively filed absent any evidence to the contrary. Applicant is advised of the obligation under 37 CFR 1.56 to point out the inventor and effective filing dates of each claim that was not commonly owned at the time a later invention was effectively filed in order for the examiner to consider the applicability of 35 U.S.C. 102(b)(2)(C) for any potential 35 U.S.C. 102(a)(2) prior art against the later invention.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claim(s) 9-11 and 17 are rejected under 35 U.S.C. 102 (a)(1) and 35 U.S.C. 102 (a)(2) as being anticipated by Williams (5,517,379).
With regard to claim 9, Williams teaches a method for managing current flow through a battery pack cutoff circuit (10 – Fig. 2, Fig. 3), the method comprising:
flowing a current from a first node (A – Fig. 3; see annotated figure below) that is coupled to a control input (gate of 10 – Fig. 3) of the battery pack cutoff circuit (10 – Fig. 3) to a second node (B – Fig. 3; see annotated figure below) that is coupled to an output (drain of 10 – Fig. 3) of the battery pack cutoff circuit (10 – Fig. 3) while preventing current flow across the control input (gate of 10 – Fig. 3) to the output (drain of 10 – Fig. 3) in response to a negative voltage being applied to the second node (B – Fig. 3; see annotated figure below) (col. 2, lines 19-26; col. 4, lines 59-61).
With regard to claim 10, Williams teaches all the limitations of claim 9, and further teaches further comprising not flowing the current from the first node (A – Fig. 3; see annotated figure below) to the second node (B – Fig. 3; see annotated figure below) in response to an absence of the negative voltage at the second node (Abstract, lines 3-6).
With regard to claim 11, Williams teaches all the limitations of claim 9, and further teaches wherein flowing the current from the first node (A – Fig. 3; see annotated figure below) to the second node (A – Fig. 3; see annotated figure below) is enabled by activating a transistor (23 – Fig. 3; see annotated figure below).
With regard to claim 17, Williams teaches all the limitations of claim 11, and further teaches the first node (A – Fig. 3; see annotated figure below) and second node (B – Fig. 3; see annotated figure below) are included a reverse bias protection circuit (22 – Fig. 2), and the reverse bias protection circuit (22 – Fig. 2) is coupled to a driver integrated circuit (20 – Fig. 2) via three pins (Ground, Undervoltage Flag, Output of 22 to transistor 23 – See Fig. 2).
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Williams (5,517,379) – Annotated Fig. 3
Allowable Subject Matter
Claim(s) 12-16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
With regard to claim 12, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein the current flows from ground to the transistor by flowing through two diodes.”
Claim(s) 13 is allowed by dependence on claim 12.
With regard to claim 14, in combination with other limitations of the claim, the prior art fails to teach or fairly suggest “wherein the transistor is a low-current leakage transistor and activating the transistor includes increasing a base-emitter voltage (VBE) of the low-current leakage transistor.”
Claim(s) 15-16 are allowed by dependence on claim 14.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure. Please see attached PTO-892.
Gagnon (US 10,778,019 B2) teaches a battery reverse polarity protection circuit is disclosed. The battery reverse polarity protection circuit includes a field effect transistor (FET) coupled to a control circuit. The FET is configured to transmit an input voltage from a normal-polarity-connected battery to an output terminal, and block the input voltage from a reverses polarity-connected battery to the output terminal. The control circuit is coupled to the input terminal, the output terminal, and a common terminal and is configured to detect, during transmission of the input voltage from the normal-polarity-connected battery to the output terminal, that the input voltage is less than an output voltage, indicating onset of an abnormal operating mode, and turn off the FET to prevent the output voltage from being affected by the input voltage during the abnormal operating mode.
Park (US 2024/0077541 A1) teaches an apparatus for measuring voltage in a battery including battery cells connected in series includes a positive voltage sensing circuit to detect each voltage of the battery cells, received through sensing terminals, within a positive voltage range, a reverse voltage protection circuit including protection circuits, the printed circuits including first ends respectively connected to the plurality of sensing terminals different from each other, and second ends connected to each other, a boosting resistor including a first end connected to at least one electrode of the battery, and a reverse voltage sensing circuit to detect a voltage between the first node at which the second ends of the protection circuits are connected to each other and a second node to which a second end of the boosting resistor is connected, and based on the detection, output a signal indicating whether a reverse voltage is generated in the battery.
Contact Information
Any inquiry concerning this communication or earlier communications from the examiner should be directed to Nicolas Bellido whose telephone number is (571) 272-5034. The examiner can normally be reached Monday to Friday from 9:00 am to 5:00 pm.
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If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Monica Lewis can be reached at (571) 272-1838. The fax phone number for the organization where this application or proceeding is assigned is (571) 273-8300.
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/N.B./Examiner, Art Unit 2838
/MONICA LEWIS/Supervisory Patent Examiner, Art Unit 2838
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