Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim(s) 1-5, 9, and 12-15 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (U.S. PGPUB 20170097825) in view of Wu (CN 114518900).
With respect to claim 1, Lo et al. disclose a method to implement thread group execution ordering via branch target prioritization in a data processor, the method comprising:
executing a branch instruction in a thread group comprising a plurality of converged threads (paragraph 27, There are, however, points in a program (i.e., branches) where threads in a thread group are allowed to “diverge” from each other so that one or more threads may execute instructions on their respective samples that do not need to be executed by the other threads in the thread group, thus “converged” before the “diverged” state); and
forming a plurality of converged thread sub-groups from the thread group, each thread sub-group comprising a common code block to configure and execute a loop (paragraph 27, the twelve threads are divided into three thread groups (i.e. thread group 0, thread group 1 and thread group 2), paragraph 28, For threads in the same thread group (e.g. thread 0 through thread 3), a program counter is shared so that operations to be executed by each thread should be the same for a given clock cycle, paragraph 50, Thus, in a given cycle, all processing engine 802 in core 808 nominally executes the same instruction for different threads in the same thread group). However, Lo et al. do not expressly disclose each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of multiple target addresses of the branch instruction.
Wu, who also deals with parallel processing, discloses a method wherein each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of multiple target addresses of the branch instruction (paragraph 8, selecting the branch jump information including the target instruction address from the branch jump history record with the highest priority).
Lo et al. and Wu are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of multiple target addresses of the branch instruction, as taught by Wu, to the Lo et al. system, because since the first branch jump history record is stored in the first processing core, the first processing core can obtain the branch jump information from the first branch jump history record at the fastest speed, which can provide a method for quickly reading the branch jump information (paragraph 8 of Wu).
With respect to claim 2, Lo et al. as modified by Wu disclose the method of claim 1, wherein the common code block is configured to store one of the multiple target addresses in a first per-thread register (Lo et al.: paragraph 11, The plurality of registers is configured for storing operands associated with the multiple threads), paragraph 41, The compiler 601 further includes a register allocator 613 and a code generator 615. When the analysis module 611 finishes the analysis on the instruction sequence, the register allocator 613 allocates registers to source and destination operands (e.g. b0 through b11) for each instruction, and the code generator module 615 generates executable machine code (such as the compiled code of FIG. 4) according to the redirection array) and a corresponding one of the pre-configured priorities in a second per-thread register (Lo et al.: paragraph 11, The plurality of registers is configured for storing operands associated with the multiple threads, Wu: paragraph 6, The first branch jump history record is stored in the first processing core, and the second branch jump history record is stored in the second processing core. The number of branch jump information including the target instruction address may be one or more, paragraph 8, selecting the branch jump information including the target instruction address from the branch jump history record with the highest priority).
With respect to claim 3, Lo et al. as modified by Wu disclose the method of claim 2, wherein the common code block is further configured to determine a highest of the priorities stored in the per-thread registers of the thread sub-groups (Wu: paragraph 8, When more than two branch jump history records are found to include the target instruction address, the branch jump information may be selected according to the priority. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record).
With respect to claim 4, Lo et al. as modified by Wu disclose the method of claim 3, wherein the common code block is further configured to store the highest of the priorities in a shared register (Wu: paragraph 8, the first processing core selects branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record).
With respect to claim 5, Lo et al. as modified by Wu disclose the method of claim 4. Lo et al. disclose a warp-wide register (paragraph 41, the register allocator 613 allocates registers to source and destination operands (e.g. b0 through b11) for each instruction, and the code generator module 615 generates executable machine code (such as the compiled code of FIG. 4) according to the redirection array). It would have been obvious to implement the shared register is a warp-wide register, because this would optimize use of the computer hardware.
With respect to claim 9, Lo et al. disclose a system (paragraph 42, FIG. 7 illustrates a diagrammatic representation of a machine in the exemplary form of the computer system 600) comprising: at least one processor (paragraph 43, The computer system 600 includes a processing circuit 602. The processing circuit 602 represents one or more general-purpose processors); and logic that configures the at least one processor to: form a plurality of converged thread sub-groups from a main thread group, each thread sub-group comprising a common code block (paragraph 27, the twelve threads are divided into three thread groups (i.e. thread group 0, thread group 1 and thread group 2), paragraph 28, For threads in the same thread group (e.g. thread 0 through thread 3), a program counter is shared so that operations to be executed by each thread should be the same for a given clock cycle, paragraph 50, Thus, in a given cycle, all processing engine 802 in core 808 nominally executes the same instruction for different threads in the same thread group). However, Lo et al. do not expressly disclose configuring a loop in the common code block each thread sub-group to jump to a different target address of a branch instruction in an order determined by a priority configured for each different target address.
Wu, who also deals with parallel processing, discloses a method for configuring a loop in the common code block each thread sub-group to jump to a different target address of a branch instruction in an order determined by a priority configured for each different target address (paragraph 8, selecting the branch jump information including the target instruction address from the branch jump history record with the highest priority, When more than two branch jump history records are found to include the target instruction address, the branch jump information may be selected according to the priority).
Lo et al. and Wu are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of configuring a loop in the common code block each thread sub-group to jump to a different target address of a branch instruction in an order determined by a priority configured for each different target address, as taught by Wu, to the Lo et al. system, because since the first branch jump history record is stored in the first processing core, the first processing core can obtain the branch jump information from the first branch jump history record at the fastest speed, which can provide a method for quickly reading the branch jump information (paragraph 8 of Wu).
With respect to claim 12, Lo et al. as modified by Wu disclose the system of claim 9, wherein the different target addresses are prioritized by resource consumption of code blocks at the different target addresses (Wu: paragraph 57, the distance from each processing core to the first processing core is obtained, and the priority of the branch jump history records of each processing core is set according to the distance).
With respect to claim 13, Lo et al. as modified by Wu disclose the system of claim 9, wherein target addresses of code blocks comprising long-latency instructions are prioritized over target addresses of code blocks that do not comprise long-latency instructions (Wu: paragraph 57, the distance from each processing core to the first processing core is obtained, and the priority of the branch jump history records of each processing core is set according to the distance. The distance is negatively correlated with the priority).
With respect to claim 14, Lo et al. as modified by Wu disclose the system of claim 9, wherein the common code block is configured to determine a highest of the configured priorities of the target addresses stored in per-thread registers of the thread sub-groups (Wu: paragraph 8, When more than two branch jump history records are found to include the target instruction address, the branch jump information may be selected according to the priority. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record).
With respect to claim 15, Lo et al. as modified by Wu disclose the system of claim 14, wherein the common code block is further configured to store the highest of the configured priorities in a shared register (Wu: paragraph 8, When more than two branch jump history records are found to include the target instruction address, the branch jump information may be selected according to the priority. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record).
Claim(s) 7-8 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (U.S. PGPUB 20170097825) in view of Wu (CN 114518900) and further in view of Kothinti Naresh (U.S. PGPUB 20210089313).
With respect to claim 7, Lo et al. as modified by Wu disclose the method of claim 1. However, Lo et al. as modified by Wu do not expressly disclose the multiple target addresses comprise an address of a fall-through target instruction and an address of an alternate target instruction.
Kothinti Naresh, who also deals with parallel processing, disclose a method wherein the multiple target addresses comprise an address of a fall-through target instruction and an address of an alternate target instruction (paragraph 45, The indication of a conditional branch instruction 424F may be contained in a conditional branch instruction record 506 received by the branch hammock detection circuit 452 that also includes the branch target address of the conditional branch instruction 424F, and the branch fall-through address of the conditional branch instruction 424F).
Lo et al., Wu, and Kothinti Naresh are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the multiple target addresses comprise an address of a fall-through target instruction and an address of an alternate target instruction, as taught by Kothinti Naresh, to the Lo et al. as modified by Wu system, because the detection of a branch hammock for a conditional branch instruction 424F can be used by the processor to optimize processing, including when the conditional branch instruction 424F is again processed at a later time (paragraph 45 of Kothinti Naresh).
With respect to claim 8, Lo et al. as modified by Wu and Kothinti Naresh disclose the method of claim 1, wherein the multiple target addresses comprise an address of at least three different target instructions (Kothinti Naresh: paragraph 46, To initiate the training process for an in-training branch hammock, the branch hammock control circuit 502 is configured to allocate a branch state entry 508 associated with the indicator (e.g., PC) for a branch condition instruction among a plurality of branch state entries 508(1)-508(B) in a branch state table circuit 510. As will be discussed in more detail below, each branch state entry 508(1)-508(B) includes entries that can be used to track and store information about an in-training branch hammock as the instruction processing circuit 422 processes instructions following the conditional branch instruction 424F). Three entries 508(1), 508(2), and 508(B) corresponds to at least three target instructions. It would have been obvious to apply the teachings of Kothinti Naresh because branch state entries 508(1)-508(B) can also be used to record information about the instructions 424F executed following the conditional branch instruction 424F to be used for predicting future values of the instructions 424F when the conditional branch instruction 424F is fetched again into the instruction processing circuit 422 (paragraph 46 of Kothinti Naresh).
Claim(s) 10 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (U.S. PGPUB 20170097825) in view of Wu (CN 114518900) and further in view of Chen et al. (U.S. Patent No. 10,120,685).
With respect to claim 10, Lo et al. as modified by Wu disclose the system of claim 9. However, Lo et al. as modified by Wu do not expressly disclose: logic to configure the at least one processor to configure a stack of loops in the common code block to implement a hierarchy of prioritizations for the different target addresses.
Chen et al., who also deal with parallel processing, disclose a method for including logic to configure the at least one processor to configure a stack of loops in the common code block to implement a hierarchy of prioritizations for the different target addresses (column 8, lines 59-67, a “lowest” iteration number (oldest iteration) gets highest priority for decode/execution. Thus, if instructions from multiple iterations are ready for execution (i.e., they have all been pre-decoded and the register inputs for these instructions have been procured and placed in the operand buffers), then the HW picks the instruction associated with the lowest iteration number ready for execution. If in a particular clock cycle, a loop iteration with a lower iteration number is stalled (e.g., while it is waiting for data), the HW will automatically execute the instruction from the next higher iteration number that is ready, i.e., that has all the data available for execution).
Lo et al., Wu, and Chen et al. are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of including logic to configure the at least one processor to configure a stack of loops in the common code block to implement a hierarchy of prioritizations for the different target addresses, as taught by Chen et al., to the Lo et al. as modified by Wu system, because this frees up the operand buffers 420 for the decode of the next instruction in the following cycle (column 9, lines 27-28 of Chen et al.).
Claim(s) 11 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (U.S. PGPUB 20170097825) in view of Wu (CN 114518900) and further in view of Croxford et al. (U.S. PGPUB 20240036874).
With respect to claim 11, Lo et al. as modified by Wu disclose the system of claim 9. However, Lo et al. as modified by Wu do not expressly disclose the main thread group comprises an instruction block of a ray tracing application.
Croxford et al., who also deal with parallel processing, disclose a method wherein the main thread group comprises an instruction block of a ray tracing application (paragraph 226, the technology disclosed herein is also applicable to hybrid-ray tracing and raytracing).
Lo et al., Wu, and Croxford et al. are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein the main thread group comprises an instruction block of a ray tracing application, as taught by Croxford et al., to the Lo et al. as modified by Wu system, because this would implement additional methods of generating computer graphics besides rasterization.
Claim(s) 17-21 is/are rejected under 35 U.S.C. 103 as being unpatentable over Lo et al. (U.S. PGPUB 20170097825) in view of Croxford et al. (U.S. PGPUB 20240036874), Nevraev et al. (U.S. PGPUB 20180232936), and further in view of Wu (CN 114518900).
With respect to claim 17, Lo et al. disclose a non-transitory machine readable medium comprising instructions (paragraph 46, the computer system 600 store and transmit (internally and/or with other electronic devices over a network) code (composed of software instructions) and data using computer-readable media (also referred to as a machine-readable medium, a processor-readable medium, or a computer usable medium having a computer readable program code embodied therein), such as non-transitory tangible computer-readable media) that, when applied to one or more data processor, cause the data processor to implement:
executing a branch instruction in a thread group comprising a plurality of converged threads (paragraph 27, There are, however, points in a program (i.e., branches) where threads in a thread group are allowed to “diverge” from each other so that one or more threads may execute instructions on their respective samples that do not need to be executed by the other threads in the thread group, thus “converged” before the “diverged” state),
forming a plurality of converged thread sub-groups from the thread group, each thread sub-group comprising a common code block to configure and execute a loop (paragraph 27, the twelve threads are divided into three thread groups (i.e. thread group 0, thread group 1 and thread group 2), paragraph 28, For threads in the same thread group (e.g. thread 0 through thread 3), a program counter is shared so that operations to be executed by each thread should be the same for a given clock cycle, paragraph 50, Thus, in a given cycle, all processing engine 802 in core 808 nominally executes the same instruction for different threads in the same thread group). However, Lo et al. do not expressly disclose implementing ray trace shading with improved cache locality, the branch instruction comprising target addresses to different shaders; and each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of the shaders.
Croxford et al., who also deal with parallel processing, disclose a method for implementing ray trace shading with improved cache locality (paragraph 226, the technology disclosed herein is also applicable to hybrid-ray tracing and raytracing).
Lo et al. and Croxford et al. are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of implementing ray trace shading with improved cache locality, as taught by Croxford et al., to the Lo et al. system, because this would implement additional methods of generating computer graphics besides rasterization.
Nevraev et al., who also deal with parallel processing, disclose a method for the branch instruction comprising target addresses to different shaders (paragraph 57, thread launcher 123 may select the pixel shader by specifying an entry point in GPU code corresponding to the pixel shader associated with the jump table slot value, and can accordingly branch to the associated pixel shader code, and/or may specify the memory location addresses for the pixel shader code).
Lo et al., Croxford et al., and Nevraev et al. are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method of the branch instruction comprising target addresses to different shaders, as taught by Nevraev et al., to the Lo et al. as modified by Croxford et al. system, because in generating the render target 44, the pixel shader stage 96 can appropriately position the samples from the respective outputs 131, 133 for rendering the portion of the primitive, which may be according to a steering mask, as described (paragraph 70 of Nevraev et al.).
Wu, who also deals with parallel processing, discloses a method wherein each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of the shaders (paragraph 8, selecting the branch jump information including the target instruction address from the branch jump history record with the highest priority).
Lo et al., Croxford et al., Nevraev et al., and Wu are in the same field of endeavor, namely computer architecture capable of processing computer graphics.
Before the effective filing date of the claimed invention, it would have been obvious to apply the method wherein each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of the shaders, as taught by Wu, to the Lo et al. as modified by Croxford et al. and Nevraev et al. system, because since the first branch jump history record is stored in the first processing core, the first processing core can obtain the branch jump information from the first branch jump history record at the fastest speed, which can provide a method for quickly reading the branch jump information (paragraph 8 of Wu).
With respect to claim 18, Lo et al. as modified by Croxford et al., Nevraev et al., and Wu disclose the non-transitory machine readable medium of claim 17, the branch instruction comprising target addresses to at least three different shaders (Nevraev et al.: paragraph 58, pixel shader selection can be performed by the GPU 12, which may execute code similar to the following in selecting the pixel shader 125 based on the received pixel shader parameter values, paragraph 59, the GPU 12 can select one pixel shader at pixel shader stage 96 and can indicate the jump table slot value (or related pixel shader parameter values) to the selected pixel shader. In this example, the compiler can generate code that can statically uniformly branch on the jump table slot value).
With respect to claim 19, Lo et al. as modified by Croxford et al., Nevraev et al., and Wu disclose the non-transitory machine readable medium of claim 17, wherein the pre-configured priority assigned to each of the shaders is based on an extent of instructions common among the shaders (Wu: paragraph 80, When the first thread and the second thread contain the same sub-function and the proportion of the same sub-function is greater than a preset ratio, it indicates that the first thread is similar to the second thread. The scheduling unit can send the first thread to the first processing core and send the second thread to the second processing core. The first processing core can generate a branch jump history record of the first processing core according to the jump instruction of the first thread, and the second processing core can generate a second branch jump history record according to the jump instruction of the second thread. In this way, the branch jump history records of the two processing cores contain some identical branch jump information). It would have been obvious to implement a pre-configured priority assigned to each of the shaders is based on an extent of instructions common among the shaders because this would efficiently utilize code.
With respect to claim 20, Lo et al. as modified by Croxford et al., Nevraev et al., and Wu disclose the non-transitory machine readable medium of claim 17, wherein the common code block is configured to determine a highest of the pre-configured priorities stored in per-thread registers of the thread sub-groups (Wu: paragraph 8, When more than two branch jump history records are found to include the target instruction address, the branch jump information may be selected according to the priority. Optionally, the priority of the first branch jump history record is higher than the priority of the second branch jump history record).
With respect to claim 21, Lo et al. as modified by Croxford et al., Nevraev et al., and Wu disclose the non-transitory machine readable medium of claim 20, wherein the common code block is further configured to store the highest of the pre-configured priorities in a shared register (Wu: paragraph 8, the first processing core selects branch jump information including the target instruction address from the first branch jump history record and the second branch jump history record).
Allowable Subject Matter
Claims 6 and 16 are objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter: none of the prior art teaches or suggests looping until the priorities satisfy the condition in claims 6 and 16, i.e., wherein the common code block is configured to loop until the corresponding one of the pre-configured priorities stored in the first per-thread register satisfies a comparison with the highest of the priorities stored in the shared register.
Response to Arguments
Applicant's arguments filed February 17, 2026 have been fully considered but they are not persuasive. Applicant argues that Lo is directed towards reducing static divergence by reassigning operands at compile time across threads/thread groups so that more threads within a group follow the same control (branch) path at execution time instead of a mechanism that determines which execution path is prioritized after a branch instruction is executed, namely branch target prioritization by configuring a loop in the threads to exit based on a pre-configured priority assigned to each of the multiple target addresses of the branch instruction (top of page 7 of remarks). However, Wu teaches each thread sub-group configuring the loop to exit based on a pre-configured priority assigned to each of multiple target addresses of the branch instruction (paragraph 8, selecting the branch jump information including the target instruction address from the branch jump history record with the highest priority). In response to applicant's arguments against the references individually, one cannot show nonobviousness by attacking references individually where the rejections are based on combinations of references. See In re Keller, 642 F.2d 413, 208 USPQ 871 (CCPA 1981); In re Merck & Co., 800 F.2d 1091, 231 USPQ 375 (Fed. Cir. 1986). Thus, it is the combination of Lo with Wu that teaches the claimed limitation as a whole.
Applicant argues that Lo does not teach a common code block of the threads configured to determine a highest of pre-configured priorities for target addresses of a branch instruction stored in per-thread registers, nor a teaching of thread sub-groups storing the highest priority in a shared register (page 7, second full paragraph). However, this limitation is taught by Wu. As explained above, it is the combination of Lo with Wu that teaches the claimed limitation as a whole.
Applicant argues that Lo does not teach for branch target priorities set according to resource consumption of target blocks or prioritizing branch targets comprising long-latency instructions, or prioritizing shaders based on extent of common instructions among shaders (bottom of page 7). However, this limitation is taught by Wu. As explained above, it is the combination of Lo with Wu that teaches the claimed limitation as a whole.
Applicant argues that Wu is directed to an entirely different problem and that Wu teaches multicore branch prediction using shared branch history/BTB records instead of mechanisms to thread-group execution ordering via branch-target prioritization (top of page 8). In response to applicant's argument that Wu is directed to an entirely different problem, a recitation of the intended use of the claimed invention must result in a structural difference between the claimed invention and the prior art in order to patentably distinguish the claimed invention from the prior art. If the prior art structure is capable of performing the intended use, then it meets the claim. In this case, Wu is capable of performing the intended method of the claimed invention, i.e., exiting a loop based on pre-configured priority assigned to each of multiple target addresses of the branch instruction. Applicant has not clearly articulated how Wu does not teach claimed limitation from claim 1.
Applicant argues that neither Lo nor Wu provides any disclosure of forming a plurality of converged thread sub-groups from a thread group executing a branch instruction, where each thread sub-group comprising a common code block to configure and execute a loop, and for each thread sub-group, configuring the loop to exit based on a pre-configured priority assigned to each of multiple target addresses of the branch instruction, in that Lo and Wu are directed to solving different problems, using different mechanisms (page 8, second and third full paragraphs). However, as explained above, if the prior art structure is capable of performing the intended use, then it meets the claim. Applicant has not clearly articulated how Lo nor Wu are incapable of performing the method directly recited in claim 1.
Applicant argues that prioritizing history records is not analogous to setting branch target priorities according to resource consumption of target blocks or prioritizing branch targets comprising long-latency instructions (top of page 9). However, the prioritizing of records is related to resource consumption; the closer processing core (quicker access) does not require as much resource consumption. Furthermore, it can be inferred the prioritized branch targets comprise long-latency instructions in order to avoid fetching instructions from a memory instead of a cache (Wu: paragraph 63, It should be understood that when the first processing core reads the instruction again based on the first jump address, the first processing core does not need to read it from memory, but can directly read the instruction from the processor cache, Wu: paragraph 64, The method of this embodiment can improve the success rate of obtaining branch jump information including the target address, thereby improving the accuracy of branch prediction, reducing pipeline interruptions, and thus improving instruction processing efficiency).
Applicant argues that Lo and Wu do not disclose the features of claim 9 (page 9, third full paragraph). However, the same arguments can be applied to claim 1, as previously explained.
Applicant argues that Chen does not teach a stack of loops implementing a hierarchy of prioritizations among branch targets (bottom of page 9). However, Chen discloses a plurality of loops, each with an iteration priority, which corresponds to a stack of loops implementing a hierarchy of prioritizations.
Applicant’s arguments directed towards claims 11 and 17-21 (page 10) are not persuasive because of similar reasons to claim 1, as previously explained.
Applicant argues that claim 19 is not obvious because the history-generating mechanisms are not analogous to assigning pre-configured priorities to branch targets for shaders based on an extent of instructions common among shaders (bottom of page 10 to top of page 11). However, Wu discloses when the first thread and second thread contain the same sub-function and the proportion of the same sub-function is greater than a preset ratio and assigning a priority based on the history record (paragraph 80), which is analogous to instructions common among shaders.
Applicant’s arguments with respect to claim(s) 7-8 have been considered but are moot because the new ground(s) of rejection.
Conclusion
The prior art made of record and not relied upon is considered pertinent to applicant's disclosure.
U.S. PGPUB 20090178044 to Musuvathi et al. for a method of evaluating a thread priority for exiting a loop.
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
Any inquiry concerning this communication or earlier communications from the examiner should be directed to ANDREW GUS YANG whose telephone number is (571)272-5514. The examiner can normally be reached M-F 9 AM - 5:30 PM.
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/ANDREW G YANG/Primary Examiner, Art Unit 2614
4/2/26