Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Drawings
The drawings are objected to under 37 CFR 1.83(a) because they fail to show "Portions of the STI that are located between the plurality of fins and portions of the STI that are located between the plurality of gate regions are isolated by the first spacer layer" as described in the specification and found in at least claims 1 and 9. Any structural detail that is essential for a proper understanding of the disclosed invention should be shown in the drawing. MPEP § 608.02(d). Corrected drawing sheets in compliance with 37 CFR 1.121(d) are required in reply to the Office action to avoid abandonment of the application. Any amended replacement drawing sheet should include all of the figures appearing on the immediate prior version of the sheet, even if only one figure is being amended. The figure or figure number of an amended drawing should not be labeled as “amended.” If a drawing figure is to be canceled, the appropriate figure must be removed from the replacement sheet, and where necessary, the remaining figures must be renumbered and appropriate changes made to the brief description of the several views of the drawings for consistency. Additional replacement sheets may be necessary to show the renumbering of the remaining figures. Each drawing sheet submitted after the filing date of an application must be labeled in the top margin as either “Replacement Sheet” or “New Sheet” pursuant to 37 CFR 1.121(d). If the changes are not accepted by the examiner, the applicant will be notified and informed of any required corrective action in the next Office action. The objection to the drawings will not be held in abeyance.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-20 are rejected under 35 U.S.C. 102(a)(2) as being anticipated by Wong et al. (US 20220310816 A1) hereinafter referred to as "Wong".
Regarding claim 1, Wong discloses a semiconductor device, comprising: a shallow trench isolation (STI) (fig. 15, element 68; pa. [0026]); a plurality of fins over the STI (fig. 15, element 66; pa. [0012], [0033]), wherein each of the plurality of fins comprises at least a source/drain region (fig. 18A, element 92; pa. [0013]); a plurality of gate regions (fig. 15, element 76; pa. [0013]); and a first spacer layer, wherein portions of the STI that are located between the plurality of fins and portions of the STI that are located between the plurality of gate regions are separated by the first spacer layer (fig. 15, element 91; pa. [0050]).
Regarding claim 2, Wong discloses portions of sidewalls of the plurality of gate regions and portions of sidewalls of the plurality of fins being isolated by a second spacer layer (fig. 15, element 93; pa. [0053]).
Regarding claim 3, Wong discloses the first spacer layer and the second spacer layer forming a continuous layer (pa. [0053]).
Regarding claim 4, Wong discloses the first spacer layer and the second spacer layer being made of a same material (pa. [0054]).
Regarding claim 5, Wong discloses the first spacer layer and the second spacer layer being made of a different material (pa. [0054]).
Regarding claim 6, Wong discloses the semiconductor device being a nanosheet field-effect transistor (pa. [0011]).
Regarding claim 7, Wong discloses the nanosheet FET including nanosheets of alternating layers of silicon and silicon germanium (fig. 15, element 52, 54; pa. [0049]).
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Regarding claim 8, Wong discloses a semiconductor device, comprising: a shallow trench isolation (STI) (fig. 15, element 68; pa. [0026]); a plurality of fins over the STI (fig. 15, element 66, pa. [0012], [0033]), wherein each of the plurality of fins comprises at least a source/drain region (fig. 18A, element 92; pa. [0013]); a plurality of gate regions (fig. 15, element 76; pa. [0013]); and a first spacer layer, wherein portions of sidewalls of the plurality of gate regions and portions of sidewalls of the plurality of fins are isolated by the first spacer layer (fig. 15, element 93; pa. [0053]).
Regarding claim 9, Wong discloses portions of the STI between the plurality of fins and portions of the STI between the plurality of gate regions are isolated by a second spacer layer (fig. 15, element 91; pa. [0050]).
Regarding claim 10, Wong discloses the first spacer layer and the second spacer layer forming a continuous layer (pa. [0053]).
Regarding claim 11, Wong discloses the first spacer layer and the second spacer layer being made of a same material (pa. [0054]).
Regarding claim 12, Wong discloses the first spacer layer and the second spacer layer being made of a different material (pa. [0054]).
Regarding claim 13, Wong discloses the semiconductor device being a nanosheet field-effect transistor (pa. [0011]).
Regarding claim 14, Wong discloses the nanosheet FET including nanosheets of alternating layers of silicon and silicon germanium (fig. 15, element 52, 54; pa. [0049]).
Regarding claim 15, Wong discloses a method for forming a semiconductor device, the method comprising: forming a shallow trench isolation (STI) (fig. 15, element 68; pa. [0026]); forming a plurality of fins over the STI (fig. 15, element 66; pa. [0012], [0033]), wherein forming each of the plurality of fins comprises forming at least a source/drain region (fig. 18A, element 92; pa. [0013]); forming a plurality of gate regions (fig. 15, element 76; pa. [0013]); forming a first spacer layer (fig. 15, element 91; pa. [0050]); and isolating portions of the STI that are located between the plurality of fins and portions of the STI that are located between the plurality of gate regions by the first spacer layer (Wong, pa: [0050]).
Regarding claim 16, Wong discloses isolating portions of sidewalls of the plurality of gate regions and portions of sidewalls of the plurality of fins by a second spacer layer (fig. 15, element 93; pa. [0053]).
Regarding claim 17, Wong discloses forming a continuous layer by connecting the first spacer layer and the second spacer layer (pa. [0053]).
Regarding claim 18, Wong discloses the first spacer layer and the second spacer layer being made of a same material (pa. [0054]).
Regarding claim 19, Wong discloses the first spacer layer and the second spacer layer being made of a different material (pa. [0054]).
Regarding claim 20, Wong discloses forming nanosheets of alternating layers of silicon and silicon germanium (fig. 15, element 52, 54; pa. [0049]).
Conclusion
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/I.H./Examiner, Art Unit 2899
/ZANDRA V SMITH/Supervisory Patent Examiner, Art Unit 2899
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