Notice of Pre-AIA or AIA Status
The present application, filed on or after March 16, 2013, is being examined under the first inventor to file provisions of the AIA .
Claim Rejections - 35 USC § 103
The text of those sections of Title 35, U.S. Code not included in this action can be found in a prior Office action.
Claim(s) 1, 3-5, 11-16, and 18-20 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN (United States Patent Application Publication US 2020/0183860), hereinafter CHEN, in view of Yim (United States Patent Application Publication US 2024/0143758), hereinafter Yim.
Regarding claim 1, CHEN teaches receiving, by a code, an indication of a persona associated with the device, wherein the device ([0014] “the processing device 100 may be a microcontroller (MCU) or a microprocessor (MPU).” [0017] “when the user needs to change or modify the functions of pins P1~P8 of the processing devic e…”) is associated with a first configuration that assigns a first physical input/output pin of the device to a first functionality associated with the device and a second physical input/output pin of the device to a second functionality associated with the device ([0016] “the register 120 may store the setting values corresponding to the pins Pl-PS of the processing device 100 to set the functions of pins P1~P8…each of the pins P1~P8 may be set to different functions.” [0024] “In step S210, a processor of the processing device 100 executes a first command stored in a memory device of the processing device 100 to generate initial setting values for setting the functions of a plurality of pins of the processing device 100.” Each pin of the processing device is set to have a function. Furthermore, a setting value indicates values for the assigned function of the corresponding pin.);
based on receiving the indication of the persona, modifying, by the code, configuration data associated with the SoC, wherein modifying the configuration data comprises configuring a pin multiplexer of the SoC to: disconnect the first physical input/output pin from the first functionality and connect the first physical input/output pin to the second functionality, and disconnect the second physical input/output pin from the second functionality and connect the second physical input/output pin to the first functionality ([0024] “In step S230, when the initial setting values need to be changed to change the function of one or more pins, the processor of the processing device 100 may executes a second command stored in a memory device of the processing device 100 to generate the second setting values for setting the functions of a plurality of pins of the processing device 100. In step S240, when the second setting values are written into the register of the processing device 100, the register of the processing device 100 may determine whether to replace the initial setting values with the second setting values according to each setting value of the second setting values” As the setting value for the function of one or more pins are changed, the function or persona of the pins of the processing device is changed. Then, based on the new setting values, the values of the registers are changed. Each value of the setting value corresponds to the function and the position of the setting values in the register corresponds to the pin. Thus, by changing a function of a first pin from a first value to a second value, the function of the first pin is disconnected from the first function and connected to the second function. Furthermore, a function of another pin can be changed from the second function to the first function.); and
subsequent to modifying the configuration data, enabling the device to operate in accordance with the configuration data ([0027] “the method for changing the functions of pins further comprise that after the setting values of the pins are changed, a multiplexer (MUX) circuit of the processing device 100 provides the data to the pins according to the updated setting values of pins.”).
However, CHEN does not teach a SoC and an isolated Root of Trust (RoT) code.
Yim teaches an isolated Root of Trust (RoT) code ([0051] “TPM may establish a root of trust that includes core components of IHS 200 that are validated as operating using instructions that originate from a trusted source.”) and a system-on-chip ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified Fender by incorporating the teaching of Yim of an isolated Root of Trust (RoT) code and a system-on-chip. As well known in the art before the effective filing date of the claimed invention, the RoT provides a secure and trusted base, which improves security. Also, the system-on-chip integrates various components into a single chip, which reduce power consumption and footprint. Therefore, it would be advantageous to incorporate the teaching of Yim of an isolated Root of Trust (RoT) code and a system-on-chip in order to improve security, reduce power consumption, and save space.
Regarding claim 3, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
CHEN, as modified above, further teaches wherein: the first configuration assigns a first register of the device to the first functionality, a first segment of the first register to a first setting associated with the first functionality, and a second segment of the first register to a second setting associated with the first functionality, and modifying the configuration data further comprises assigning the first segment to the second setting and the second segment to the first setting ([0021] “if the initial setting values of pins P1~P8 is 000000AB (i.e. the initial setting value of the function of pin Pl is function B, the initial setting value of the function of pin P2 is function A, and the initial setting values of the functions of other pins are function 0 (i.e. no function)), when the user determines to change the initial setting values of pins Pl-PS according to the second setting values 0000CD00 (i.e. the user only wants to change the setting value of the function of pin P3 to function D, and change the setting value of the function of pin P4 to function C), the register 120 may use the non-zero setting values of the second setting values to replace the initial setting values.”).
Yim teaches the SoC ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
Regarding claim 4, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
CHEN, as modified above, further teaches the first configuration assigns a first behavioral profile to the device, wherein the first behavioral profile is associated with a third functionality; and modifying the configuration data further comprises disabling the first behavioral profile ([0026] “the setting value corresponding to a first pin of the pins is a first value and in the second setting values, the setting value corresponding to the first pin is a non-zero value (e.g. a second value), when the register of the processing device 100 determines whether to replace the initial setting values with the second setting values, the register of the processing device 100 may replace the first value with the second value (i.e. change the setting value of the first pin from the first value to the second value), wherein the first value may be 0 or a non-zero value.” As the setting value is changed, the previous setting value is changed, which disables the previous setting.).
Yim teaches the SoC ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
Regarding claim 5, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
CHEN, as modified above, further teaches wherein: the first configuration assigns a first interconnect setting to an interconnect component associated with the device, wherein the interconnect component is configured to route internal signals between a plurality of components of the device, and modifying the configuration data further comprises disabling the first interconnect setting ([0026] “the setting value corresponding to a first pin of the pins is a first value and in the second setting values, the setting value corresponding to the first pin is a non-zero value (e.g. a second value), when the register of the processing device 100 determines whether to replace the initial setting values with the second setting values, the register of the processing device 100 may replace the first value with the second value (i.e. change the setting value of the first pin from the first value to the second value), wherein the first value may be 0 or a non-zero value.” Pins of the processing device are interconnects associated with the device, which also transmit data through the pins. Furthermore, by setting or changing the value to 0, the function of the pin is disabled.).
Yim teaches the SoC ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
Regarding claim(s) 11, and 13-15, the claim(s) 11, and 13-15 are the apparatus claims of the method claim(s) 1, and 3-5. The claim(s) 11, and 13-15 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, CHEN in view of Yim teaches all the limitations of the claim(s) 11, and 13-15.
Regarding claim(s) 16, and 18-20, the claim(s) 16, and 18-20 are the one or more non-transitory computer-readable media for operating a system-on-chip (SoC), the one or more non-transitory computer-readable media storing computer-executable instructions claims of the method claim(s) 1, and, 3-5. CHEN teaches the one or more non-transitory computer-readable media storing computer-executable instructions ([0030] “A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a "processor") such that the processor can read information (e.g., code) from and write information to the storage medium.”). The claim(s) 16, 19, and 20 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, Fender in view of Yim teaches all the limitations of the claim(s) 16, 19, and 20.
Claim(s) 2, 12, and 17 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of Yim as applied to claims 1, 11, and 16 above, and further in view of Jeon et al. (United States Patent Application Publication US 2023/0318606), hereinafter Jeon.
Regarding claim 2, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
Yim teaches the SoC ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
However, CHEN in view of Yim does not explicitly teach wherein the first configuration assigns a first register to the first functionality and a second register to the second functionality, and modifying the configuration data further comprises assigning the first register to the second functionality and the second register to the first functionality.
Jeon teaches wherein the first configuration assigns a first register to the first functionality and a second register to the second functionality, and modifying the configuration data further comprises assigning the first register to the second functionality and the second register to the first functionality ([0086] “Each of the plurality of functions Function 0 to Function N r gay be assigned to a system image.” [0091] “The PCie capabilities register may identify the function type of a PCie device and associated capabilities.” [0092] “The device capabilities register may identify PCie device function-specific capabilities.” [0209] “At operation S120, as described above with reference to FIGS. 10A and 11A, unassigned functions may be assigned to respective ports…a specific field of a PCie capability register indicating port assignment information for unassigned functions may be updated to a value indicating the corresponding port.” Jeon teaches a plurality of registers to indicate capability or functionality of PCIe devices. As the functions for ports are assigned, the registers are updated or modified for the assigned function.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN in view of Yim by incorporating the teaching of Jeon of the first configuration assigning a first register to the first functionality and a second register to the second functionality, and modifying the configuration data further comprises assigning the first register to the second functionality and the second register to the first functionality. As well known in the art before the effective filing date of the claimed invention, a register is a very small high-speed storage location that allows a processor to access quickly, which allows faster data access to improve performance. By having two registers for each functionality, access to each register allows to avoid slower memory access and to access multiple data simultaneously. Therefore, it would be advantageous to incorporate the teaching of Jeon the first configuration assigning a first register to the first functionality and a second register to the second functionality, and modifying the configuration data further comprises assigning the first register to the second functionality and the second register to the first functionality in order to improve performance.
Regarding claim(s) 12, the claim(s) 12 is the apparatus claim of the method claim(s) 2. The claim(s) 12 does not further teach or define the limitation over the limitations recited in the rejected claim above. Therefore, CHEN in view of Yim and further in view of Jeon teaches all the limitations of the claim(s) 12.
Regarding claim(s) 17, the claim(s) 17 is the one or more non-transitory computer-readable media for operating a system-on-chip (SoC), the one or more non-transitory computer-readable media storing computer-executable instructions claim of the method claim(s) 2. CHEN teaches the one or more non-transitory computer-readable media storing computer-executable instructions ([0030] “A sample storage medium may be coupled to a machine such as, for example, a computer/processor (which may be referred to herein, for convenience, as a "processor") such that the processor can read information (e.g., code) from and write information to the storage medium.”). The claim(s) 17 do not further teach or define the limitation over the limitations recited in the rejected claims above. Therefore, CHEN in view of Yim and further in view of Jeon teaches all the limitations of the claim(s) 17.
Claim(s) 8 and 9 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of Yim as applied to claim 1 above, and further in view of Fender et al. (United States Patent Application Publication US 2019/0146943), hereinafter Fender.
Regarding claim 8, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
Yim further teaches the isolated Root of Trust (RoT) code ([0051] “TPM may establish a root of trust that includes core components of IHS 200 that are validated as operating using instructions that originate from a trusted source.”) and the system-on-chip ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
However, CHEN in view of Yim does not teach wherein: the persona is associated with a first operational environment, wherein the first operational environment is defined based on at least one of a geographic region, a network type, or a system type; and the method further comprises: detecting, by code, that the chip is operating outside of the first operational environment; and based on detecting that the chip is operating outside the first operational environment, modifying the configuration data to disable the second configuration.
Fender teaches wherein: the persona is associated with a first operational environment, wherein the first operational environment is defined based on at least one of a geographic region, a network type, or a system type ([0025] “Each device persona of each circuit may include one for more pieces of device persona information that identifies the device persona. The device persona information may include information for a vendor identifier, a device identifier, a revision identifier, a programming interface identifier, a class code identifier, a base class code, a subsystem vendor identifier, a subsystem subclass code, identifiers for specific PCie capabilities such as SR-IOv, address translation services (ATS), Process Address Space ID (PASID), page request interface (PRI), other identifiers, or any combination of these identifiers”); and the method further comprises: detecting, by code, that the device is operating outside of the first operational environment; and based on detecting that the device is operating outside the first operational environment, modifying the configuration data to disable the second configuration ([0055] “After the hot-plug emulation software determines the PCie identity of the second circuit device, the hot-plug emulation software may load any appropriate drivers for the second circuit device. Thereafter, the second circuit device of the configurable IC die may operate in the host as a compliant PCie device.” As the persona change request needs environment or configuration including drivers to operate the second circuit device, a new environment for the second circuit device to operate is configured. Thus, the configuration data for the second circuit device not to operate is modified.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN in view of Yim by incorporating the teaching of Fender of detecting that the device is operating outside of the first operational environment; and based on detecting that the device is operating outside the first operational environment, modifying the configuration data to disable the second configuration. As recognized by Fender, as a new device is connected, a new software and a driver for the new device is required to operate properly. By a new environment of the newly connected device, required software and driver for the new device can be loaded, which enable the device to perform properly ([0055]). Therefore, it would be advantageous to incorporate the teaching of Fender of detecting that the device is operating outside of the first operational environment; and based on detecting that the device is operating outside the first operational environment, modifying the configuration data to disable the second configuration in order to operate the newly connected device properly.
Regarding claim 9, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
Yim further teaches the isolated Root of Trust (RoT) code ([0051] “TPM may establish a root of trust that includes core components of IHS 200 that are validated as operating using instructions that originate from a trusted source.”) and the system-on-chip ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
Fender teaches determining, by the code, a first operational environment by monitoring the chip; determining, by the code, that the first operational environment is incompatible with a second operational environment associated with the persona; and modifying a configuration associated with the device based on determining that the first operational environment is incompatible with the second operational environment ([0055] “After the hot-plug emulation software determines the PCie identity of the second circuit device, the hot-plug emulation software may load any appropriate drivers for the second circuit device. Thereafter, the second circuit device of the configurable IC die may operate in the host as a compliant PCie device.” As the persona change request needs environment or configuration including drivers to operate the second circuit device, a new environment for the second circuit device to operate is configured. Thus, the configuration data or the environment for the second circuit device to operate is modified.).
Claim(s) 6 and 7 are rejected under 35 U.S.C. 103 as being unpatentable over CHEN in view of Yim as applied to claim 1 above, and further in view of JP 2008500635 A, hereinafter JP.
Regarding claim 6, CHEN in view of Yim teaches all the limitations of the method of claim 1, as discussed above.
Yim further teaches the SoC ([0066] “all or a portion of the functionality provided by the illustrated components may instead be provided by components integrated into the one or more processor(s) 302 as an SoC.”).
However, CHEN in view of Yim does not teach wherein: the first configuration assigns a byte ordering to a first memory location associated with the chip, and modifying the configuration data comprises disabling the byte ordering in relation to the first memory location.
JP teaches wherein: the first configuration assigns a byte ordering to a first memory location associated with the chip, and modifying the configuration data comprises disabling the byte ordering in relation to the first memory location (Abstract “Endianness control in a data processing system includes starting an access to a peripheral, defining a first endianness control unit corresponding to the peripheral, and information transferred during access using the endianness control unit.” Page 13 “the peripheral endianness control register 154 selectively disables the endianness information provided by the master endianness control units 132 and 134 according to the values of the fields 300 and 302” TECH-SOLUTION “Endianness is therefore also called byte order” Endianness control in a data is to control access data in storage or memory using an endianness. Endianness is used to access the data in the memory. Therefore, by disabling the endianness information, the endianness is disabled in relation to a memory location.).
It would have been obvious to one of ordinary skill in the art before the effective filing date of the claimed invention to have modified CHEN in view of Yim by incorporating the teaching of JP of wherein: the first configuration assigns a byte ordering to a first memory location associated with the chip, and modifying the configuration data comprises disabling the byte ordering in relation to the first memory location. As recognized by JP, when data stored in memory is read with various endian formats, individual byes of different endian formats are reversed (TECH-SOLUTION Pages 3-4). Thus, by selecting a byte ordering in relation to a memory location, a flexible access to the memory can be provided. Therefore, it would be advantageous to incorporate the teaching of JP of wherein: the first configuration assigns a byte ordering to a first memory location associated with the chip, and modifying the configuration data comprises disabling the byte ordering in relation to the first memory location in order to provide the flexibility of the system.
Regarding claim 7, CHEN in view of Yim and further in view of JP teaches all the limitations of the method of claim 6, as discussed above.
JP further teaches wherein the byte ordering represents at least one of a big-endian ordering or a little-endian ordering (Page 3 “data can be stored in memory according to various endian formats, such as, for example, big endian format or little endian format…Endianness is therefore also called byte order.”).
Response to Arguments
Applicant’s arguments, see Remarks, filed 12/29/2025, with respect to “CLAIMS 3, 13, AND 18 COMPLY WITH 35 U.S.C. §112(B)” have been fully considered and are persuasive. The rejections of claims 3, 13, and 18 under 35 U.S.C. §112(b) has been withdrawn.
Applicant’s arguments, see Remarks, filed 12/29/2025, with respect to the rejection(s) of claim(s) 1, 4-5, 11, 14-16, 19, and 20 under 35 U.S.C. 103 have been fully considered and are persuasive. Therefore, the rejection has been withdrawn. However, upon further consideration, a new ground(s) of rejection is made in view of CHEN. CHEN teaches changing setting values of a register in order to change function of one or more pins.
Allowable Subject Matter
Claim 10 is objected to as being dependent upon a rejected base claim, but would be allowable if rewritten in independent form including all of the limitations of the base claim and any intervening claims.
The following is a statement of reasons for the indication of allowable subject matter:
CHEN teaches setting values in a register that indicates functions of pins of a processing device. However, CHEN does not teach “wherein modifying the configuration comprises modifying the configuration data to disable a third functionality that is associated with the first operational environment but not with the second operational environment.”
Jeon teaches a plurality of registers to indicate functionality and various information of ports. However, Jeon does not teach “wherein modifying the configuration comprises modifying the configuration data to disable a third functionality that is associated with the first operational environment but not with the second operational environment.”
Fender teaches hanging or reconfiguring a first circuit device and a second circuit device when a request to change persona is received. Fender further teaches to load any appropriate drivers for the second circuit to operate as a compliant PCIe device according to the persona change request. However, Fender does not teach “wherein modifying the configuration comprises modifying the configuration data to disable a third functionality that is associated with the first operational environment but not with the second operational environment.”
Conclusion
Applicant's amendment necessitated the new ground(s) of rejection presented in this Office action. Accordingly, THIS ACTION IS MADE FINAL. See MPEP § 706.07(a). Applicant is reminded of the extension of time policy as set forth in 37 CFR 1.136(a).
A shortened statutory period for reply to this final action is set to expire THREE MONTHS from the mailing date of this action. In the event a first reply is filed within TWO MONTHS of the mailing date of this final action and the advisory action is not mailed until after the end of the THREE-MONTH shortened statutory period, then the shortened statutory period will expire on the date the advisory action is mailed, and any nonprovisional extension fee (37 CFR 1.17(a)) pursuant to 37 CFR 1.136(a) will be calculated from the mailing date of the advisory action. In no event, however, will the statutory period for reply expire later than SIX MONTHS from the mailing date of this final action.
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/HYUN SOO KIM/Examiner, Art Unit 2176