DETAILED ACTION
Election/Restrictions
Applicant’s election without traverse of Invention I in the reply filed on 06/26/2026 is acknowledged. Claims 10-17 are withdrawn from further consideration pursuant to 37 CFR 1.142(b) as
being drawn to a nonelected method. Election was made without traverse in the reply filed on 06/26/2026.
Claim Rejections - 35 USC § 102
The following is a quotation of the appropriate paragraphs of 35 U.S.C. 102 that form the basis for the rejections under this section made in this Office action:
A person shall be entitled to a patent unless –
(a)(1) the claimed invention was patented, described in a printed publication, or in public use, on sale or otherwise available to the public before the effective filing date of the claimed invention.
(a)(2) the claimed invention was described in a patent issued under section 151, or in an application for patent published or deemed published under section 122(b), in which the patent or application, as the case may be, names another inventor and was effectively filed before the effective filing date of the claimed invention.
Claims 1-2 and 7-9 are rejected under 35 U.S.C. 102 (a)(1) as being anticipated by Chiu et al. (US 2023/0027792 A1; hereinafter “Chiu”).
In regard to claim 1, Chiu teaches a semiconductor device (a memory device 10 ) (Fig. 1 and paragraph 23), comprising:
a substrate (an inter-layer dielectric (ILD) layer 100A) (Fig. 1 and paragraph 24);
a metal layer (metallization patterns 100B) in contact with the substrate (Fig. 1 and paragraph 24);
an electrode (SOT bottom electrode 104) comprising tantalum (Ta) arranged on top of the metal layer (the SOT bottom electrode 104 includes tantalum (Ta)) (Fig. 1 and paragraph 26);
a diffusion barrier (a diffusion barrier layer 102) layer arranged between the electrode and the metal layer (the diffusion barrier layer 102 is shown between the metallization patterns 100B and SOT bottom electrode 104in Fig. 1) (Fig. 1 and paragraph 25),
wherein the diffusion barrier layer comprises a halogen-blocking material (the diffusion barrier layer 102 is formed from tantalum nitride which is a known halogen blocking material) (paragraph 25).
In regard to claim 2, Chiu teaches wherein the diffusion barrier layer comprises tantalum nitride (TaN) (the diffusion barrier layer 102 is formed from tantalum nitride) (paragraph 25).
In regard to claim 7, Chiu teaches wherein the metal layer comprises copper (Cu) (the metallization patterns 100B may be copper) (paragraph 24).
In regard to claim 8, Chiu teaches wherein the substrate comprises a patterned substrate (the inter-layer dielectric (ILD) layer is shown to be patterned in Fig. 1).
In regard to claim 9, Chiu teaches wherein the substrate comprises silicon (Si) or silicon nitride (SiN) (the ILD layer 100A may be silicon oxide) (paragraph 24).
Claim Rejections - 35 USC § 103
The following is a quotation of 35 U.S.C. 103 which forms the basis for all obviousness rejections set forth in this Office action:
A patent for a claimed invention may not be obtained, notwithstanding that the claimed invention is not identically disclosed as set forth in section 102, if the differences between the claimed invention and the prior art are such that the claimed invention as a whole would have been obvious before the effective filing date of the claimed invention to a person having ordinary skill in the art to which the claimed invention pertains. Patentability shall not be negated by the manner in which the invention was made.
Claim 3-4, 18 and 20 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu as applied to claim 1 above.
In regard to claim 3, Chiu teaches wherein the diffusion barrier layer has a height in a range of substantially 8 to 10 nm (the diffusion barrier layer 102 may have a thickness in a range from 1 nm to 1 μm, therefore the Examiner takes official notice that it would’ve been obvious for one skilled in the art to have a diffusion barrier with a thickness of 8nm to 10nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233).
In regard to claim 4, Chiu teaches wherein the diffusion barrier layer has a height in a range of 8 to 20 nm (the diffusion barrier layer 102 may have a thickness in a range from 1 nm to 1 μm, therefore the Examiner takes official notice that it would’ve been obvious for one skilled in the art to have a diffusion barrier with a thickness of 8nm to 10nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233).
In regard to claim 18, Chiu teaches a semiconductor device (a memory device 10 ) (Fig. 1 and paragraph 23), comprising:
a metal layer (metallization patterns 100B) (Fig. 1 and paragraph 24);
a magnetic tunnel junction stack (a lower MTJ stack MTJ2) arranged on the metal layer (Fig. 1 and paragraph 28);
an electrode (SOT bottom electrode 104) comprising tantalum (Ta) arranged on top of the metal layer (the SOT bottom electrode 104 includes tantalum (Ta)) (Fig. 1 and paragraph 26);
a diffusion barrier layer (a diffusion barrier layer 102) arranged between the electrode and the metal layer the diffusion barrier layer 102 is shown between the metallization patterns 100B and SOT bottom electrode 104in Fig. 1) (Fig. 1 and paragraph 25), wherein the diffusion barrier layer comprises a halogen gas-blocking material (the diffusion barrier layer 102 is formed from tantalum nitride which is a known halogen blocking material) (Fig. 1 and paragraph 25), wherein a thickness of the diffusion barrier layer is 8 to 10nm (the diffusion barrier layer 102 may have a thickness in a range from 1 nm to 1 μm, therefore the Examiner takes official notice that it would’ve been obvious for one skilled in the art to have a diffusion barrier with a thickness of 8nm to 10nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233).
In regard to claim 20, Chiu teaches wherein the diffusion barrier layer blocks fluorine (F), chlorine (Cl), and bromine (Br) gases from passing to the metal layer.
The Examiner notes recitation with respect to the manner in which a claimed apparatus is intended to be employed does not differentiate the claimed apparatus from a prior art apparatus if the prior art apparatus teaches all the structural limitations of the claim. Ex parte Masham, 2 USPQ2d 1647 (Bd. Pat. App. & Inter. 1987). Therefore, as the device of the prior art contains a diffusion barrier layer 102 formed from tantalum nitride, the claim is met.
Claims 1-2, 4-6, 18 and 19 are rejected under 35 U.S.C. 103 as being unpatentable over Chiu, and further in view of Chuang et al. (US 2022/0352457 A1; hereinafter “Chuang”).
In regard to claim 1, Chiu teaches a semiconductor device (a memory device 10 ) (Fig. 1 and paragraph 23), comprising:
a substrate (an inter-layer dielectric (ILD) layer 100A) (Fig. 1 and paragraph 24);
a metal layer (metallization patterns 100B) in contact with the substrate (Fig. 1 and paragraph 24);
an electrode (filling metal 111) comprising tantalum (Ta) arranged on top of the metal layer (the filling metal 111 is shown on top of the metallization patterns 100B) (Fig. 1 and paragraph 80);
a diffusion barrier (a diffusion barrier layer 110 is formed of Ta) layer arranged between the electrode and the metal layer (the diffusion barrier layer 110 is shown between the metallization patterns 100B and filling metal 111 in Fig. 1) (Fig. 1 and paragraph 80),
wherein the diffusion barrier layer comprises a halogen-blocking material (the diffusion barrier layer 110 is formed from tantalum nitride which is a known halogen blocking material) (paragraph 80).
However, Chiu doesn’t explicitly teach the electrode comprises tantalum (Ta).
Chuang teaches a semiconductor device (a memory device as shown in Fig. 19) (Fig. 19 and paragraph 5), comprising:
an electrode (a filling layer of conductive features 260) comprising tantalum (Ta) arranged on top of a metal layer (the filling layer of the conductive features 260 are formed of Tantalum and shown on top of conductive features 114formed of copper) (Fig. 19 and paragraphs 58-59).
It would’ve been obvious to one skilled in the art to combine the teachings of Chiu with the teachings of Chuang to have the electrode comprise tantalum (Ta) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use such as selecting a material because it is conductive, as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 2, Chiu teaches wherein the diffusion barrier layer comprises tantalum nitride (TaN) (the diffusion barrier layer 110 is formed from tantalum nitride) (paragraph 80).
In regard to claim 4, Chiu teaches wherein the diffusion barrier layer has a height in a range of 8 to 20 nm (the diffusion barrier layer 110 may have a thickness in a range from 1 nm to 1 μm along the z-axis) (paragraph 80), therefore the Examiner takes official notice that it would’ve been obvious for one skilled in the art to have a diffusion barrier with a thickness of 8nm to 10nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233).
In regard to claim 5, Chiu teaches further comprising an etch stop layer (a hard mask 124) arranged between the diffusion barrier layer and the metal layer (the hard mask 124 is shown between the diffusion barrier layer 110 and the metallization patterns 100B in Fig. 1), the etch stop layer extending over an upper portion of the substrate (the hard mask 124 is shown over the inter-layer dielectric (ILD) layer 100A in Fig. 1).
In regard to claim 6, Chiu teaches wherein the etch stop layer comprises ruthenium (Ru) (the hard mask 124 material includes Ru) (paragraph 72), and further comprising a magnetic tunnel junction stack (memory stack 105) formed between the metal layer and the etch stop layer (Fig. 1 and paragraph 72).
In regard to claim 18, Chiu teaches a semiconductor device (a memory device 10 ) (Fig. 1 and paragraph 23), comprising:
a metal layer (metallization patterns 100B) (Fig. 1 and paragraph 24);
a magnetic tunnel junction stack (a lower MTJ stack MTJ2) arranged on the metal layer (Fig. 1 and paragraph 28);
an electrode (filling metal 111) comprising tantalum (Ta) arranged on top of the metal layer (the filling metal 111 is shown on top of the metallization patterns 100B) (Fig. 1 and paragraph 80) (Fig. 1 and paragraph 26);
a diffusion barrier layer (a diffusion barrier layer 110 is formed of Ta) arranged between the electrode and the metal layer (the diffusion barrier layer 110 is shown between the metallization patterns 100B and filling metal 111 in Fig. 1) (Fig. 1 and paragraph 25), wherein the diffusion barrier layer comprises a halogen gas-blocking material (the diffusion barrier layer 110 is formed of Ta which is a known halogen gas-blocking material) (Fig. 1 and paragraph 25), wherein a thickness of the diffusion barrier layer is 8 to 10nm (the diffusion barrier layer 110 may have a thickness in a range from 1 nm to 1 μm (paragraph 80), therefore the Examiner takes official notice that it would’ve been obvious for one skilled in the art to have a diffusion barrier with a thickness of 8nm to 10nm since it has been held that where the general conditions of a claim are disclosed in the prior art, discovering the optimum or working ranges involves only routine skill in the art. In re Aller, 105 USPQ 233).
However, Chiu doesn’t explicitly teach the electrode comprises tantalum (Ta).
Chuang teaches a semiconductor device (a memory device as shown in Fig. 19) (Fig. 19 and paragraph 5), comprising:
an electrode (a filling layer of conductive features 260) comprising tantalum (Ta) arranged on top of a metal layer (the filling layer of the conductive features 260 are formed of Tantalum and shown on top of conductive features 114formed of copper) (Fig. 19 and paragraphs 58-59).
It would’ve been obvious to one skilled in the art to combine the teachings of Chiu with the teachings of Chuang to have the electrode comprise tantalum (Ta) since it has been held to be within the general skill of a worker in the art to select a known material on the basis of its suitability for the intended use such as selecting a material because it is conductive, as a matter of obvious design choice. In re Leshin, 125 USPQ 416.
In regard to claim 19, Chiu teaches the semiconductor device, further comprising an etch stop layer (a hard mask 124) arranged between the diffusion barrier layer and the metal layer (the hard mask 124 is shown between the diffusion barrier layer 110 and the metallization patterns 100B in Fig. 1), and wherein the electrode and the diffusion barrier layer are etched into a pillar shape by reactive ion etching (RIE) (the diffusion barrier layer 110 and filling metal 111 are shown in a pillar shape in Fig. 1). Further regarding the limitation “ by reactive ion etching (RIE), the Examiner notes the method of forming a device is not germane to the issue of patentability of the device itself. Therefore, this limitation has not been given patentable weight.
Conclusion
The following prior art made of record and not relied upon is considered pertinent to applicant's disclosure:
Chuang et al. US 2023/0189657 A1
Wu et al. US 2025/0318436 A1
Any inquiry concerning this communication or earlier communications from the examiner should be directed to SEYON ALI-SIMAH PUNCHBEDDELL whose telephone number is (571)270-0078. The examiner can normally be reached Mon-Thur: 7:30AM-3:30 PM.
Examiner interviews are available via telephone, in-person, and video conferencing using a USPTO supplied web-based collaboration tool. To schedule an interview, applicant is encouraged to use the USPTO Automated Interview Request (AIR) at http://www.uspto.gov/interviewpractice.
If attempts to reach the examiner by telephone are unsuccessful, the examiner’s supervisor, Sue Purvis can be reached at (571) 272-1236. The fax phone number for the organization where this application or proceeding is assigned is 571-273-8300.
Information regarding the status of published or unpublished applications may be obtained from Patent Center. Unpublished application information in Patent Center is available to registered users. To file and manage patent submissions in Patent Center, visit: https://patentcenter.uspto.gov. Visit https://www.uspto.gov/patents/apply/patent-center for more information about Patent Center and https://www.uspto.gov/patents/docx for information about filing in DOCX format. For additional questions, contact the Electronic Business Center (EBC) at 866-217-9197 (toll-free). If you would like assistance from a USPTO Customer Service Representative, call 800-786-9199 (IN USA OR CANADA) or 571-272-1000.
/SEYON ALI-SIMAH PUNCHBEDDELL/ Examiner, Art Unit 2893
/SUE A PURVIS/ Supervisory Patent Examiner, Art Unit 2893
Prosecution Insights